1 /*
2 * Copyright (c) 2012-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 * Christian Gmeiner <christian.gmeiner@gmail.com>
26 */
27
28 #include "etnaviv_screen.h"
29
30 #include "hw/common.xml.h"
31
32 #include "etnaviv_compiler.h"
33 #include "etnaviv_context.h"
34 #include "etnaviv_debug.h"
35 #include "etnaviv_fence.h"
36 #include "etnaviv_format.h"
37 #include "etnaviv_query.h"
38 #include "etnaviv_resource.h"
39 #include "etnaviv_translate.h"
40
41 #include "util/hash_table.h"
42 #include "util/os_time.h"
43 #include "util/u_math.h"
44 #include "util/u_memory.h"
45 #include "util/u_screen.h"
46 #include "util/u_string.h"
47
48 #include "frontend/drm_driver.h"
49
50 #include "drm-uapi/drm_fourcc.h"
51
52 #define ETNA_DRM_VERSION_FENCE_FD ETNA_DRM_VERSION(1, 1)
53 #define ETNA_DRM_VERSION_PERFMON ETNA_DRM_VERSION(1, 2)
54
55 static const struct debug_named_value etna_debug_options[] = {
56 {"dbg_msgs", ETNA_DBG_MSGS, "Print debug messages"},
57 {"drm_msgs", ETNA_DRM_MSGS, "Print drm messages"},
58 {"frame_msgs", ETNA_DBG_FRAME_MSGS, "Print frame messages"},
59 {"resource_msgs", ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
60 {"compiler_msgs", ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
61 {"linker_msgs", ETNA_DBG_LINKER_MSGS, "Print linker messages"},
62 {"ml_msgs", ETNA_DBG_ML_MSGS, "Print ML messages"},
63 {"dump_shaders", ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
64 {"no_ts", ETNA_DBG_NO_TS, "Disable TS"},
65 {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
66 {"no_supertile", ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
67 {"no_early_z", ETNA_DBG_NO_EARLY_Z, "Disable early z"},
68 {"cflush_all", ETNA_DBG_CFLUSH_ALL, "Flush every cache before state update"},
69 {"flush_all", ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
70 {"zero", ETNA_DBG_ZERO, "Zero all resources after allocation"},
71 {"draw_stall", ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
72 {"shaderdb", ETNA_DBG_SHADERDB, "Enable shaderdb output"},
73 {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF, "Disable single buffer feature"},
74 {"deqp", ETNA_DBG_DEQP, "Hacks to run dEQP GLES3 tests"}, /* needs MESA_GLES_VERSION_OVERRIDE=3.0 */
75 {"nocache", ETNA_DBG_NOCACHE, "Disable shader cache"},
76 {"linear_pe", ETNA_DBG_LINEAR_PE, "Enable linear PE"},
77 {"no_msaa", ETNA_DBG_NO_MSAA, "Disable MSAA support"},
78 {"shared_ts", ETNA_DBG_SHARED_TS, "Enable TS sharing"},
79 {"perf", ETNA_DBG_PERF, "Enable performance warnings"},
80 {"npu_parallel", ETNA_DBG_NPU_PARALLEL, "Enable parallelism inside NPU batches (unsafe)"},
81 {"npu_no_batching",ETNA_DBG_NPU_NO_BATCHING, "Disable batching NPU jobs"},
82 {"no_texdesc" ,ETNA_DBG_NO_TEXDESC, "Disable texture descriptor"},
83 DEBUG_NAMED_VALUE_END
84 };
85
86 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", etna_debug_options, 0)
87 int etna_mesa_debug = 0;
88
89 static void
etna_screen_destroy(struct pipe_screen * pscreen)90 etna_screen_destroy(struct pipe_screen *pscreen)
91 {
92 struct etna_screen *screen = etna_screen(pscreen);
93
94 if (screen->dummy_bo)
95 etna_bo_del(screen->dummy_bo);
96
97 if (screen->dummy_rt_reloc.bo)
98 etna_bo_del(screen->dummy_rt_reloc.bo);
99
100 if (screen->perfmon)
101 etna_perfmon_del(screen->perfmon);
102
103 util_dynarray_fini(&screen->supported_pm_queries);
104
105 etna_shader_screen_fini(pscreen);
106
107 if (screen->pipe_nn)
108 etna_pipe_del(screen->pipe_nn);
109
110 if (screen->pipe)
111 etna_pipe_del(screen->pipe);
112
113 if (screen->npu && screen->npu != screen->gpu)
114 etna_gpu_del(screen->npu);
115
116 if (screen->gpu)
117 etna_gpu_del(screen->gpu);
118
119 if (screen->ro)
120 screen->ro->destroy(screen->ro);
121
122 if (screen->dev)
123 etna_device_del(screen->dev);
124
125 FREE(screen);
126 }
127
128 static const char *
etna_screen_get_name(struct pipe_screen * pscreen)129 etna_screen_get_name(struct pipe_screen *pscreen)
130 {
131 struct etna_screen *priv = etna_screen(pscreen);
132 static char buffer[128];
133
134 snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->info->model,
135 priv->info->revision);
136
137 return buffer;
138 }
139
140 static const char *
etna_screen_get_vendor(struct pipe_screen * pscreen)141 etna_screen_get_vendor(struct pipe_screen *pscreen)
142 {
143 return "Mesa";
144 }
145
146 static const char *
etna_screen_get_device_vendor(struct pipe_screen * pscreen)147 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
148 {
149 return "Vivante";
150 }
151
152 static int
etna_screen_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)153 etna_screen_get_shader_param(struct pipe_screen *pscreen,
154 enum pipe_shader_type shader,
155 enum pipe_shader_cap param)
156 {
157 struct etna_screen *screen = etna_screen(pscreen);
158 bool ubo_enable = screen->info->halti >= 2;
159
160 if (DBG_ENABLED(ETNA_DBG_DEQP))
161 ubo_enable = true;
162
163 switch (shader) {
164 case PIPE_SHADER_FRAGMENT:
165 case PIPE_SHADER_VERTEX:
166 break;
167 case PIPE_SHADER_COMPUTE:
168 case PIPE_SHADER_GEOMETRY:
169 case PIPE_SHADER_TESS_CTRL:
170 case PIPE_SHADER_TESS_EVAL:
171 return 0;
172 default:
173 DBG("unknown shader type %d", shader);
174 return 0;
175 }
176
177 switch (param) {
178 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
179 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
180 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
181 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
182 return ETNA_MAX_TOKENS;
183 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
184 return ETNA_MAX_DEPTH; /* XXX */
185 case PIPE_SHADER_CAP_MAX_INPUTS:
186 /* Maximum number of inputs for the vertex shader is the number
187 * of vertex elements - each element defines one vertex shader
188 * input register. For the fragment shader, this is the number
189 * of varyings. */
190 return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
191 : screen->specs.vertex_max_elements;
192 case PIPE_SHADER_CAP_MAX_OUTPUTS:
193 return screen->specs.max_vs_outputs;
194 case PIPE_SHADER_CAP_MAX_TEMPS:
195 return 64; /* Max native temporaries. */
196 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
197 return ubo_enable ? ETNA_MAX_CONST_BUF : 1;
198 case PIPE_SHADER_CAP_CONT_SUPPORTED:
199 return 1;
200 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
201 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
202 return 1;
203 case PIPE_SHADER_CAP_SUBROUTINES:
204 return 0;
205 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
206 return VIV_FEATURE(screen, ETNA_FEATURE_HAS_SQRT_TRIG);
207 case PIPE_SHADER_CAP_INT64_ATOMICS:
208 case PIPE_SHADER_CAP_FP16:
209 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
210 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
211 case PIPE_SHADER_CAP_INT16:
212 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
213 return 0;
214 case PIPE_SHADER_CAP_INTEGERS:
215 return screen->info->halti >= 2;
216 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
217 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
218 return shader == PIPE_SHADER_FRAGMENT
219 ? screen->specs.fragment_sampler_count
220 : screen->specs.vertex_sampler_count;
221 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
222 if (ubo_enable)
223 return 16384; /* 16384 so state tracker enables UBOs */
224 return shader == PIPE_SHADER_FRAGMENT
225 ? screen->specs.max_ps_uniforms * sizeof(float[4])
226 : screen->specs.max_vs_uniforms * sizeof(float[4]);
227 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
228 return false;
229 case PIPE_SHADER_CAP_SUPPORTED_IRS:
230 return (1 << PIPE_SHADER_IR_TGSI) |
231 (1 << PIPE_SHADER_IR_NIR);
232 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
233 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
234 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
235 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
236 return 0;
237 }
238
239 debug_printf("unknown shader param %d", param);
240 return 0;
241 }
242
243 static void
etna_init_screen_caps(struct etna_screen * screen)244 etna_init_screen_caps(struct etna_screen *screen)
245 {
246 struct pipe_caps *caps = (struct pipe_caps *)&screen->base.caps;
247
248 u_init_pipe_screen_caps(&screen->base, 1);
249
250 /* Supported features (boolean caps). */
251 caps->blend_equation_separate = true;
252 caps->fs_coord_origin_upper_left = true;
253 caps->fs_coord_pixel_center_half_integer = true;
254 caps->fragment_shader_texture_lod = true;
255 caps->fragment_shader_derivatives = true;
256 caps->texture_barrier = true;
257 caps->quads_follow_provoking_vertex_convention = true;
258 caps->tgsi_texcoord = true;
259 caps->vertex_color_unclamped = true;
260 caps->mixed_color_depth_bits = true;
261 caps->mixed_framebuffer_sizes = true;
262 caps->string_marker = true;
263 caps->frontend_noop = true;
264 caps->framebuffer_no_attachment = true;
265 caps->vertex_input_alignment = PIPE_VERTEX_INPUT_ALIGNMENT_4BYTE;
266 caps->native_fence_fd = screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
267 caps->fs_position_is_sysval = true;
268 caps->fs_face_is_integer_sysval = true; /* note: not integer */
269 caps->fs_point_is_sysval = false;
270
271 /* Memory */
272 caps->constant_buffer_offset_alignment = 256;
273 caps->min_map_buffer_alignment = 4096;
274
275 caps->npot_textures = true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1, NON_POWER_OF_TWO); */
276
277 caps->anisotropic_filter =
278 caps->texture_swizzle =
279 caps->primitive_restart =
280 caps->primitive_restart_fixed_index = VIV_FEATURE(screen, ETNA_FEATURE_HALTI0);
281
282 caps->alpha_test = !VIV_FEATURE(screen, ETNA_FEATURE_PE_NO_ALPHA_TEST);
283
284 caps->draw_indirect = VIV_FEATURE(screen, ETNA_FEATURE_HALTI5);
285
286 /* Unsupported features. */
287 caps->texture_buffer_offset_alignment = false;
288 caps->texrect = false;
289
290 /* Stream output. */
291 caps->max_stream_output_buffers = DBG_ENABLED(ETNA_DBG_DEQP) ? 4 : 0;
292 caps->max_stream_output_separate_components = 0;
293 caps->max_stream_output_interleaved_components = 0;
294
295 caps->max_vertex_attrib_stride = 128;
296 caps->max_vertex_element_src_offset = 255;
297 caps->max_vertex_buffers = screen->info->gpu.stream_count;
298 caps->vs_instanceid =
299 caps->vertex_element_instance_divisor = VIV_FEATURE(screen, ETNA_FEATURE_HALTI2);
300
301
302 /* Texturing. */
303 caps->texture_half_float_linear = VIV_FEATURE(screen, ETNA_FEATURE_HALF_FLOAT);
304 caps->texture_shadow_map = true;
305 caps->max_texture_2d_size = screen->specs.max_texture_size;
306 caps->max_texture_array_layers =
307 screen->info->halti >= 0 ? screen->specs.max_texture_size : 0; /* TODO: verify */
308 unsigned log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
309 assert(log2_max_tex_size > 0);
310 caps->max_texture_3d_levels = screen->info->halti < 0 ? 0 : log2_max_tex_size;
311 caps->max_texture_cube_levels = log2_max_tex_size;
312
313 caps->min_texel_offset = -8;
314 caps->max_texel_offset = 7;
315 caps->seamless_cube_map_per_texture = screen->specs.seamless_cube_map;
316
317 /* Render targets. */
318 caps->max_render_targets = VIV_FEATURE(screen, ETNA_FEATURE_HALTI2) ?
319 /* If the GPU supports float formats we need to reserve half of
320 * the available render targets for emulation proposes.
321 */
322 screen->specs.num_rts / 2 :
323 screen->specs.num_rts;
324 caps->indep_blend_enable =
325 caps->indep_blend_func = screen->info->halti >= 5;
326
327 /* Queries. */
328 caps->occlusion_query =
329 caps->conditional_render =
330 caps->conditional_render_inverted = VIV_FEATURE(screen, ETNA_FEATURE_HALTI0);
331
332 /* Preferences */
333 caps->texture_transfer_modes = 0;
334 /* etnaviv is being run on systems as small as 256MB total RAM so
335 * we need to provide a sane value for such a device. Limit the
336 * memory budget to min(~3% of pyhiscal memory, 64MB).
337 *
338 * a simple divison by 32 provides the numbers we want.
339 * 256MB / 32 = 8MB
340 * 2048MB / 32 = 64MB
341 */
342 uint64_t system_memory;
343 if (!os_get_total_physical_memory(&system_memory))
344 system_memory = (uint64_t)4096 << 20;
345 caps->max_texture_upload_memory_budget = MIN2(system_memory / 32, 64 * 1024 * 1024);
346
347 caps->max_varyings = screen->specs.max_varyings;
348
349 /* Generate the bitmask of supported draw primitives. */
350 uint32_t modes = 1 << MESA_PRIM_POINTS |
351 1 << MESA_PRIM_LINES |
352 1 << MESA_PRIM_LINE_STRIP |
353 1 << MESA_PRIM_TRIANGLES |
354 1 << MESA_PRIM_TRIANGLE_FAN;
355
356 /* TODO: The bug relates only to indexed draws, but here we signal
357 * that there is no support for triangle strips at all. This should
358 * be refined.
359 */
360 if (VIV_FEATURE(screen, ETNA_FEATURE_BUG_FIXES8))
361 modes |= 1 << MESA_PRIM_TRIANGLE_STRIP;
362
363 if (VIV_FEATURE(screen, ETNA_FEATURE_LINE_LOOP))
364 modes |= 1 << MESA_PRIM_LINE_LOOP;
365
366 caps->supported_prim_modes =
367 caps->supported_prim_modes_with_restart = modes;
368
369 caps->pci_group =
370 caps->pci_bus =
371 caps->pci_device =
372 caps->pci_function = 0;
373 caps->video_memory = 0;
374 caps->uma = true;
375 caps->graphics = !VIV_FEATURE(screen, ETNA_FEATURE_COMPUTE_ONLY);
376
377 caps->min_line_width =
378 caps->min_line_width_aa =
379 caps->min_point_size =
380 caps->min_point_size_aa = 1;
381
382 caps->point_size_granularity =
383 caps->line_width_granularity = 0.1;
384
385 caps->max_line_width =
386 caps->max_line_width_aa =
387 caps->max_point_size =
388 caps->max_point_size_aa = 8192.0f;
389
390 caps->max_texture_anisotropy = 16.0f;
391 caps->max_texture_lod_bias = util_last_bit(screen->specs.max_texture_size);
392 }
393
394 static bool
gpu_supports_texture_target(struct etna_screen * screen,enum pipe_texture_target target)395 gpu_supports_texture_target(struct etna_screen *screen,
396 enum pipe_texture_target target)
397 {
398 if (target == PIPE_TEXTURE_CUBE_ARRAY)
399 return false;
400
401 /* pre-halti has no array/3D */
402 if (screen->info->halti < 0 &&
403 (target == PIPE_TEXTURE_1D_ARRAY ||
404 target == PIPE_TEXTURE_2D_ARRAY ||
405 target == PIPE_TEXTURE_3D))
406 return false;
407
408 return true;
409 }
410
411 static bool
gpu_supports_texture_format(struct etna_screen * screen,uint32_t fmt,enum pipe_format format)412 gpu_supports_texture_format(struct etna_screen *screen, uint32_t fmt,
413 enum pipe_format format)
414 {
415 bool supported = true;
416
417 /* Requires split sampler support, which the driver doesn't support, yet. */
418 if (!util_format_is_compressed(format) &&
419 util_format_get_blocksizebits(format) > 64)
420 return false;
421
422 if (fmt == TEXTURE_FORMAT_ETC1)
423 supported = VIV_FEATURE(screen, ETNA_FEATURE_ETC1_TEXTURE_COMPRESSION);
424
425 if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
426 supported = VIV_FEATURE(screen, ETNA_FEATURE_DXT_TEXTURE_COMPRESSION);
427
428 if (util_format_is_srgb(format))
429 supported = VIV_FEATURE(screen, ETNA_FEATURE_HALTI0);
430
431 if (fmt & EXT_FORMAT)
432 supported = VIV_FEATURE(screen, ETNA_FEATURE_HALTI0);
433
434 if (fmt & ASTC_FORMAT) {
435 supported = screen->specs.tex_astc;
436 }
437
438 if (util_format_is_snorm(format))
439 supported = VIV_FEATURE(screen, ETNA_FEATURE_HALTI1);
440
441 if (format != PIPE_FORMAT_S8_UINT_Z24_UNORM &&
442 (util_format_is_pure_integer(format) || util_format_is_float(format)))
443 supported = VIV_FEATURE(screen, ETNA_FEATURE_HALTI2);
444
445
446 if (!supported)
447 return false;
448
449 if (texture_format_needs_swiz(format))
450 return VIV_FEATURE(screen, ETNA_FEATURE_HALTI0);
451
452 return true;
453 }
454
455 static bool
gpu_supports_render_format(struct etna_screen * screen,enum pipe_format format,unsigned sample_count)456 gpu_supports_render_format(struct etna_screen *screen, enum pipe_format format,
457 unsigned sample_count)
458 {
459 const uint32_t fmt = translate_pe_format(format);
460
461 if (fmt == ETNA_NO_MATCH)
462 return false;
463
464 /* Requires split target support, which the driver doesn't support, yet. */
465 if (util_format_get_blocksizebits(format) > 64)
466 return false;
467
468 if (sample_count > 1) {
469 /* Explicitly disabled. */
470 if (DBG_ENABLED(ETNA_DBG_NO_MSAA))
471 return false;
472
473 /* The hardware supports it. */
474 if (!VIV_FEATURE(screen, ETNA_FEATURE_MSAA))
475 return false;
476
477 /* Number of samples must be allowed. */
478 if (!translate_samples_to_xyscale(sample_count, NULL, NULL))
479 return false;
480
481 /* On SMALL_MSAA hardware 2x MSAA does not work. */
482 if (sample_count == 2 && VIV_FEATURE(screen, ETNA_FEATURE_SMALL_MSAA))
483 return false;
484
485 /* BLT/RS supports the format. */
486 if (screen->specs.use_blt) {
487 if (translate_blt_format(format) == ETNA_NO_MATCH)
488 return false;
489 } else {
490 if (translate_rs_format(format) == ETNA_NO_MATCH)
491 return false;
492 }
493 }
494
495 if (format == PIPE_FORMAT_R8_UNORM)
496 return VIV_FEATURE(screen, ETNA_FEATURE_HALTI5);
497
498 /* figure out 8bpp RS clear to enable these formats */
499 if (format == PIPE_FORMAT_R8_SINT || format == PIPE_FORMAT_R8_UINT)
500 return VIV_FEATURE(screen, ETNA_FEATURE_HALTI5);
501
502 if (util_format_is_srgb(format))
503 return VIV_FEATURE(screen, ETNA_FEATURE_HALTI3);
504
505 if (util_format_is_pure_integer(format) || util_format_is_float(format))
506 return VIV_FEATURE(screen, ETNA_FEATURE_HALTI2);
507
508 if (format == PIPE_FORMAT_R8G8_UNORM)
509 return VIV_FEATURE(screen, ETNA_FEATURE_HALTI2);
510
511 /* any other extended format is HALTI0 (only R10G10B10A2?) */
512 if (fmt >= PE_FORMAT_R16F)
513 return VIV_FEATURE(screen, ETNA_FEATURE_HALTI0);
514
515 return true;
516 }
517
518 static bool
gpu_supports_vertex_format(struct etna_screen * screen,enum pipe_format format)519 gpu_supports_vertex_format(struct etna_screen *screen, enum pipe_format format)
520 {
521 if (translate_vertex_format_type(format) == ETNA_NO_MATCH)
522 return false;
523
524 if (util_format_is_pure_integer(format))
525 return VIV_FEATURE(screen, ETNA_FEATURE_HALTI2);
526
527 return true;
528 }
529
530 static bool
etna_screen_is_format_supported(struct pipe_screen * pscreen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned usage)531 etna_screen_is_format_supported(struct pipe_screen *pscreen,
532 enum pipe_format format,
533 enum pipe_texture_target target,
534 unsigned sample_count,
535 unsigned storage_sample_count,
536 unsigned usage)
537 {
538 struct etna_screen *screen = etna_screen(pscreen);
539 unsigned allowed = 0;
540
541 if (!gpu_supports_texture_target(screen, target))
542 return false;
543
544 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
545 return false;
546
547 /* For ARB_framebuffer_no_attachments - Short-circuit the rest of the logic. */
548 if (format == PIPE_FORMAT_NONE && usage & PIPE_BIND_RENDER_TARGET)
549 return true;
550
551 if (usage & PIPE_BIND_RENDER_TARGET) {
552 if (gpu_supports_render_format(screen, format, sample_count))
553 allowed |= PIPE_BIND_RENDER_TARGET;
554 }
555
556 if (usage & PIPE_BIND_DEPTH_STENCIL) {
557 if (translate_depth_format(format) != ETNA_NO_MATCH)
558 allowed |= PIPE_BIND_DEPTH_STENCIL;
559 }
560
561 if (usage & PIPE_BIND_SAMPLER_VIEW) {
562 uint32_t fmt = translate_texture_format(format);
563
564 if (!gpu_supports_texture_format(screen, fmt, format))
565 fmt = ETNA_NO_MATCH;
566
567 if (sample_count < 2 && fmt != ETNA_NO_MATCH)
568 allowed |= PIPE_BIND_SAMPLER_VIEW;
569 }
570
571 if (usage & PIPE_BIND_VERTEX_BUFFER) {
572 if (gpu_supports_vertex_format(screen, format))
573 allowed |= PIPE_BIND_VERTEX_BUFFER;
574 }
575
576 if (usage & PIPE_BIND_INDEX_BUFFER) {
577 /* must be supported index format */
578 if (format == PIPE_FORMAT_R8_UINT || format == PIPE_FORMAT_R16_UINT ||
579 (format == PIPE_FORMAT_R32_UINT &&
580 VIV_FEATURE(screen, ETNA_FEATURE_32_BIT_INDICES))) {
581 allowed |= PIPE_BIND_INDEX_BUFFER;
582 }
583 }
584
585 /* Always allowed */
586 allowed |=
587 usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
588
589 if (usage != allowed) {
590 DBG("not supported: format=%s, target=%d, sample_count=%d, "
591 "usage=%x, allowed=%x",
592 util_format_name(format), target, sample_count, usage, allowed);
593 }
594
595 return usage == allowed;
596 }
597
598 const uint64_t supported_modifiers[] = {
599 DRM_FORMAT_MOD_LINEAR,
600 DRM_FORMAT_MOD_VIVANTE_TILED,
601 DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
602 DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED,
603 DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED,
604 };
605
etna_get_num_modifiers(struct etna_screen * screen)606 static int etna_get_num_modifiers(struct etna_screen *screen)
607 {
608 int num = ARRAY_SIZE(supported_modifiers);
609
610 /* don't advertise split tiled formats on single pipe/buffer GPUs */
611 if (screen->specs.pixel_pipes == 1 || screen->specs.single_buffer)
612 num = 3;
613
614 return num;
615 }
616
617 static void
etna_screen_query_dmabuf_modifiers(struct pipe_screen * pscreen,enum pipe_format format,int max,uint64_t * modifiers,unsigned int * external_only,int * count)618 etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
619 enum pipe_format format, int max,
620 uint64_t *modifiers,
621 unsigned int *external_only, int *count)
622 {
623 struct etna_screen *screen = etna_screen(pscreen);
624 int num_base_mods = etna_get_num_modifiers(screen);
625 int mods_multiplier = 1;
626 int i, j;
627
628 if (DBG_ENABLED(ETNA_DBG_SHARED_TS) &&
629 VIV_FEATURE(screen, ETNA_FEATURE_FAST_CLEAR)) {
630 /* If TS is supported expose the TS modifiers. GPUs with feature
631 * CACHE128B256BPERLINE have both 128B and 256B color tile TS modes,
632 * older cores support exactly one TS layout.
633 */
634 if (VIV_FEATURE(screen, ETNA_FEATURE_CACHE128B256BPERLINE))
635 if (screen->specs.v4_compression &&
636 translate_ts_format(format) != ETNA_NO_MATCH)
637 mods_multiplier += 4;
638 else
639 mods_multiplier += 2;
640 else
641 mods_multiplier += 1;
642 }
643
644 if (max > num_base_mods * mods_multiplier)
645 max = num_base_mods * mods_multiplier;
646
647 if (!max) {
648 modifiers = NULL;
649 max = num_base_mods * mods_multiplier;
650 }
651
652 for (i = 0, *count = 0; *count < max && i < num_base_mods; i++) {
653 for (j = 0; *count < max && j < mods_multiplier; j++, (*count)++) {
654 uint64_t ts_mod;
655
656 if (j == 0) {
657 ts_mod = 0;
658 } else if (VIV_FEATURE(screen, ETNA_FEATURE_CACHE128B256BPERLINE)) {
659 switch (j) {
660 case 1:
661 ts_mod = VIVANTE_MOD_TS_128_4;
662 break;
663 case 2:
664 ts_mod = VIVANTE_MOD_TS_256_4;
665 break;
666 case 3:
667 ts_mod = VIVANTE_MOD_TS_128_4 | VIVANTE_MOD_COMP_DEC400;
668 break;
669 case 4:
670 ts_mod = VIVANTE_MOD_TS_256_4 | VIVANTE_MOD_COMP_DEC400;
671 }
672 } else {
673 if (screen->specs.bits_per_tile == 2)
674 ts_mod = VIVANTE_MOD_TS_64_2;
675 else
676 ts_mod = VIVANTE_MOD_TS_64_4;
677 }
678
679 if (modifiers)
680 modifiers[*count] = supported_modifiers[i] | ts_mod;
681 if (external_only)
682 external_only[*count] = util_format_is_yuv(format) ? 1 : 0;
683 }
684 }
685 }
686
687 static bool
etna_screen_is_dmabuf_modifier_supported(struct pipe_screen * pscreen,uint64_t modifier,enum pipe_format format,bool * external_only)688 etna_screen_is_dmabuf_modifier_supported(struct pipe_screen *pscreen,
689 uint64_t modifier,
690 enum pipe_format format,
691 bool *external_only)
692 {
693 struct etna_screen *screen = etna_screen(pscreen);
694 int num_base_mods = etna_get_num_modifiers(screen);
695 uint64_t base_mod = modifier & ~VIVANTE_MOD_EXT_MASK;
696 uint64_t ts_mod = modifier & VIVANTE_MOD_TS_MASK;
697 int i;
698
699 for (i = 0; i < num_base_mods; i++) {
700 if (base_mod != supported_modifiers[i])
701 continue;
702
703 if ((modifier & VIVANTE_MOD_COMP_DEC400) &&
704 (!screen->specs.v4_compression || translate_ts_format(format) == ETNA_NO_MATCH))
705 return false;
706
707 if (ts_mod) {
708 if (!VIV_FEATURE(screen, ETNA_FEATURE_FAST_CLEAR))
709 return false;
710
711 if (VIV_FEATURE(screen, ETNA_FEATURE_CACHE128B256BPERLINE)) {
712 if (ts_mod != VIVANTE_MOD_TS_128_4 &&
713 ts_mod != VIVANTE_MOD_TS_256_4)
714 return false;
715 } else {
716 if ((screen->specs.bits_per_tile == 2 &&
717 ts_mod != VIVANTE_MOD_TS_64_2) ||
718 (screen->specs.bits_per_tile == 4 &&
719 ts_mod != VIVANTE_MOD_TS_64_4))
720 return false;
721 }
722 }
723
724 if (external_only)
725 *external_only = util_format_is_yuv(format) ? 1 : 0;
726
727 return true;
728 }
729
730 return false;
731 }
732
733 static unsigned int
etna_screen_get_dmabuf_modifier_planes(struct pipe_screen * pscreen,uint64_t modifier,enum pipe_format format)734 etna_screen_get_dmabuf_modifier_planes(struct pipe_screen *pscreen,
735 uint64_t modifier,
736 enum pipe_format format)
737 {
738 unsigned planes = util_format_get_num_planes(format);
739
740 if (modifier & VIVANTE_MOD_TS_MASK)
741 return planes * 2;
742
743 return planes;
744 }
745
746 static void
etna_determine_num_rts(struct etna_screen * screen)747 etna_determine_num_rts(struct etna_screen *screen)
748 {
749 if (screen->info->halti >= 2)
750 screen->specs.num_rts = 8;
751 else if (screen->info->halti >= 0)
752 screen->specs.num_rts = 4;
753 else
754 screen->specs.num_rts = 1;
755 }
756
757 static void
etna_determine_uniform_limits(struct etna_screen * screen)758 etna_determine_uniform_limits(struct etna_screen *screen)
759 {
760 /* values for the non unified case are taken from
761 * gcmCONFIGUREUNIFORMS in the Vivante kernel driver file
762 * drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h.
763 */
764 if (screen->info->model == chipModel_GC2000 &&
765 (screen->info->revision == 0x5118 || screen->info->revision == 0x5140)) {
766 screen->specs.max_vs_uniforms = 256;
767 screen->specs.max_ps_uniforms = 64;
768 } else if (screen->info->gpu.num_constants == 320) {
769 screen->specs.max_vs_uniforms = 256;
770 screen->specs.max_ps_uniforms = 64;
771 } else if (screen->info->gpu.num_constants > 256 &&
772 screen->info->model == chipModel_GC1000) {
773 /* All GC1000 series chips can only support 64 uniforms for ps on non-unified const mode. */
774 screen->specs.max_vs_uniforms = 256;
775 screen->specs.max_ps_uniforms = 64;
776 } else if (screen->info->gpu.num_constants > 256) {
777 screen->specs.max_vs_uniforms = 256;
778 screen->specs.max_ps_uniforms = 256;
779 } else if (screen->info->gpu.num_constants == 256) {
780 screen->specs.max_vs_uniforms = 256;
781 screen->specs.max_ps_uniforms = 256;
782 } else {
783 screen->specs.max_vs_uniforms = 168;
784 screen->specs.max_ps_uniforms = 64;
785 }
786 }
787
788 static void
etna_determine_sampler_limits(struct etna_screen * screen)789 etna_determine_sampler_limits(struct etna_screen *screen)
790 {
791 /* vertex and fragment samplers live in one address space */
792 if (screen->info->halti >= 1) {
793 screen->specs.vertex_sampler_offset = 16;
794 screen->specs.fragment_sampler_count = 16;
795 screen->specs.vertex_sampler_count = 16;
796 } else {
797 screen->specs.vertex_sampler_offset = 8;
798 screen->specs.fragment_sampler_count = 8;
799 screen->specs.vertex_sampler_count = 4;
800 }
801
802 if (screen->info->model == 0x400)
803 screen->specs.vertex_sampler_count = 0;
804 }
805
806 static void
etna_get_specs(struct etna_screen * screen)807 etna_get_specs(struct etna_screen *screen)
808 {
809 const struct etna_core_info *info = screen->info;
810 uint32_t instruction_count = 0;
811
812 /* Copy all relevant limits from etna_core_info. */
813 if (info->type == ETNA_CORE_GPU) {
814 instruction_count = info->gpu.max_instructions;
815 screen->specs.pixel_pipes = info->gpu.pixel_pipes;
816
817 if (screen->npu)
818 info = etna_gpu_get_core_info(screen->npu);
819 }
820
821 if (info->type == ETNA_CORE_NPU) {
822 if (etna_core_has_feature(info, ETNA_FEATURE_NN_XYDP0))
823 screen->specs.nn_core_version = 8;
824 else if (etna_core_has_feature(info, ETNA_FEATURE_VIP_V7))
825 screen->specs.nn_core_version = 7;
826 else
827 screen->specs.nn_core_version = 6;
828 }
829
830 screen->info->halti = info->halti;
831 if (screen->info->halti >= 0)
832 DBG("etnaviv: GPU arch: HALTI%d", screen->info->halti);
833 else
834 DBG("etnaviv: GPU arch: pre-HALTI");
835
836 screen->specs.can_supertile =
837 VIV_FEATURE(screen, ETNA_FEATURE_SUPER_TILED);
838 screen->specs.bits_per_tile =
839 !VIV_FEATURE(screen, ETNA_FEATURE_2BITPERTILE) ||
840 VIV_FEATURE(screen, ETNA_FEATURE_CACHE128B256BPERLINE) ? 4 : 2;
841
842 screen->specs.ts_clear_value =
843 VIV_FEATURE(screen, ETNA_FEATURE_DEC400) ? 0xffffffff :
844 screen->specs.bits_per_tile == 4 ? 0x11111111 : 0x55555555;
845
846 screen->specs.vs_need_z_div =
847 screen->info->model < 0x1000 && screen->info->model != 0x880;
848 screen->specs.has_shader_range_registers =
849 screen->info->model >= 0x1000 || screen->info->model == 0x880;
850 screen->specs.has_new_transcendentals =
851 VIV_FEATURE(screen, ETNA_FEATURE_HAS_FAST_TRANSCENDENTALS);
852 screen->specs.has_no_oneconst_limit =
853 VIV_FEATURE(screen, ETNA_FEATURE_SH_NO_ONECONST_LIMIT);
854 screen->specs.v4_compression =
855 VIV_FEATURE(screen, ETNA_FEATURE_V4_COMPRESSION);
856 screen->specs.seamless_cube_map =
857 (screen->info->model != 0x880) && /* Seamless cubemap is broken on GC880? */
858 VIV_FEATURE(screen, ETNA_FEATURE_SEAMLESS_CUBE_MAP);
859
860 if (screen->info->halti >= 5) {
861 /* GC7000 - this core must load shaders from memory. */
862 screen->specs.vs_offset = 0;
863 screen->specs.ps_offset = 0;
864 screen->specs.max_instructions = 0; /* Do not program shaders manually */
865 screen->specs.has_icache = true;
866 } else if (VIV_FEATURE(screen, ETNA_FEATURE_INSTRUCTION_CACHE)) {
867 /* GC3000 - this core is capable of loading shaders from
868 * memory. It can also run shaders from registers, as a fallback, but
869 * "max_instructions" does not have the correct value. It has place for
870 * 2*256 instructions just like GC2000, but the offsets are slightly
871 * different.
872 */
873 screen->specs.vs_offset = 0xC000;
874 /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
875 * this mirror for writing PS instructions, probably safest to do the
876 * same.
877 */
878 screen->specs.ps_offset = 0x8000 + 0x1000;
879 screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */
880 screen->specs.has_icache = true;
881 } else {
882 if (instruction_count > 256) { /* unified instruction memory? */
883 screen->specs.vs_offset = 0xC000;
884 screen->specs.ps_offset = 0xD000; /* like vivante driver */
885 screen->specs.max_instructions = 256;
886 } else {
887 screen->specs.vs_offset = 0x4000;
888 screen->specs.ps_offset = 0x6000;
889 screen->specs.max_instructions = instruction_count;
890 }
891 screen->specs.has_icache = false;
892 }
893
894 if (VIV_FEATURE(screen, ETNA_FEATURE_HALTI0)) {
895 screen->specs.vertex_max_elements = 16;
896 } else {
897 /* Etna_viv documentation seems confused over the correct value
898 * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
899 * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
900 screen->specs.vertex_max_elements = 10;
901 }
902
903 etna_determine_num_rts(screen);
904 etna_determine_uniform_limits(screen);
905 etna_determine_sampler_limits(screen);
906
907 if (screen->info->halti >= 5) {
908 screen->specs.has_unified_uniforms = true;
909 screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0);
910 screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4);
911 } else if (screen->info->halti >= 1) {
912 /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess
913 */
914 screen->specs.has_unified_uniforms = true;
915 screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0);
916 /* hardcode PS uniforms to start after end of VS uniforms -
917 * for more flexibility this offset could be variable based on the
918 * shader.
919 */
920 screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4);
921 } else {
922 screen->specs.has_unified_uniforms = false;
923 screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0);
924 screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0);
925 }
926
927 screen->specs.max_vs_outputs = screen->info->halti >= 5 ? 32 : 16;
928
929 screen->specs.max_varyings = MIN3(ETNA_NUM_VARYINGS,
930 info->gpu.max_varyings,
931 /* one output slot used for position */
932 screen->specs.max_vs_outputs - 1);
933
934 screen->specs.max_texture_size =
935 VIV_FEATURE(screen, ETNA_FEATURE_TEXTURE_8K) ? 8192 : 2048;
936 screen->specs.max_rendertarget_size =
937 VIV_FEATURE(screen, ETNA_FEATURE_RENDERTARGET_8K) ? 8192 : 2048;
938
939 screen->specs.single_buffer = VIV_FEATURE(screen, ETNA_FEATURE_SINGLE_BUFFER);
940 if (screen->specs.single_buffer)
941 DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes);
942
943 screen->specs.tex_astc = VIV_FEATURE(screen, ETNA_FEATURE_TEXTURE_ASTC) &&
944 !VIV_FEATURE(screen, ETNA_FEATURE_NO_ASTC);
945
946 screen->specs.use_blt = VIV_FEATURE(screen, ETNA_FEATURE_BLT_ENGINE);
947
948 /* Only allow fast clear with MC2.0 or MMUv2, as the TS unit bypasses the
949 * memory offset for the MMUv1 linear window on MC1.0 and we have no way to
950 * fixup the address.
951 */
952 if (!VIV_FEATURE(screen, ETNA_FEATURE_MC20) &&
953 !VIV_FEATURE(screen, ETNA_FEATURE_MMU_VERSION))
954 etna_core_disable_feature(screen->info, ETNA_FEATURE_FAST_CLEAR);
955 }
956
957 struct etna_bo *
etna_screen_bo_from_handle(struct pipe_screen * pscreen,struct winsys_handle * whandle)958 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
959 struct winsys_handle *whandle)
960 {
961 struct etna_screen *screen = etna_screen(pscreen);
962 struct etna_bo *bo;
963
964 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
965 bo = etna_bo_from_name(screen->dev, whandle->handle);
966 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
967 bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
968 } else {
969 DBG("Attempt to import unsupported handle type %d", whandle->type);
970 return NULL;
971 }
972
973 if (!bo) {
974 DBG("ref name 0x%08x failed", whandle->handle);
975 return NULL;
976 }
977
978 return bo;
979 }
980
981 static const void *
etna_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)982 etna_get_compiler_options(struct pipe_screen *pscreen,
983 enum pipe_shader_ir ir, enum pipe_shader_type shader)
984 {
985 return etna_compiler_get_options(etna_screen(pscreen)->compiler);
986 }
987
988 static struct disk_cache *
etna_get_disk_shader_cache(struct pipe_screen * pscreen)989 etna_get_disk_shader_cache(struct pipe_screen *pscreen)
990 {
991 struct etna_screen *screen = etna_screen(pscreen);
992 struct etna_compiler *compiler = screen->compiler;
993
994 return compiler->disk_cache;
995 }
996
997 static int
etna_screen_get_fd(struct pipe_screen * pscreen)998 etna_screen_get_fd(struct pipe_screen *pscreen)
999 {
1000 struct etna_screen *screen = etna_screen(pscreen);
1001 return etna_device_fd(screen->dev);
1002 }
1003
1004 struct pipe_screen *
etna_screen_create(struct etna_device * dev,struct etna_gpu * gpu,struct etna_gpu * npu,struct renderonly * ro)1005 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
1006 struct etna_gpu *npu, struct renderonly *ro)
1007 {
1008 struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
1009 struct pipe_screen *pscreen;
1010
1011 if (!screen)
1012 return NULL;
1013
1014 if (!gpu)
1015 gpu = npu;
1016
1017 pscreen = &screen->base;
1018 screen->dev = dev;
1019 screen->gpu = gpu;
1020 screen->npu = npu;
1021 screen->ro = ro;
1022 screen->info = etna_gpu_get_core_info(gpu);
1023
1024 screen->drm_version = etnaviv_device_version(screen->dev);
1025 etna_mesa_debug = debug_get_option_etna_mesa_debug();
1026
1027 /* Disable autodisable for correct rendering with TS */
1028 etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE;
1029
1030 screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
1031 if (!screen->pipe) {
1032 DBG("could not create 3d pipe");
1033 goto fail;
1034 }
1035
1036 if (npu && gpu != npu) {
1037 screen->pipe_nn = etna_pipe_new(npu, ETNA_PIPE_3D);
1038 if (!screen->pipe_nn) {
1039 DBG("could not create nn pipe");
1040 goto fail;
1041 }
1042 }
1043
1044 /* apply debug options that disable individual features */
1045 if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z))
1046 etna_core_disable_feature(screen->info, ETNA_FEATURE_NO_EARLY_Z);
1047 if (DBG_ENABLED(ETNA_DBG_NO_TS))
1048 etna_core_disable_feature(screen->info, ETNA_FEATURE_FAST_CLEAR);
1049 if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE))
1050 etna_core_disable_feature(screen->info, ETNA_FEATURE_AUTO_DISABLE);
1051 if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE))
1052 etna_core_disable_feature(screen->info, ETNA_FEATURE_SUPER_TILED);
1053 if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF))
1054 etna_core_disable_feature(screen->info, ETNA_FEATURE_SINGLE_BUFFER);
1055 if (!DBG_ENABLED(ETNA_DBG_LINEAR_PE))
1056 etna_core_disable_feature(screen->info, ETNA_FEATURE_LINEAR_PE);
1057
1058 etna_get_specs(screen);
1059
1060 if (screen->info->halti >= 5 && !etnaviv_device_softpin_capable(dev)) {
1061 DBG("halti5 requires softpin");
1062 goto fail;
1063 }
1064
1065 pscreen->destroy = etna_screen_destroy;
1066 pscreen->get_screen_fd = etna_screen_get_fd;
1067 pscreen->get_shader_param = etna_screen_get_shader_param;
1068 pscreen->get_compiler_options = etna_get_compiler_options;
1069 pscreen->get_disk_shader_cache = etna_get_disk_shader_cache;
1070
1071 pscreen->get_name = etna_screen_get_name;
1072 pscreen->get_vendor = etna_screen_get_vendor;
1073 pscreen->get_device_vendor = etna_screen_get_device_vendor;
1074
1075 pscreen->context_create = etna_context_create;
1076 pscreen->is_format_supported = etna_screen_is_format_supported;
1077 pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers;
1078 pscreen->is_dmabuf_modifier_supported = etna_screen_is_dmabuf_modifier_supported;
1079 pscreen->get_dmabuf_modifier_planes = etna_screen_get_dmabuf_modifier_planes;
1080
1081 if (!etna_shader_screen_init(pscreen))
1082 goto fail;
1083
1084 etna_fence_screen_init(pscreen);
1085 etna_query_screen_init(pscreen);
1086 etna_resource_screen_init(pscreen);
1087
1088 etna_init_screen_caps(screen);
1089
1090 util_dynarray_init(&screen->supported_pm_queries, NULL);
1091 slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
1092
1093 if (screen->drm_version >= ETNA_DRM_VERSION_PERFMON)
1094 etna_pm_query_setup(screen);
1095
1096
1097 /* create dummy RT buffer, used when rendering with no color buffer */
1098 screen->dummy_bo = etna_bo_new(screen->dev, 64 * 64 * 4, DRM_ETNA_GEM_CACHE_WC);
1099 if (!screen->dummy_bo)
1100 goto fail;
1101
1102 screen->dummy_rt_reloc.bo = screen->dummy_bo;
1103 screen->dummy_rt_reloc.offset = 0;
1104 screen->dummy_rt_reloc.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
1105
1106 if (screen->info->halti >= 5) {
1107 void *buf;
1108
1109 /* create an empty dummy texture descriptor */
1110 screen->dummy_desc_reloc.bo = etna_bo_new(screen->dev, 0x100,
1111 DRM_ETNA_GEM_CACHE_WC);
1112 if (!screen->dummy_desc_reloc.bo)
1113 goto fail;
1114
1115 buf = etna_bo_map(screen->dummy_desc_reloc.bo);
1116 etna_bo_cpu_prep(screen->dummy_desc_reloc.bo, DRM_ETNA_PREP_WRITE);
1117 memset(buf, 0, 0x100);
1118 etna_bo_cpu_fini(screen->dummy_desc_reloc.bo);
1119 screen->dummy_desc_reloc.offset = 0;
1120 screen->dummy_desc_reloc.flags = ETNA_RELOC_READ;
1121 }
1122
1123 return pscreen;
1124
1125 fail:
1126 etna_screen_destroy(pscreen);
1127 return NULL;
1128 }
1129