1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * SPDX-License-Identifier: MIT
4 */
5
6 #include "r600_formats.h"
7 #include "r600_shader.h"
8 #include "r600_query.h"
9 #include "r600d_common.h"
10 #include "evergreend.h"
11
12 #include "pipe/p_shader_tokens.h"
13 #include "util/u_endian.h"
14 #include "util/u_pack_color.h"
15 #include "util/u_memory.h"
16 #include "util/u_framebuffer.h"
17 #include "util/u_dual_blend.h"
18 #include "evergreen_compute.h"
19 #include "util/u_math.h"
20
21 #include <assert.h>
22
evergreen_array_mode(unsigned mode)23 static inline unsigned evergreen_array_mode(unsigned mode)
24 {
25 switch (mode) {
26 default:
27 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED;
28 break;
29 case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1;
30 break;
31 case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1;
32 }
33 }
34
eg_num_banks(uint32_t nbanks)35 static uint32_t eg_num_banks(uint32_t nbanks)
36 {
37 switch (nbanks) {
38 case 2:
39 return 0;
40 case 4:
41 return 1;
42 case 8:
43 default:
44 return 2;
45 case 16:
46 return 3;
47 }
48 }
49
50
eg_tile_split(unsigned tile_split)51 static unsigned eg_tile_split(unsigned tile_split)
52 {
53 switch (tile_split) {
54 case 64: tile_split = 0; break;
55 case 128: tile_split = 1; break;
56 case 256: tile_split = 2; break;
57 case 512: tile_split = 3; break;
58 default:
59 case 1024: tile_split = 4; break;
60 case 2048: tile_split = 5; break;
61 case 4096: tile_split = 6; break;
62 }
63 return tile_split;
64 }
65
eg_macro_tile_aspect(unsigned macro_tile_aspect)66 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
67 {
68 switch (macro_tile_aspect) {
69 default:
70 case 1: macro_tile_aspect = 0; break;
71 case 2: macro_tile_aspect = 1; break;
72 case 4: macro_tile_aspect = 2; break;
73 case 8: macro_tile_aspect = 3; break;
74 }
75 return macro_tile_aspect;
76 }
77
eg_bank_wh(unsigned bankwh)78 static unsigned eg_bank_wh(unsigned bankwh)
79 {
80 switch (bankwh) {
81 default:
82 case 1: bankwh = 0; break;
83 case 2: bankwh = 1; break;
84 case 4: bankwh = 2; break;
85 case 8: bankwh = 3; break;
86 }
87 return bankwh;
88 }
89
r600_translate_blend_function(int blend_func)90 static uint32_t r600_translate_blend_function(int blend_func)
91 {
92 switch (blend_func) {
93 case PIPE_BLEND_ADD:
94 return V_028780_COMB_DST_PLUS_SRC;
95 case PIPE_BLEND_SUBTRACT:
96 return V_028780_COMB_SRC_MINUS_DST;
97 case PIPE_BLEND_REVERSE_SUBTRACT:
98 return V_028780_COMB_DST_MINUS_SRC;
99 case PIPE_BLEND_MIN:
100 return V_028780_COMB_MIN_DST_SRC;
101 case PIPE_BLEND_MAX:
102 return V_028780_COMB_MAX_DST_SRC;
103 default:
104 R600_ERR("Unknown blend function %d\n", blend_func);
105 assert(0);
106 break;
107 }
108 return 0;
109 }
110
r600_translate_blend_factor(int blend_fact)111 static uint32_t r600_translate_blend_factor(int blend_fact)
112 {
113 switch (blend_fact) {
114 case PIPE_BLENDFACTOR_ONE:
115 return V_028780_BLEND_ONE;
116 case PIPE_BLENDFACTOR_SRC_COLOR:
117 return V_028780_BLEND_SRC_COLOR;
118 case PIPE_BLENDFACTOR_SRC_ALPHA:
119 return V_028780_BLEND_SRC_ALPHA;
120 case PIPE_BLENDFACTOR_DST_ALPHA:
121 return V_028780_BLEND_DST_ALPHA;
122 case PIPE_BLENDFACTOR_DST_COLOR:
123 return V_028780_BLEND_DST_COLOR;
124 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
125 return V_028780_BLEND_SRC_ALPHA_SATURATE;
126 case PIPE_BLENDFACTOR_CONST_COLOR:
127 return V_028780_BLEND_CONST_COLOR;
128 case PIPE_BLENDFACTOR_CONST_ALPHA:
129 return V_028780_BLEND_CONST_ALPHA;
130 case PIPE_BLENDFACTOR_ZERO:
131 return V_028780_BLEND_ZERO;
132 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
133 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
134 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
135 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
136 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
137 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
138 case PIPE_BLENDFACTOR_INV_DST_COLOR:
139 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
140 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
141 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
142 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
143 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
144 case PIPE_BLENDFACTOR_SRC1_COLOR:
145 return V_028780_BLEND_SRC1_COLOR;
146 case PIPE_BLENDFACTOR_SRC1_ALPHA:
147 return V_028780_BLEND_SRC1_ALPHA;
148 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
149 return V_028780_BLEND_INV_SRC1_COLOR;
150 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
151 return V_028780_BLEND_INV_SRC1_ALPHA;
152 default:
153 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
154 assert(0);
155 break;
156 }
157 return 0;
158 }
159
r600_tex_dim(struct r600_texture * rtex,unsigned view_target,unsigned nr_samples)160 static unsigned r600_tex_dim(struct r600_texture *rtex,
161 unsigned view_target, unsigned nr_samples)
162 {
163 unsigned res_target = rtex->resource.b.b.target;
164
165 if (view_target == PIPE_TEXTURE_CUBE ||
166 view_target == PIPE_TEXTURE_CUBE_ARRAY)
167 res_target = view_target;
168 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
169 else if (res_target == PIPE_TEXTURE_CUBE ||
170 res_target == PIPE_TEXTURE_CUBE_ARRAY)
171 res_target = PIPE_TEXTURE_2D_ARRAY;
172
173 switch (res_target) {
174 default:
175 case PIPE_TEXTURE_1D:
176 return V_030000_SQ_TEX_DIM_1D;
177 case PIPE_TEXTURE_1D_ARRAY:
178 return V_030000_SQ_TEX_DIM_1D_ARRAY;
179 case PIPE_TEXTURE_2D:
180 case PIPE_TEXTURE_RECT:
181 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
182 V_030000_SQ_TEX_DIM_2D;
183 case PIPE_TEXTURE_2D_ARRAY:
184 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
185 V_030000_SQ_TEX_DIM_2D_ARRAY;
186 case PIPE_TEXTURE_3D:
187 return V_030000_SQ_TEX_DIM_3D;
188 case PIPE_TEXTURE_CUBE:
189 case PIPE_TEXTURE_CUBE_ARRAY:
190 return V_030000_SQ_TEX_DIM_CUBEMAP;
191 }
192 }
193
r600_translate_dbformat(enum pipe_format format)194 static uint32_t r600_translate_dbformat(enum pipe_format format)
195 {
196 switch (format) {
197 case PIPE_FORMAT_Z16_UNORM:
198 return V_028040_Z_16;
199 case PIPE_FORMAT_Z24X8_UNORM:
200 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
201 case PIPE_FORMAT_X8Z24_UNORM:
202 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
203 return V_028040_Z_24;
204 case PIPE_FORMAT_Z32_FLOAT:
205 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
206 return V_028040_Z_32_FLOAT;
207 default:
208 return ~0U;
209 }
210 }
211
r600_is_sampler_format_supported(struct pipe_screen * screen,enum pipe_format format)212 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
213 {
214 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
215 false) != ~0U;
216 }
217
r600_is_colorbuffer_format_supported(enum amd_gfx_level chip,enum pipe_format format)218 static bool r600_is_colorbuffer_format_supported(enum amd_gfx_level chip, enum pipe_format format)
219 {
220 return r600_translate_colorformat(chip, format, false) != ~0U &&
221 r600_translate_colorswap(format, false) != ~0U;
222 }
223
r600_is_zs_format_supported(enum pipe_format format)224 static bool r600_is_zs_format_supported(enum pipe_format format)
225 {
226 return r600_translate_dbformat(format) != ~0U;
227 }
228
evergreen_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned usage)229 bool evergreen_is_format_supported(struct pipe_screen *screen,
230 enum pipe_format format,
231 enum pipe_texture_target target,
232 unsigned sample_count,
233 unsigned storage_sample_count,
234 unsigned usage)
235 {
236 struct r600_screen *rscreen = (struct r600_screen*)screen;
237 unsigned retval = 0;
238
239 if (target >= PIPE_MAX_TEXTURE_TYPES) {
240 R600_ERR("r600: unsupported texture type %d\n", target);
241 return false;
242 }
243
244 if (util_format_get_num_planes(format) > 1)
245 return false;
246
247 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
248 return false;
249
250 if (sample_count > 1) {
251 if (!rscreen->has_msaa)
252 return false;
253
254 switch (sample_count) {
255 case 2:
256 case 4:
257 case 8:
258 break;
259 default:
260 return false;
261 }
262 }
263
264 if (usage & PIPE_BIND_SAMPLER_VIEW) {
265 if (target == PIPE_BUFFER) {
266 if (r600_is_buffer_format_supported(format, false))
267 retval |= PIPE_BIND_SAMPLER_VIEW;
268 } else {
269 if (r600_is_sampler_format_supported(screen, format))
270 retval |= PIPE_BIND_SAMPLER_VIEW;
271 }
272 }
273
274 if ((usage & (PIPE_BIND_RENDER_TARGET |
275 PIPE_BIND_DISPLAY_TARGET |
276 PIPE_BIND_SCANOUT |
277 PIPE_BIND_SHARED |
278 PIPE_BIND_BLENDABLE)) &&
279 r600_is_colorbuffer_format_supported(rscreen->b.gfx_level, format)) {
280 retval |= usage &
281 (PIPE_BIND_RENDER_TARGET |
282 PIPE_BIND_DISPLAY_TARGET |
283 PIPE_BIND_SCANOUT |
284 PIPE_BIND_SHARED);
285 if (!util_format_is_pure_integer(format) &&
286 !util_format_is_depth_or_stencil(format))
287 retval |= usage & PIPE_BIND_BLENDABLE;
288 }
289
290 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
291 r600_is_zs_format_supported(format)) {
292 retval |= PIPE_BIND_DEPTH_STENCIL;
293 }
294
295 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
296 r600_is_buffer_format_supported(format, true)) {
297 retval |= PIPE_BIND_VERTEX_BUFFER;
298 }
299
300 if (usage & PIPE_BIND_INDEX_BUFFER &&
301 r600_is_index_format_supported(format)) {
302 retval |= PIPE_BIND_INDEX_BUFFER;
303 }
304
305 if ((usage & PIPE_BIND_LINEAR) &&
306 !util_format_is_compressed(format) &&
307 !(usage & PIPE_BIND_DEPTH_STENCIL))
308 retval |= PIPE_BIND_LINEAR;
309
310 return retval == usage;
311 }
312
evergreen_create_blend_state_mode(struct pipe_context * ctx,const struct pipe_blend_state * state,int mode)313 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
314 const struct pipe_blend_state *state, int mode)
315 {
316 uint32_t color_control = 0, target_mask = 0;
317 uint32_t alpha_to_mask = 0;
318 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
319
320 if (!blend) {
321 return NULL;
322 }
323
324 r600_init_command_buffer(&blend->buffer, 20);
325 r600_init_command_buffer(&blend->buffer_no_blend, 20);
326
327 if (state->logicop_enable) {
328 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
329 } else {
330 color_control |= (0xcc << 16);
331 }
332 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
333 if (state->independent_blend_enable) {
334 for (int i = 0; i < 8; i++) {
335 target_mask |= (state->rt[i].colormask << (4 * i));
336 }
337 } else {
338 for (int i = 0; i < 8; i++) {
339 target_mask |= (state->rt[0].colormask << (4 * i));
340 }
341 }
342
343 /* only have dual source on MRT0 */
344 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
345 blend->cb_target_mask = target_mask;
346 blend->alpha_to_one = state->alpha_to_one;
347
348 if (target_mask)
349 color_control |= S_028808_MODE(mode);
350 else
351 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
352
353 r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
354
355 if (state->alpha_to_coverage) {
356 if (state->alpha_to_coverage_dither) {
357 alpha_to_mask = S_028B70_ALPHA_TO_MASK_ENABLE(1) |
358 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
359 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
360 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
361 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
362 S_028B70_OFFSET_ROUND(1);
363 } else {
364 alpha_to_mask = S_028B70_ALPHA_TO_MASK_ENABLE(1) |
365 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
366 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
367 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
368 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
369 S_028B70_OFFSET_ROUND(0);
370 }
371 }
372 r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK, alpha_to_mask);
373
374 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
375
376 /* Copy over the dwords set so far into buffer_no_blend.
377 * Only the CB_BLENDi_CONTROL registers must be set after this. */
378 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
379 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
380
381 for (int i = 0; i < 8; i++) {
382 /* state->rt entries > 0 only written if independent blending */
383 const int j = state->independent_blend_enable ? i : 0;
384
385 unsigned eqRGB = state->rt[j].rgb_func;
386 unsigned srcRGB = state->rt[j].rgb_src_factor;
387 unsigned dstRGB = state->rt[j].rgb_dst_factor;
388 unsigned eqA = state->rt[j].alpha_func;
389 unsigned srcA = state->rt[j].alpha_src_factor;
390 unsigned dstA = state->rt[j].alpha_dst_factor;
391 uint32_t bc = 0;
392
393 r600_store_value(&blend->buffer_no_blend, 0);
394
395 if (!state->rt[j].blend_enable) {
396 r600_store_value(&blend->buffer, 0);
397 continue;
398 }
399
400 bc |= S_028780_BLEND_CONTROL_ENABLE(1);
401 bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
402 bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
403 bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
404
405 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
406 bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
407 bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
408 bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
409 bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
410 }
411 r600_store_value(&blend->buffer, bc);
412 }
413 return blend;
414 }
415
evergreen_create_blend_state(struct pipe_context * ctx,const struct pipe_blend_state * state)416 static void *evergreen_create_blend_state(struct pipe_context *ctx,
417 const struct pipe_blend_state *state)
418 {
419
420 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
421 }
422
evergreen_create_dsa_state(struct pipe_context * ctx,const struct pipe_depth_stencil_alpha_state * state)423 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
424 const struct pipe_depth_stencil_alpha_state *state)
425 {
426 unsigned db_depth_control, alpha_test_control, alpha_ref;
427 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
428
429 if (!dsa) {
430 return NULL;
431 }
432
433 r600_init_command_buffer(&dsa->buffer, 3);
434
435 dsa->valuemask[0] = state->stencil[0].valuemask;
436 dsa->valuemask[1] = state->stencil[1].valuemask;
437 dsa->writemask[0] = state->stencil[0].writemask;
438 dsa->writemask[1] = state->stencil[1].writemask;
439 dsa->zwritemask = state->depth_writemask;
440
441 db_depth_control = S_028800_Z_ENABLE(state->depth_enabled) |
442 S_028800_Z_WRITE_ENABLE(state->depth_writemask) |
443 S_028800_ZFUNC(state->depth_func);
444
445 /* stencil */
446 if (state->stencil[0].enabled) {
447 db_depth_control |= S_028800_STENCIL_ENABLE(1);
448 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
449 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
450 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
451 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
452
453 if (state->stencil[1].enabled) {
454 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
455 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
456 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
457 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
458 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
459 }
460 }
461
462 /* alpha */
463 alpha_test_control = 0;
464 alpha_ref = 0;
465 if (state->alpha_enabled) {
466 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha_func);
467 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
468 alpha_ref = fui(state->alpha_ref_value);
469 }
470 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
471 dsa->alpha_ref = alpha_ref;
472
473 /* misc */
474 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
475 return dsa;
476 }
477
evergreen_create_rs_state(struct pipe_context * ctx,const struct pipe_rasterizer_state * state)478 static void *evergreen_create_rs_state(struct pipe_context *ctx,
479 const struct pipe_rasterizer_state *state)
480 {
481 struct r600_context *rctx = (struct r600_context *)ctx;
482 unsigned tmp, spi_interp;
483 float psize_min, psize_max;
484 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
485
486 if (!rs) {
487 return NULL;
488 }
489
490 r600_init_command_buffer(&rs->buffer, 30);
491
492 rs->scissor_enable = state->scissor;
493 rs->clip_halfz = state->clip_halfz;
494 rs->flatshade = state->flatshade;
495 rs->sprite_coord_enable = state->sprite_coord_enable;
496 rs->rasterizer_discard = state->rasterizer_discard;
497 rs->two_side = state->light_twoside;
498 rs->clip_plane_enable = state->clip_plane_enable;
499 rs->pa_sc_line_stipple = state->line_stipple_enable ?
500 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
501 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
502 rs->pa_cl_clip_cntl =
503 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
504 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
505 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
506 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
507 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
508 rs->multisample_enable = state->multisample;
509
510 /* offset */
511 rs->offset_units = state->offset_units;
512 rs->offset_scale = state->offset_scale * 16.0f;
513 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
514 rs->offset_units_unscaled = state->offset_units_unscaled;
515
516 if (state->point_size_per_vertex) {
517 psize_min = util_get_min_point_size(state);
518 psize_max = 8192;
519 } else {
520 /* Force the point size to be as if the vertex output was disabled. */
521 psize_min = state->point_size;
522 psize_max = state->point_size;
523 }
524
525 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
526 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
527 S_0286D4_PNT_SPRITE_OVRD_X(2) |
528 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
529 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
530 S_0286D4_PNT_SPRITE_OVRD_W(1);
531 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
532 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
533 }
534
535 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
536 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel) */
537 tmp = r600_pack_float_12p4(state->point_size/2);
538 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
539 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
540 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
541 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
542 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
543 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
544 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
545
546 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
547 r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0,
548 S_028A48_MSAA_ENABLE(state->multisample) |
549 S_028A48_VPORT_SCISSOR_ENABLE(1) |
550 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
551
552 if (rctx->b.gfx_level == CAYMAN) {
553 r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
554 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
555 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
556 } else {
557 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
558 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
559 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
560 }
561
562 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
563 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
564 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
565 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
566 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
567 S_028814_FACE(!state->front_ccw) |
568 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
569 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
570 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
571 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
572 state->fill_back != PIPE_POLYGON_MODE_FILL) |
573 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
574 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
575 return rs;
576 }
577
evergreen_create_sampler_state(struct pipe_context * ctx,const struct pipe_sampler_state * state)578 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
579 const struct pipe_sampler_state *state)
580 {
581 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
582 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
583 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
584 : state->max_anisotropy;
585 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
586 bool trunc_coord = state->min_img_filter == PIPE_TEX_FILTER_NEAREST &&
587 state->mag_img_filter == PIPE_TEX_FILTER_NEAREST;
588 float max_lod = state->max_lod;
589
590 if (!ss) {
591 return NULL;
592 }
593
594 /* If the min_mip_filter is NONE, then the texture has no mipmapping and
595 * MIP_FILTER will also be set to NONE. However, if more then one LOD is
596 * configured, then the texture lookup seems to fail for some specific texture
597 * formats. Forcing the number of LODs to one in this case fixes it. */
598 if (state->min_mip_filter == PIPE_TEX_MIPFILTER_NONE &&
599 state->mag_img_filter == state->min_img_filter)
600 max_lod = state->min_lod;
601
602 ss->border_color_use = sampler_state_needs_border_color(state);
603
604 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
605 ss->tex_sampler_words[0] =
606 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
607 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
608 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
609 S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
610 S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
611 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
612 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
613 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
614 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
615 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
616 ss->tex_sampler_words[1] =
617 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
618 S_03C004_MAX_LOD(S_FIXED(CLAMP(max_lod, 0, 15), 8));
619 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
620 ss->tex_sampler_words[2] =
621 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
622 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
623 S_03C008_TRUNCATE_COORD(trunc_coord) |
624 S_03C008_TYPE(1);
625
626 if (ss->border_color_use) {
627 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
628 }
629 return ss;
630 }
631
632 struct eg_buf_res_params {
633 enum pipe_format pipe_format;
634 unsigned offset;
635 unsigned size;
636 unsigned char swizzle[4];
637 bool uncached;
638 bool force_swizzle;
639 bool size_in_bytes;
640 };
641
evergreen_fill_buffer_resource_words(struct r600_context * rctx,struct pipe_resource * buffer,struct eg_buf_res_params * params,bool * skip_mip_address_reloc,unsigned tex_resource_words[8])642 static void evergreen_fill_buffer_resource_words(struct r600_context *rctx,
643 struct pipe_resource *buffer,
644 struct eg_buf_res_params *params,
645 bool *skip_mip_address_reloc,
646 unsigned tex_resource_words[8])
647 {
648 struct r600_texture *tmp = (struct r600_texture*)buffer;
649 uint64_t va;
650 int stride = util_format_get_blocksize(params->pipe_format);
651 unsigned format, num_format, format_comp, endian;
652 unsigned swizzle_res;
653 const struct util_format_description *desc;
654
655 r600_vertex_data_type(params->pipe_format,
656 &format, &num_format, &format_comp,
657 &endian);
658
659 desc = util_format_description(params->pipe_format);
660
661 if (params->force_swizzle)
662 swizzle_res = r600_get_swizzle_combined(params->swizzle, NULL, true);
663 else
664 swizzle_res = r600_get_swizzle_combined(desc->swizzle, params->swizzle, true);
665
666 va = tmp->resource.gpu_address + params->offset;
667 *skip_mip_address_reloc = true;
668 tex_resource_words[0] = va;
669 tex_resource_words[1] = params->size - 1;
670 tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
671 S_030008_STRIDE(stride) |
672 S_030008_DATA_FORMAT(format) |
673 S_030008_NUM_FORMAT_ALL(num_format) |
674 S_030008_FORMAT_COMP_ALL(format_comp) |
675 S_030008_ENDIAN_SWAP(endian);
676 tex_resource_words[3] = swizzle_res | S_03000C_UNCACHED(params->uncached);
677 /*
678 * dword 4 is for number of elements, for use with resinfo,
679 * albeit the amd gpu shader analyser
680 * uses a const buffer to store the element sizes for buffer txq
681 */
682 tex_resource_words[4] = params->size_in_bytes ? params->size : (params->size / stride);
683
684 tex_resource_words[5] = tex_resource_words[6] = 0;
685 tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
686 }
687
688 static struct pipe_sampler_view *
texture_buffer_sampler_view(struct r600_context * rctx,struct r600_pipe_sampler_view * view,unsigned width0,unsigned height0)689 texture_buffer_sampler_view(struct r600_context *rctx,
690 struct r600_pipe_sampler_view *view,
691 unsigned width0, unsigned height0)
692 {
693 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
694 struct eg_buf_res_params params;
695
696 memset(¶ms, 0, sizeof(params));
697
698 params.pipe_format = view->base.format;
699 params.offset = view->base.u.buf.offset;
700 params.size = view->base.u.buf.size;
701 params.swizzle[0] = view->base.swizzle_r;
702 params.swizzle[1] = view->base.swizzle_g;
703 params.swizzle[2] = view->base.swizzle_b;
704 params.swizzle[3] = view->base.swizzle_a;
705
706 evergreen_fill_buffer_resource_words(rctx, view->base.texture,
707 ¶ms, &view->skip_mip_address_reloc,
708 view->tex_resource_words);
709 view->tex_resource = &tmp->resource;
710
711 if (tmp->resource.gpu_address)
712 list_addtail(&view->list, &rctx->texture_buffers);
713 return &view->base;
714 }
715
716 struct eg_tex_res_params {
717 enum pipe_format pipe_format;
718 int force_level;
719 unsigned width0;
720 unsigned height0;
721 unsigned first_level;
722 unsigned last_level;
723 unsigned first_layer;
724 unsigned last_layer;
725 unsigned target;
726 unsigned char swizzle[4];
727 };
728
evergreen_fill_tex_resource_words(struct r600_context * rctx,struct pipe_resource * texture,struct eg_tex_res_params * params,bool * skip_mip_address_reloc,unsigned tex_resource_words[8])729 static int evergreen_fill_tex_resource_words(struct r600_context *rctx,
730 struct pipe_resource *texture,
731 struct eg_tex_res_params *params,
732 bool *skip_mip_address_reloc,
733 unsigned tex_resource_words[8])
734 {
735 struct r600_screen *rscreen = (struct r600_screen*)rctx->b.b.screen;
736 struct r600_texture *tmp = (struct r600_texture*)texture;
737 unsigned format, endian;
738 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
739 unsigned char array_mode = 0, non_disp_tiling = 0;
740 unsigned height, depth, width;
741 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
742 struct legacy_surf_level *surflevel;
743 unsigned base_level, first_level, last_level;
744 unsigned dim, last_layer;
745 uint64_t va;
746 bool do_endian_swap = false;
747
748 tile_split = tmp->surface.u.legacy.tile_split;
749 surflevel = tmp->surface.u.legacy.level;
750
751 /* Texturing with separate depth and stencil. */
752 if (tmp->db_compatible) {
753 switch (params->pipe_format) {
754 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
755 params->pipe_format = PIPE_FORMAT_Z32_FLOAT;
756 break;
757 case PIPE_FORMAT_X8Z24_UNORM:
758 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
759 /* Z24 is always stored like this for DB
760 * compatibility.
761 */
762 params->pipe_format = PIPE_FORMAT_Z24X8_UNORM;
763 break;
764 case PIPE_FORMAT_X24S8_UINT:
765 case PIPE_FORMAT_S8X24_UINT:
766 case PIPE_FORMAT_X32_S8X24_UINT:
767 params->pipe_format = PIPE_FORMAT_S8_UINT;
768 tile_split = tmp->surface.u.legacy.stencil_tile_split;
769 surflevel = tmp->surface.u.legacy.zs.stencil_level;
770 break;
771 default:;
772 }
773 }
774
775 if (UTIL_ARCH_BIG_ENDIAN)
776 do_endian_swap = !tmp->db_compatible;
777
778 format = r600_translate_texformat(rctx->b.b.screen, params->pipe_format,
779 params->swizzle,
780 &word4, &yuv_format, do_endian_swap);
781 assert(format != ~0);
782 if (format == ~0) {
783 return -1;
784 }
785
786 endian = r600_colorformat_endian_swap(format, do_endian_swap);
787
788 base_level = 0;
789 first_level = params->first_level;
790 last_level = params->last_level;
791 width = params->width0;
792 height = params->height0;
793 depth = texture->depth0;
794
795 if (params->force_level) {
796 base_level = params->force_level;
797 first_level = 0;
798 last_level = 0;
799 width = u_minify(width, params->force_level);
800 height = u_minify(height, params->force_level);
801 depth = u_minify(depth, params->force_level);
802 }
803
804 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(params->pipe_format);
805 non_disp_tiling = tmp->non_disp_tiling;
806
807 switch (surflevel[base_level].mode) {
808 default:
809 case RADEON_SURF_MODE_LINEAR_ALIGNED:
810 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
811 break;
812 case RADEON_SURF_MODE_2D:
813 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
814 break;
815 case RADEON_SURF_MODE_1D:
816 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
817 break;
818 }
819 macro_aspect = tmp->surface.u.legacy.mtilea;
820 bankw = tmp->surface.u.legacy.bankw;
821 bankh = tmp->surface.u.legacy.bankh;
822 tile_split = eg_tile_split(tile_split);
823 macro_aspect = eg_macro_tile_aspect(macro_aspect);
824 bankw = eg_bank_wh(bankw);
825 bankh = eg_bank_wh(bankh);
826 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
827
828 /* 128 bit formats require tile type = 1 */
829 if (rscreen->b.gfx_level == CAYMAN) {
830 if (util_format_get_blocksize(params->pipe_format) >= 16)
831 non_disp_tiling = 1;
832 }
833 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
834
835
836 va = tmp->resource.gpu_address;
837
838 /* array type views and views into array types need to use layer offset */
839 dim = r600_tex_dim(tmp, params->target, texture->nr_samples);
840
841 if (dim == V_030000_SQ_TEX_DIM_1D_ARRAY) {
842 height = 1;
843 depth = texture->array_size;
844 } else if (dim == V_030000_SQ_TEX_DIM_2D_ARRAY ||
845 dim == V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA) {
846 depth = texture->array_size;
847 } else if (dim == V_030000_SQ_TEX_DIM_CUBEMAP)
848 depth = texture->array_size / 6;
849
850 tex_resource_words[0] = (S_030000_DIM(dim) |
851 S_030000_PITCH((pitch / 8) - 1) |
852 S_030000_TEX_WIDTH(width - 1));
853 if (rscreen->b.gfx_level == CAYMAN)
854 tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
855 else
856 tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
857 tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
858 S_030004_TEX_DEPTH(depth - 1) |
859 S_030004_ARRAY_MODE(array_mode));
860 tex_resource_words[2] = ((uint64_t)surflevel[base_level].offset_256B * 256 + va) >> 8;
861
862 *skip_mip_address_reloc = false;
863 /* TEX_RESOURCE_WORD3.MIP_ADDRESS */
864 if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
865 if (tmp->is_depth) {
866 /* disable FMASK (0 = disabled) */
867 tex_resource_words[3] = 0;
868 *skip_mip_address_reloc = true;
869 } else {
870 /* FMASK should be in MIP_ADDRESS for multisample textures */
871 tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
872 }
873 } else if (last_level && texture->nr_samples <= 1) {
874 tex_resource_words[3] = ((uint64_t)surflevel[1].offset_256B * 256 + va) >> 8;
875 } else {
876 tex_resource_words[3] = ((uint64_t)surflevel[base_level].offset_256B * 256 + va) >> 8;
877 }
878
879 last_layer = params->last_layer;
880 if (params->target != texture->target && depth == 1) {
881 last_layer = params->first_layer;
882 }
883 tex_resource_words[4] = (word4 |
884 S_030010_ENDIAN_SWAP(endian));
885 tex_resource_words[5] = S_030014_BASE_ARRAY(params->first_layer) |
886 S_030014_LAST_ARRAY(last_layer);
887 tex_resource_words[6] = S_030018_TILE_SPLIT(tile_split);
888
889 if (texture->nr_samples > 1) {
890 unsigned log_samples = util_logbase2(texture->nr_samples);
891 if (rscreen->b.gfx_level == CAYMAN) {
892 tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
893 }
894 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
895 tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
896 tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
897 } else {
898 bool no_mip = first_level == last_level;
899
900 tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
901 tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
902 /* aniso max 16 samples */
903 tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4);
904 }
905
906 tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
907 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
908 S_03001C_BANK_WIDTH(bankw) |
909 S_03001C_BANK_HEIGHT(bankh) |
910 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
911 S_03001C_NUM_BANKS(nbanks) |
912 S_03001C_DEPTH_SAMPLE_ORDER(tmp->db_compatible);
913 return 0;
914 }
915
916 struct pipe_sampler_view *
evergreen_create_sampler_view_custom(struct pipe_context * ctx,struct pipe_resource * texture,const struct pipe_sampler_view * state,unsigned width0,unsigned height0,unsigned force_level)917 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
918 struct pipe_resource *texture,
919 const struct pipe_sampler_view *state,
920 unsigned width0, unsigned height0,
921 unsigned force_level)
922 {
923 struct r600_context *rctx = (struct r600_context*)ctx;
924 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
925 struct r600_texture *tmp = (struct r600_texture*)texture;
926 struct eg_tex_res_params params;
927 int ret;
928
929 if (!view)
930 return NULL;
931
932 /* initialize base object */
933 view->base = *state;
934 view->base.texture = NULL;
935 pipe_reference(NULL, &texture->reference);
936 view->base.texture = texture;
937 view->base.reference.count = 1;
938 view->base.context = ctx;
939
940 if (state->target == PIPE_BUFFER)
941 return texture_buffer_sampler_view(rctx, view, width0, height0);
942
943 memset(¶ms, 0, sizeof(params));
944 params.pipe_format = state->format;
945 params.force_level = force_level;
946 params.width0 = width0;
947 params.height0 = height0;
948 params.first_level = state->u.tex.first_level;
949 params.last_level = state->u.tex.last_level;
950 params.first_layer = state->u.tex.first_layer;
951 params.last_layer = state->u.tex.last_layer;
952 params.target = state->target;
953 params.swizzle[0] = state->swizzle_r;
954 params.swizzle[1] = state->swizzle_g;
955 params.swizzle[2] = state->swizzle_b;
956 params.swizzle[3] = state->swizzle_a;
957
958 ret = evergreen_fill_tex_resource_words(rctx, texture, ¶ms,
959 &view->skip_mip_address_reloc,
960 view->tex_resource_words);
961 if (ret != 0) {
962 FREE(view);
963 return NULL;
964 }
965
966 if (state->format == PIPE_FORMAT_X24S8_UINT ||
967 state->format == PIPE_FORMAT_S8X24_UINT ||
968 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
969 state->format == PIPE_FORMAT_S8_UINT)
970 view->is_stencil_sampler = true;
971
972 view->tex_resource = &tmp->resource;
973
974 return &view->base;
975 }
976
977 static struct pipe_sampler_view *
evergreen_create_sampler_view(struct pipe_context * ctx,struct pipe_resource * tex,const struct pipe_sampler_view * state)978 evergreen_create_sampler_view(struct pipe_context *ctx,
979 struct pipe_resource *tex,
980 const struct pipe_sampler_view *state)
981 {
982 return evergreen_create_sampler_view_custom(ctx, tex, state,
983 tex->width0, tex->height0, 0);
984 }
985
evergreen_emit_config_state(struct r600_context * rctx,struct r600_atom * atom)986 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
987 {
988 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
989 struct r600_config_state *a = (struct r600_config_state*)atom;
990
991 radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3);
992 if (a->dyn_gpr_enabled) {
993 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
994 radeon_emit(cs, 0);
995 radeon_emit(cs, 0);
996 } else {
997 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
998 radeon_emit(cs, a->sq_gpr_resource_mgmt_2);
999 radeon_emit(cs, a->sq_gpr_resource_mgmt_3);
1000 }
1001 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8));
1002 if (a->dyn_gpr_enabled) {
1003 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
1004 S_028838_PS_GPRS(0x1e) |
1005 S_028838_VS_GPRS(0x1e) |
1006 S_028838_GS_GPRS(0x1e) |
1007 S_028838_ES_GPRS(0x1e) |
1008 S_028838_HS_GPRS(0x1e) |
1009 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
1010 }
1011 }
1012
evergreen_emit_clip_state(struct r600_context * rctx,struct r600_atom * atom)1013 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1014 {
1015 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1016 struct pipe_clip_state *state = &rctx->clip_state.state;
1017
1018 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
1019 radeon_emit_array(cs, (unsigned*)state, 6*4);
1020 }
1021
evergreen_set_polygon_stipple(struct pipe_context * ctx,const struct pipe_poly_stipple * state)1022 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1023 const struct pipe_poly_stipple *state)
1024 {
1025 }
1026
evergreen_get_scissor_rect(struct r600_context * rctx,unsigned tl_x,unsigned tl_y,unsigned br_x,unsigned br_y,uint32_t * tl,uint32_t * br)1027 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1028 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1029 uint32_t *tl, uint32_t *br)
1030 {
1031 struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y};
1032
1033 evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor);
1034
1035 *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny);
1036 *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy);
1037 }
1038
1039 struct r600_tex_color_info {
1040 unsigned info;
1041 unsigned view;
1042 unsigned dim;
1043 unsigned pitch;
1044 unsigned slice;
1045 unsigned attrib;
1046 unsigned ntype;
1047 unsigned fmask;
1048 unsigned fmask_slice;
1049 uint64_t offset;
1050 bool export_16bpc;
1051 };
1052
evergreen_set_color_surface_buffer(struct r600_context * rctx,struct r600_resource * res,enum pipe_format pformat,unsigned first_element,unsigned last_element,struct r600_tex_color_info * color)1053 static void evergreen_set_color_surface_buffer(struct r600_context *rctx,
1054 struct r600_resource *res,
1055 enum pipe_format pformat,
1056 unsigned first_element,
1057 unsigned last_element,
1058 struct r600_tex_color_info *color)
1059 {
1060 unsigned format, swap, ntype, endian;
1061 const struct util_format_description *desc;
1062 unsigned block_size = util_format_get_blocksize(res->b.b.format);
1063 unsigned pitch_alignment =
1064 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
1065 unsigned pitch = align(res->b.b.width0, pitch_alignment);
1066 int i;
1067 unsigned width_elements;
1068
1069 width_elements = last_element - first_element + 1;
1070
1071 format = r600_translate_colorformat(rctx->b.gfx_level, pformat, false);
1072 swap = r600_translate_colorswap(pformat, false);
1073
1074 endian = r600_colorformat_endian_swap(format, false);
1075
1076 desc = util_format_description(pformat);
1077 i = util_format_get_first_non_void_channel(pformat);
1078 ntype = V_028C70_NUMBER_UNORM;
1079 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1080 ntype = V_028C70_NUMBER_SRGB;
1081 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1082 if (desc->channel[i].normalized)
1083 ntype = V_028C70_NUMBER_SNORM;
1084 else if (desc->channel[i].pure_integer)
1085 ntype = V_028C70_NUMBER_SINT;
1086 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1087 if (desc->channel[i].normalized)
1088 ntype = V_028C70_NUMBER_UNORM;
1089 else if (desc->channel[i].pure_integer)
1090 ntype = V_028C70_NUMBER_UINT;
1091 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1092 ntype = V_028C70_NUMBER_FLOAT;
1093 }
1094
1095 pitch = (pitch / 8) - 1;
1096 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1097
1098 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1099 color->info |= S_028C70_FORMAT(format) |
1100 S_028C70_COMP_SWAP(swap) |
1101 S_028C70_BLEND_CLAMP(0) |
1102 S_028C70_BLEND_BYPASS(1) |
1103 S_028C70_NUMBER_TYPE(ntype) |
1104 S_028C70_ENDIAN(endian);
1105 color->attrib = S_028C74_NON_DISP_TILING_ORDER(1);
1106 color->ntype = ntype;
1107 color->export_16bpc = false;
1108 color->dim = width_elements - 1;
1109 color->slice = 0; /* (width_elements / 64) - 1;*/
1110 color->view = 0;
1111 color->offset = (res->gpu_address + first_element) >> 8;
1112
1113 color->fmask = color->offset;
1114 color->fmask_slice = 0;
1115 }
1116
evergreen_set_color_surface_common(struct r600_context * rctx,struct r600_texture * rtex,unsigned level,unsigned first_layer,unsigned last_layer,enum pipe_format pformat,struct r600_tex_color_info * color)1117 static void evergreen_set_color_surface_common(struct r600_context *rctx,
1118 struct r600_texture *rtex,
1119 unsigned level,
1120 unsigned first_layer,
1121 unsigned last_layer,
1122 enum pipe_format pformat,
1123 struct r600_tex_color_info *color)
1124 {
1125 struct r600_screen *rscreen = rctx->screen;
1126 unsigned pitch, slice;
1127 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1128 unsigned format, swap, ntype, endian;
1129 const struct util_format_description *desc;
1130 bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = false;
1131 int i;
1132
1133 color->offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
1134 color->view = S_028C6C_SLICE_START(first_layer) |
1135 S_028C6C_SLICE_MAX(last_layer);
1136
1137 color->offset += rtex->resource.gpu_address;
1138 color->offset >>= 8;
1139
1140 color->dim = 0;
1141 pitch = (rtex->surface.u.legacy.level[level].nblk_x) / 8 - 1;
1142 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
1143 if (slice) {
1144 slice = slice - 1;
1145 }
1146
1147 color->info = 0;
1148 switch (rtex->surface.u.legacy.level[level].mode) {
1149 default:
1150 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1151 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1152 non_disp_tiling = 1;
1153 break;
1154 case RADEON_SURF_MODE_1D:
1155 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1156 non_disp_tiling = rtex->non_disp_tiling;
1157 break;
1158 case RADEON_SURF_MODE_2D:
1159 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1160 non_disp_tiling = rtex->non_disp_tiling;
1161 break;
1162 }
1163 tile_split = rtex->surface.u.legacy.tile_split;
1164 macro_aspect = rtex->surface.u.legacy.mtilea;
1165 bankw = rtex->surface.u.legacy.bankw;
1166 bankh = rtex->surface.u.legacy.bankh;
1167 if (rtex->fmask.size)
1168 fmask_bankh = rtex->fmask.bank_height;
1169 else
1170 fmask_bankh = rtex->surface.u.legacy.bankh;
1171 tile_split = eg_tile_split(tile_split);
1172 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1173 bankw = eg_bank_wh(bankw);
1174 bankh = eg_bank_wh(bankh);
1175 fmask_bankh = eg_bank_wh(fmask_bankh);
1176
1177 if (rscreen->b.gfx_level == CAYMAN) {
1178 if (util_format_get_blocksize(pformat) >= 16)
1179 non_disp_tiling = 1;
1180 }
1181 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1182 desc = util_format_description(pformat);
1183 i = util_format_get_first_non_void_channel(pformat);
1184 color->attrib = S_028C74_TILE_SPLIT(tile_split)|
1185 S_028C74_NUM_BANKS(nbanks) |
1186 S_028C74_BANK_WIDTH(bankw) |
1187 S_028C74_BANK_HEIGHT(bankh) |
1188 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1189 S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
1190 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1191
1192 if (rctx->b.gfx_level == CAYMAN) {
1193 color->attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
1194 PIPE_SWIZZLE_1);
1195
1196 if (rtex->resource.b.b.nr_samples > 1) {
1197 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1198 color->attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1199 S_028C74_NUM_FRAGMENTS(log_samples);
1200 }
1201 }
1202
1203 ntype = V_028C70_NUMBER_UNORM;
1204 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1205 ntype = V_028C70_NUMBER_SRGB;
1206 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1207 if (desc->channel[i].normalized)
1208 ntype = V_028C70_NUMBER_SNORM;
1209 else if (desc->channel[i].pure_integer)
1210 ntype = V_028C70_NUMBER_SINT;
1211 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1212 if (desc->channel[i].normalized)
1213 ntype = V_028C70_NUMBER_UNORM;
1214 else if (desc->channel[i].pure_integer)
1215 ntype = V_028C70_NUMBER_UINT;
1216 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1217 ntype = V_028C70_NUMBER_FLOAT;
1218 }
1219
1220 if (UTIL_ARCH_BIG_ENDIAN)
1221 do_endian_swap = !rtex->db_compatible;
1222
1223 format = r600_translate_colorformat(rctx->b.gfx_level, pformat, do_endian_swap);
1224 assert(format != ~0);
1225 swap = r600_translate_colorswap(pformat, do_endian_swap);
1226 assert(swap != ~0);
1227
1228 endian = r600_colorformat_endian_swap(format, do_endian_swap);
1229
1230 /* blend clamp should be set for all NORM/SRGB types */
1231 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1232 ntype == V_028C70_NUMBER_SRGB)
1233 blend_clamp = 1;
1234
1235 /* set blend bypass according to docs if SINT/UINT or
1236 8/24 COLOR variants */
1237 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1238 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1239 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1240 blend_clamp = 0;
1241 blend_bypass = 1;
1242 }
1243
1244 color->ntype = ntype;
1245 color->info |= S_028C70_FORMAT(format) |
1246 S_028C70_COMP_SWAP(swap) |
1247 S_028C70_BLEND_CLAMP(blend_clamp) |
1248 S_028C70_BLEND_BYPASS(blend_bypass) |
1249 S_028C70_SIMPLE_FLOAT(1) |
1250 S_028C70_NUMBER_TYPE(ntype) |
1251 S_028C70_ENDIAN(endian);
1252
1253 if (rtex->fmask.size) {
1254 color->info |= S_028C70_COMPRESSION(1);
1255 }
1256
1257 /* EXPORT_NORM is an optimization that can be enabled for better
1258 * performance in certain cases.
1259 * EXPORT_NORM can be enabled if:
1260 * - 11-bit or smaller UNORM/SNORM/SRGB
1261 * - 16-bit or smaller FLOAT
1262 */
1263 color->export_16bpc = false;
1264 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1265 ((desc->channel[i].size < 12 &&
1266 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1267 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1268 (desc->channel[i].size < 17 &&
1269 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1270 color->info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1271 color->export_16bpc = true;
1272 }
1273
1274 color->pitch = S_028C64_PITCH_TILE_MAX(pitch);
1275 color->slice = S_028C68_SLICE_TILE_MAX(slice);
1276
1277 if (rtex->fmask.size) {
1278 color->fmask = (rtex->resource.gpu_address + rtex->fmask.offset) >> 8;
1279 color->fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1280 } else {
1281 color->fmask = color->offset;
1282 color->fmask_slice = S_028C88_TILE_MAX(slice);
1283 }
1284 }
1285
1286 /**
1287 * This function initializes the CB* register values for RATs. It is meant
1288 * to be used for 1D aligned buffers that do not have an associated
1289 * radeon_surf.
1290 */
evergreen_init_color_surface_rat(struct r600_context * rctx,struct r600_surface * surf)1291 void evergreen_init_color_surface_rat(struct r600_context *rctx,
1292 struct r600_surface *surf)
1293 {
1294 struct pipe_resource *pipe_buffer = surf->base.texture;
1295 struct r600_tex_color_info color;
1296
1297 evergreen_set_color_surface_buffer(rctx, (struct r600_resource *)surf->base.texture,
1298 surf->base.format, 0, pipe_buffer->width0,
1299 &color);
1300
1301 surf->cb_color_base = color.offset;
1302 surf->cb_color_dim = color.dim;
1303 surf->cb_color_info = color.info | S_028C70_RAT(1);
1304 surf->cb_color_pitch = color.pitch;
1305 surf->cb_color_slice = color.slice;
1306 surf->cb_color_view = color.view;
1307 surf->cb_color_attrib = color.attrib;
1308 surf->cb_color_fmask = color.fmask;
1309 surf->cb_color_fmask_slice = color.fmask_slice;
1310
1311 surf->cb_color_view = 0;
1312
1313 /* Set the buffer range the GPU will have access to: */
1314 util_range_add(pipe_buffer, &r600_resource(pipe_buffer)->valid_buffer_range,
1315 0, pipe_buffer->width0);
1316 }
1317
1318
evergreen_init_color_surface(struct r600_context * rctx,struct r600_surface * surf)1319 void evergreen_init_color_surface(struct r600_context *rctx,
1320 struct r600_surface *surf)
1321 {
1322 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1323 unsigned level = surf->base.u.tex.level;
1324 struct r600_tex_color_info color;
1325
1326 evergreen_set_color_surface_common(rctx, rtex, level,
1327 surf->base.u.tex.first_layer,
1328 surf->base.u.tex.last_layer,
1329 surf->base.format,
1330 &color);
1331
1332 surf->alphatest_bypass = color.ntype == V_028C70_NUMBER_UINT ||
1333 color.ntype == V_028C70_NUMBER_SINT;
1334 surf->export_16bpc = color.export_16bpc;
1335
1336 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1337 surf->cb_color_base = color.offset;
1338 surf->cb_color_dim = color.dim;
1339 surf->cb_color_info = color.info;
1340 surf->cb_color_pitch = color.pitch;
1341 surf->cb_color_slice = color.slice;
1342 surf->cb_color_view = color.view;
1343 surf->cb_color_attrib = color.attrib;
1344 surf->cb_color_fmask = color.fmask;
1345 surf->cb_color_fmask_slice = color.fmask_slice;
1346
1347 surf->color_initialized = true;
1348 }
1349
evergreen_init_depth_surface(struct r600_context * rctx,struct r600_surface * surf)1350 static void evergreen_init_depth_surface(struct r600_context *rctx,
1351 struct r600_surface *surf)
1352 {
1353 struct r600_screen *rscreen = rctx->screen;
1354 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1355 unsigned level = surf->base.u.tex.level;
1356 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
1357 uint64_t offset;
1358 unsigned format, array_mode;
1359 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1360
1361
1362 format = r600_translate_dbformat(surf->base.format);
1363 assert(format != ~0);
1364
1365 offset = rtex->resource.gpu_address;
1366 offset += (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
1367
1368 switch (rtex->surface.u.legacy.level[level].mode) {
1369 case RADEON_SURF_MODE_2D:
1370 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1371 break;
1372 case RADEON_SURF_MODE_1D:
1373 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1374 default:
1375 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1376 break;
1377 }
1378 tile_split = rtex->surface.u.legacy.tile_split;
1379 macro_aspect = rtex->surface.u.legacy.mtilea;
1380 bankw = rtex->surface.u.legacy.bankw;
1381 bankh = rtex->surface.u.legacy.bankh;
1382 tile_split = eg_tile_split(tile_split);
1383 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1384 bankw = eg_bank_wh(bankw);
1385 bankh = eg_bank_wh(bankh);
1386 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1387 offset >>= 8;
1388
1389 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
1390 S_028040_FORMAT(format) |
1391 S_028040_TILE_SPLIT(tile_split)|
1392 S_028040_NUM_BANKS(nbanks) |
1393 S_028040_BANK_WIDTH(bankw) |
1394 S_028040_BANK_HEIGHT(bankh) |
1395 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1396 if (rscreen->b.gfx_level == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1397 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1398 }
1399
1400 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1401
1402 surf->db_depth_base = offset;
1403 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1404 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1405 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) |
1406 S_028058_HEIGHT_TILE_MAX(levelinfo->nblk_y / 8 - 1);
1407 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
1408 levelinfo->nblk_y / 64 - 1);
1409
1410 if (rtex->surface.has_stencil) {
1411 uint64_t stencil_offset;
1412 unsigned stile_split = rtex->surface.u.legacy.stencil_tile_split;
1413
1414 stile_split = eg_tile_split(stile_split);
1415
1416 stencil_offset = (uint64_t)rtex->surface.u.legacy.zs.stencil_level[level].offset_256B * 256;
1417 stencil_offset += rtex->resource.gpu_address;
1418
1419 surf->db_stencil_base = stencil_offset >> 8;
1420 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8) |
1421 S_028044_TILE_SPLIT(stile_split);
1422 } else {
1423 surf->db_stencil_base = offset;
1424 surf->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1425 }
1426
1427 if (r600_htile_enabled(rtex, level)) {
1428 uint64_t va = rtex->resource.gpu_address + rtex->htile_offset;
1429 surf->db_htile_data_base = va >> 8;
1430 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
1431 S_028ABC_HTILE_HEIGHT(1) |
1432 S_028ABC_FULL_CACHE(1);
1433 surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1434 surf->db_preload_control = 0;
1435 }
1436
1437 surf->depth_initialized = true;
1438 }
1439
evergreen_set_framebuffer_state(struct pipe_context * ctx,const struct pipe_framebuffer_state * state)1440 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1441 const struct pipe_framebuffer_state *state)
1442 {
1443 struct r600_context *rctx = (struct r600_context *)ctx;
1444 struct r600_surface *surf;
1445 struct r600_texture *rtex;
1446 uint32_t i, log_samples;
1447 uint32_t target_mask = 0;
1448 /* Flush TC when changing the framebuffer state, because the only
1449 * client not using TC that can change textures is the framebuffer.
1450 * Other places don't typically have to flush TC.
1451 */
1452 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1453 R600_CONTEXT_FLUSH_AND_INV |
1454 R600_CONTEXT_FLUSH_AND_INV_CB |
1455 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1456 R600_CONTEXT_FLUSH_AND_INV_DB |
1457 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1458 R600_CONTEXT_INV_TEX_CACHE;
1459
1460 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1461
1462 /* Colorbuffers. */
1463 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1464 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1465 util_format_is_pure_integer(state->cbufs[0]->format);
1466 rctx->framebuffer.compressed_cb_mask = 0;
1467 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1468
1469 for (i = 0; i < state->nr_cbufs; i++) {
1470 surf = (struct r600_surface*)state->cbufs[i];
1471 if (!surf)
1472 continue;
1473
1474 target_mask |= (0xf << (i * 4));
1475
1476 rtex = (struct r600_texture*)surf->base.texture;
1477
1478 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1479
1480 if (!surf->color_initialized) {
1481 evergreen_init_color_surface(rctx, surf);
1482 }
1483
1484 if (!surf->export_16bpc) {
1485 rctx->framebuffer.export_16bpc = false;
1486 }
1487
1488 if (rtex->fmask.size) {
1489 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1490 }
1491 }
1492
1493 /* Update alpha-test state dependencies.
1494 * Alpha-test is done on the first colorbuffer only. */
1495 if (state->nr_cbufs) {
1496 bool alphatest_bypass = false;
1497 bool export_16bpc = true;
1498
1499 surf = (struct r600_surface*)state->cbufs[0];
1500 if (surf) {
1501 alphatest_bypass = surf->alphatest_bypass;
1502 export_16bpc = surf->export_16bpc;
1503 }
1504
1505 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1506 rctx->alphatest_state.bypass = alphatest_bypass;
1507 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1508 }
1509 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1510 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1511 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1512 }
1513 }
1514
1515 /* ZS buffer. */
1516 if (state->zsbuf) {
1517 surf = (struct r600_surface*)state->zsbuf;
1518
1519 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1520
1521 if (!surf->depth_initialized) {
1522 evergreen_init_depth_surface(rctx, surf);
1523 }
1524
1525 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1526 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1527 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1528 }
1529
1530 if (rctx->db_state.rsurf != surf) {
1531 rctx->db_state.rsurf = surf;
1532 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1533 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1534 }
1535 } else if (rctx->db_state.rsurf) {
1536 rctx->db_state.rsurf = NULL;
1537 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1538 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1539 }
1540
1541 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs ||
1542 rctx->cb_misc_state.bound_cbufs_target_mask != target_mask) {
1543 rctx->cb_misc_state.bound_cbufs_target_mask = target_mask;
1544 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1545 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1546 }
1547
1548 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1549 rctx->alphatest_state.bypass = false;
1550 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1551 }
1552
1553 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1554 /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
1555 if ((rctx->b.gfx_level == CAYMAN ||
1556 rctx->b.family == CHIP_RV770) &&
1557 rctx->db_misc_state.log_samples != log_samples) {
1558 rctx->db_misc_state.log_samples = log_samples;
1559 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1560 }
1561
1562
1563 /* Calculate the CS size. */
1564 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1565
1566 /* MSAA. */
1567 if (rctx->b.gfx_level == EVERGREEN)
1568 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1569 else
1570 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1571
1572 /* Colorbuffers. */
1573 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1574 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1575 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1576
1577 /* ZS buffer. */
1578 if (state->zsbuf) {
1579 rctx->framebuffer.atom.num_dw += 24;
1580 rctx->framebuffer.atom.num_dw += 2;
1581 } else {
1582 rctx->framebuffer.atom.num_dw += 4;
1583 }
1584
1585 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1586
1587 r600_set_sample_locations_constant_buffer(rctx);
1588 rctx->framebuffer.do_update_surf_dirtiness = true;
1589 }
1590
evergreen_set_min_samples(struct pipe_context * ctx,unsigned min_samples)1591 static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1592 {
1593 struct r600_context *rctx = (struct r600_context *)ctx;
1594
1595 if (rctx->ps_iter_samples == min_samples)
1596 return;
1597
1598 rctx->ps_iter_samples = min_samples;
1599 if (rctx->framebuffer.nr_samples > 1) {
1600 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1601 }
1602 }
1603
1604 /* 8xMSAA */
1605 static const uint32_t sample_locs_8x[] = {
1606 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1607 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1608 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1609 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1610 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1611 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1612 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1613 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1614 };
1615 static unsigned max_dist_8x = 7;
1616
evergreen_get_sample_position(struct pipe_context * ctx,unsigned sample_count,unsigned sample_index,float * out_value)1617 static void evergreen_get_sample_position(struct pipe_context *ctx,
1618 unsigned sample_count,
1619 unsigned sample_index,
1620 float *out_value)
1621 {
1622 int offset, index;
1623 struct {
1624 int idx:4;
1625 } val;
1626 switch (sample_count) {
1627 case 1:
1628 default:
1629 out_value[0] = out_value[1] = 0.5;
1630 break;
1631 case 2:
1632 offset = 4 * (sample_index * 2);
1633 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1634 out_value[0] = (float)(val.idx + 8) / 16.0f;
1635 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1636 out_value[1] = (float)(val.idx + 8) / 16.0f;
1637 break;
1638 case 4:
1639 offset = 4 * (sample_index * 2);
1640 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1641 out_value[0] = (float)(val.idx + 8) / 16.0f;
1642 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1643 out_value[1] = (float)(val.idx + 8) / 16.0f;
1644 break;
1645 case 8:
1646 offset = 4 * (sample_index % 4 * 2);
1647 index = (sample_index / 4);
1648 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1649 out_value[0] = (float)(val.idx + 8) / 16.0f;
1650 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1651 out_value[1] = (float)(val.idx + 8) / 16.0f;
1652 break;
1653 }
1654 }
1655
evergreen_emit_msaa_state(struct r600_context * rctx,int nr_samples,int ps_iter_samples)1656 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1657 {
1658
1659 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1660 unsigned max_dist = 0;
1661
1662 switch (nr_samples) {
1663 default:
1664 nr_samples = 0;
1665 break;
1666 case 2:
1667 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_2x));
1668 radeon_emit_array(cs, eg_sample_locs_2x, ARRAY_SIZE(eg_sample_locs_2x));
1669 max_dist = eg_max_dist_2x;
1670 break;
1671 case 4:
1672 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_4x));
1673 radeon_emit_array(cs, eg_sample_locs_4x, ARRAY_SIZE(eg_sample_locs_4x));
1674 max_dist = eg_max_dist_4x;
1675 break;
1676 case 8:
1677 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(sample_locs_8x));
1678 radeon_emit_array(cs, sample_locs_8x, ARRAY_SIZE(sample_locs_8x));
1679 max_dist = max_dist_8x;
1680 break;
1681 }
1682
1683 if (nr_samples > 1) {
1684 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1685 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1686 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1687 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1688 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1689 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1690 EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
1691 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1692 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1693 } else {
1694 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1695 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1696 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1697 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
1698 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1699 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
1700 }
1701 }
1702
evergreen_emit_image_state(struct r600_context * rctx,struct r600_atom * atom,int immed_id_base,int res_id_base,int offset,uint32_t pkt_flags)1703 static void evergreen_emit_image_state(struct r600_context *rctx, struct r600_atom *atom,
1704 int immed_id_base, int res_id_base, int offset, uint32_t pkt_flags)
1705 {
1706 struct r600_image_state *state = (struct r600_image_state *)atom;
1707 struct pipe_framebuffer_state *fb_state = &rctx->framebuffer.state;
1708 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1709 struct r600_texture *rtex;
1710 struct r600_resource *resource;
1711 int i;
1712
1713 for (i = 0; i < R600_MAX_IMAGES; i++) {
1714 struct r600_image_view *image = &state->views[i];
1715 unsigned reloc, immed_reloc;
1716 int idx = i + offset;
1717
1718 if (!pkt_flags)
1719 idx += fb_state->nr_cbufs + (rctx->dual_src_blend ? 1 : 0);
1720 if (!image->base.resource)
1721 continue;
1722
1723 resource = (struct r600_resource *)image->base.resource;
1724 if (resource->b.b.target != PIPE_BUFFER)
1725 rtex = (struct r600_texture *)image->base.resource;
1726 else
1727 rtex = NULL;
1728
1729 reloc = radeon_add_to_buffer_list(&rctx->b,
1730 &rctx->b.gfx,
1731 resource,
1732 RADEON_USAGE_READWRITE |
1733 RADEON_PRIO_SHADER_RW_BUFFER);
1734
1735 immed_reloc = radeon_add_to_buffer_list(&rctx->b,
1736 &rctx->b.gfx,
1737 resource->immed_buffer,
1738 RADEON_USAGE_READWRITE |
1739 RADEON_PRIO_SHADER_RW_BUFFER);
1740
1741 if (pkt_flags)
1742 radeon_compute_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + idx * 0x3C, 13);
1743 else
1744 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + idx * 0x3C, 13);
1745
1746 radeon_emit(cs, image->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1747 radeon_emit(cs, image->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1748 radeon_emit(cs, image->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1749 radeon_emit(cs, image->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1750 radeon_emit(cs, image->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1751 radeon_emit(cs, image->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1752 radeon_emit(cs, image->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1753 radeon_emit(cs, rtex ? rtex->cmask.base_address_reg : image->cb_color_base); /* R_028C7C_CB_COLOR0_CMASK */
1754 radeon_emit(cs, rtex ? rtex->cmask.slice_tile_max : 0); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1755 radeon_emit(cs, image->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1756 radeon_emit(cs, image->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1757 radeon_emit(cs, rtex ? rtex->color_clear_value[0] : 0); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1758 radeon_emit(cs, rtex ? rtex->color_clear_value[1] : 0); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1759
1760 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1761 radeon_emit(cs, reloc);
1762
1763 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1764 radeon_emit(cs, reloc);
1765
1766 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1767 radeon_emit(cs, reloc);
1768
1769 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1770 radeon_emit(cs, reloc);
1771
1772 if (pkt_flags)
1773 radeon_compute_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8);
1774 else
1775 radeon_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8);
1776
1777 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /**/
1778 radeon_emit(cs, immed_reloc);
1779
1780 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1781 radeon_emit(cs, (immed_id_base + i + offset) * 8);
1782 radeon_emit_array(cs, image->immed_resource_words, 8);
1783
1784 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1785 radeon_emit(cs, immed_reloc);
1786
1787 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1788 radeon_emit(cs, (res_id_base + i + offset) * 8);
1789 radeon_emit_array(cs, image->resource_words, 8);
1790
1791 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1792 radeon_emit(cs, reloc);
1793
1794 if (!image->skip_mip_address_reloc) {
1795 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1796 radeon_emit(cs, reloc);
1797 }
1798 }
1799 }
1800
evergreen_emit_fragment_image_state(struct r600_context * rctx,struct r600_atom * atom)1801 static void evergreen_emit_fragment_image_state(struct r600_context *rctx, struct r600_atom *atom)
1802 {
1803 evergreen_emit_image_state(rctx, atom,
1804 R600_IMAGE_IMMED_RESOURCE_OFFSET,
1805 R600_IMAGE_REAL_RESOURCE_OFFSET, 0, 0);
1806 }
1807
evergreen_emit_compute_image_state(struct r600_context * rctx,struct r600_atom * atom)1808 static void evergreen_emit_compute_image_state(struct r600_context *rctx, struct r600_atom *atom)
1809 {
1810 evergreen_emit_image_state(rctx, atom,
1811 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_IMMED_RESOURCE_OFFSET,
1812 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_REAL_RESOURCE_OFFSET,
1813 0, RADEON_CP_PACKET3_COMPUTE_MODE);
1814 }
1815
evergreen_emit_fragment_buffer_state(struct r600_context * rctx,struct r600_atom * atom)1816 static void evergreen_emit_fragment_buffer_state(struct r600_context *rctx, struct r600_atom *atom)
1817 {
1818 int offset = util_bitcount(rctx->fragment_images.enabled_mask);
1819 evergreen_emit_image_state(rctx, atom,
1820 R600_IMAGE_IMMED_RESOURCE_OFFSET,
1821 R600_IMAGE_REAL_RESOURCE_OFFSET, offset, 0);
1822 }
1823
evergreen_emit_compute_buffer_state(struct r600_context * rctx,struct r600_atom * atom)1824 static void evergreen_emit_compute_buffer_state(struct r600_context *rctx, struct r600_atom *atom)
1825 {
1826 int offset = util_bitcount(rctx->compute_images.enabled_mask);
1827 evergreen_emit_image_state(rctx, atom,
1828 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_IMMED_RESOURCE_OFFSET,
1829 EG_FETCH_CONSTANTS_OFFSET_CS + R600_IMAGE_REAL_RESOURCE_OFFSET,
1830 offset, RADEON_CP_PACKET3_COMPUTE_MODE);
1831 }
1832
evergreen_emit_framebuffer_state(struct r600_context * rctx,struct r600_atom * atom)1833 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1834 {
1835 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1836 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1837 unsigned nr_cbufs = state->nr_cbufs;
1838 unsigned i, tl, br;
1839 struct r600_texture *tex = NULL;
1840 struct r600_surface *cb = NULL;
1841
1842 /* XXX support more colorbuffers once we need them */
1843 assert(nr_cbufs <= 8);
1844 if (nr_cbufs > 8)
1845 nr_cbufs = 8;
1846
1847 /* Colorbuffers. */
1848 for (i = 0; i < nr_cbufs; i++) {
1849 unsigned reloc, cmask_reloc;
1850
1851 cb = (struct r600_surface*)state->cbufs[i];
1852 if (!cb) {
1853 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1854 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1855 continue;
1856 }
1857
1858 tex = (struct r600_texture *)cb->base.texture;
1859 reloc = radeon_add_to_buffer_list(&rctx->b,
1860 &rctx->b.gfx,
1861 (struct r600_resource*)cb->base.texture,
1862 RADEON_USAGE_READWRITE |
1863 (tex->resource.b.b.nr_samples > 1 ?
1864 RADEON_PRIO_COLOR_BUFFER_MSAA :
1865 RADEON_PRIO_COLOR_BUFFER));
1866
1867 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
1868 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1869 tex->cmask_buffer, RADEON_USAGE_READWRITE | RADEON_PRIO_SEPARATE_META);
1870 } else {
1871 cmask_reloc = reloc;
1872 }
1873
1874 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
1875 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
1876 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
1877 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
1878 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
1879 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
1880 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
1881 radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
1882 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
1883 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1884 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
1885 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
1886 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1887 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
1888
1889 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
1890 radeon_emit(cs, reloc);
1891
1892 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
1893 radeon_emit(cs, reloc);
1894
1895 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
1896 radeon_emit(cs, cmask_reloc);
1897
1898 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
1899 radeon_emit(cs, reloc);
1900 }
1901 /* set CB_COLOR1_INFO for possible dual-src blending */
1902 if (rctx->framebuffer.dual_src_blend && i == 1 && state->cbufs[0]) {
1903 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1904 cb->cb_color_info | tex->cb_color_info);
1905 i++;
1906 }
1907 i += util_bitcount(rctx->fragment_images.enabled_mask);
1908 i += util_bitcount(rctx->fragment_buffers.enabled_mask);
1909 for (; i < 8 ; i++)
1910 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1911 for (; i < 12; i++)
1912 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0);
1913
1914 /* ZS buffer. */
1915 if (state->zsbuf) {
1916 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1917 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1918 &rctx->b.gfx,
1919 (struct r600_resource*)state->zsbuf->texture,
1920 RADEON_USAGE_READWRITE |
1921 (zb->base.texture->nr_samples > 1 ?
1922 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1923 RADEON_PRIO_DEPTH_BUFFER));
1924
1925 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
1926
1927 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
1928 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
1929 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1930 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
1931 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
1932 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
1933 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1934 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1935 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1936
1937 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
1938 radeon_emit(cs, reloc);
1939
1940 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
1941 radeon_emit(cs, reloc);
1942
1943 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
1944 radeon_emit(cs, reloc);
1945
1946 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
1947 radeon_emit(cs, reloc);
1948 } else {
1949 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
1950 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
1951 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
1952 }
1953
1954 /* Framebuffer dimensions. */
1955 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1956
1957 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1958 radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1959 radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1960
1961 if (rctx->b.gfx_level == EVERGREEN) {
1962 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1963 } else {
1964 cayman_emit_msaa_state(cs, rctx->framebuffer.nr_samples,
1965 rctx->ps_iter_samples, 0);
1966 }
1967 }
1968
evergreen_emit_polygon_offset(struct r600_context * rctx,struct r600_atom * a)1969 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1970 {
1971 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1972 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1973 float offset_units = state->offset_units;
1974 float offset_scale = state->offset_scale;
1975 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
1976
1977 if (!state->offset_units_unscaled) {
1978 switch (state->zs_format) {
1979 case PIPE_FORMAT_Z24X8_UNORM:
1980 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1981 case PIPE_FORMAT_X8Z24_UNORM:
1982 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1983 offset_units *= 2.0f;
1984 pa_su_poly_offset_db_fmt_cntl =
1985 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
1986 break;
1987 case PIPE_FORMAT_Z16_UNORM:
1988 offset_units *= 4.0f;
1989 pa_su_poly_offset_db_fmt_cntl =
1990 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
1991 break;
1992 default:
1993 pa_su_poly_offset_db_fmt_cntl =
1994 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
1995 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1996 }
1997 }
1998
1999 radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
2000 radeon_emit(cs, fui(offset_scale));
2001 radeon_emit(cs, fui(offset_units));
2002 radeon_emit(cs, fui(offset_scale));
2003 radeon_emit(cs, fui(offset_units));
2004
2005 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2006 pa_su_poly_offset_db_fmt_cntl);
2007 }
2008
evergreen_construct_rat_mask(struct r600_context * rctx,struct r600_cb_misc_state * a,unsigned nr_cbufs)2009 uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_misc_state *a,
2010 unsigned nr_cbufs)
2011 {
2012 unsigned base_mask = 0;
2013 unsigned dirty_mask = a->image_rat_enabled_mask;
2014 while (dirty_mask) {
2015 unsigned idx = u_bit_scan(&dirty_mask);
2016 base_mask |= (0xf << (idx * 4));
2017 }
2018 unsigned offset = util_last_bit(a->image_rat_enabled_mask);
2019 dirty_mask = a->buffer_rat_enabled_mask;
2020 while (dirty_mask) {
2021 unsigned idx = u_bit_scan(&dirty_mask);
2022 base_mask |= (0xf << (idx + offset) * 4);
2023 }
2024 return base_mask << (nr_cbufs * 4);
2025 }
2026
evergreen_emit_cb_misc_state(struct r600_context * rctx,struct r600_atom * atom)2027 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2028 {
2029 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2030 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
2031 unsigned fb_colormask = a->bound_cbufs_target_mask;
2032 unsigned ps_colormask = a->ps_color_export_mask;
2033 unsigned rat_colormask = evergreen_construct_rat_mask(rctx, a, a->nr_cbufs);
2034 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
2035 radeon_emit(cs, (a->blend_colormask & fb_colormask) | rat_colormask); /* R_028238_CB_TARGET_MASK */
2036 /* This must match the used export instructions exactly.
2037 * Other values may lead to undefined behavior and hangs.
2038 */
2039 radeon_emit(cs, ps_colormask); /* R_02823C_CB_SHADER_MASK */
2040 }
2041
evergreen_emit_db_state(struct r600_context * rctx,struct r600_atom * atom)2042 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
2043 {
2044 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2045 struct r600_db_state *a = (struct r600_db_state*)atom;
2046
2047 if (a->rsurf && a->rsurf->db_htile_surface) {
2048 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
2049 unsigned reloc_idx;
2050
2051 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2052 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
2053 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
2054 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
2055 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
2056 RADEON_USAGE_READWRITE | RADEON_PRIO_SEPARATE_META);
2057 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2058 radeon_emit(cs, reloc_idx);
2059 } else {
2060 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0);
2061 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0);
2062 }
2063 }
2064
evergreen_emit_db_misc_state(struct r600_context * rctx,struct r600_atom * atom)2065 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2066 {
2067 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2068 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
2069 unsigned db_render_control = 0;
2070 unsigned db_count_control = 0;
2071 unsigned db_render_override =
2072 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2073 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2074
2075 if (rctx->b.num_occlusion_queries > 0 &&
2076 !a->occlusion_queries_disabled) {
2077 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
2078 if (rctx->b.gfx_level == CAYMAN) {
2079 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
2080 }
2081 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
2082 } else {
2083 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
2084 }
2085
2086 /* This is to fix a lockup when hyperz and alpha test are enabled at
2087 * the same time somehow GPU get confuse on which order to pick for
2088 * z test
2089 */
2090 if (rctx->alphatest_state.sx_alpha_test_control)
2091 db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
2092
2093 if (a->flush_depthstencil_through_cb) {
2094 assert(a->copy_depth || a->copy_stencil);
2095
2096 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
2097 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
2098 S_028000_COPY_CENTROID(1) |
2099 S_028000_COPY_SAMPLE(a->copy_sample);
2100 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
2101 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
2102 S_028000_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
2103 db_render_override |= S_02800C_DISABLE_PIXEL_RATE_TILES(1);
2104 }
2105 if (a->htile_clear) {
2106 /* FIXME we might want to disable cliprect here */
2107 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(1);
2108 }
2109
2110 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
2111 radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
2112 radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
2113 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2114 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
2115 }
2116
evergreen_emit_vertex_buffers(struct r600_context * rctx,struct r600_vertexbuf_state * state,unsigned resource_offset,unsigned pkt_flags)2117 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
2118 struct r600_vertexbuf_state *state,
2119 unsigned resource_offset,
2120 unsigned pkt_flags)
2121 {
2122 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2123 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)rctx->vertex_fetch_shader.cso;
2124 uint32_t buffer_mask = shader ? shader->buffer_mask : ~0;
2125 uint32_t dirty_mask = state->dirty_mask & buffer_mask;
2126
2127 while (dirty_mask) {
2128 struct pipe_vertex_buffer *vb;
2129 struct r600_resource *rbuffer;
2130 uint64_t va;
2131 unsigned buffer_index = u_bit_scan(&dirty_mask);
2132 unsigned stride = pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE ?
2133 1 : shader->strides[buffer_index];
2134
2135 vb = &state->vb[buffer_index];
2136 rbuffer = (struct r600_resource*)vb->buffer.resource;
2137 assert(rbuffer);
2138
2139 va = rbuffer->gpu_address + vb->buffer_offset;
2140
2141 /* fetch resources start at index 992 */
2142 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2143 radeon_emit(cs, (resource_offset + buffer_index) * 8);
2144 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2145 radeon_emit(cs, rbuffer->b.b.width0 - vb->buffer_offset - 1 + shader->width_correction[buffer_index]); /* RESOURCEi_WORD1 */
2146 radeon_emit(cs, /* RESOURCEi_WORD2 */
2147 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2148 S_030008_STRIDE(stride) |
2149 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2150 radeon_emit(cs, /* RESOURCEi_WORD3 */
2151 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2152 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2153 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2154 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2155 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2156 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2157 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2158 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2159
2160 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2161 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2162 RADEON_USAGE_READ | RADEON_PRIO_VERTEX_BUFFER));
2163 }
2164 state->dirty_mask &= ~buffer_mask;
2165 }
2166
evergreen_fs_emit_vertex_buffers(struct r600_context * rctx,struct r600_atom * atom)2167 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2168 {
2169 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
2170 }
2171
evergreen_cs_emit_vertex_buffers(struct r600_context * rctx,struct r600_atom * atom)2172 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2173 {
2174 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
2175 RADEON_CP_PACKET3_COMPUTE_MODE);
2176 }
2177
evergreen_emit_constant_buffers(struct r600_context * rctx,struct r600_constbuf_state * state,unsigned buffer_id_base,unsigned reg_alu_constbuf_size,unsigned reg_alu_const_cache,unsigned pkt_flags)2178 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
2179 struct r600_constbuf_state *state,
2180 unsigned buffer_id_base,
2181 unsigned reg_alu_constbuf_size,
2182 unsigned reg_alu_const_cache,
2183 unsigned pkt_flags)
2184 {
2185 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2186 uint32_t dirty_mask = state->dirty_mask;
2187
2188 while (dirty_mask) {
2189 struct pipe_constant_buffer *cb;
2190 struct r600_resource *rbuffer;
2191 uint64_t va;
2192 unsigned buffer_index = ffs(dirty_mask) - 1;
2193 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
2194
2195 cb = &state->cb[buffer_index];
2196 rbuffer = (struct r600_resource*)cb->buffer;
2197 assert(rbuffer);
2198
2199 va = rbuffer->gpu_address + cb->buffer_offset;
2200
2201 if (buffer_index < R600_MAX_ALU_CONST_BUFFERS) {
2202 radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
2203 DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags);
2204 radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
2205 pkt_flags);
2206 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2207 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2208 RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER));
2209 }
2210
2211 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2212 radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
2213 radeon_emit(cs, va); /* RESOURCEi_WORD0 */
2214 radeon_emit(cs, cb->buffer_size -1); /* RESOURCEi_WORD1 */
2215 radeon_emit(cs, /* RESOURCEi_WORD2 */
2216 S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
2217 S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
2218 S_030008_BASE_ADDRESS_HI(va >> 32UL) |
2219 S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
2220 radeon_emit(cs, /* RESOURCEi_WORD3 */
2221 S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
2222 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2223 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2224 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2225 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2226 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
2227 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
2228 radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
2229 radeon_emit(cs, /* RESOURCEi_WORD7 */
2230 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
2231
2232 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2233 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2234 RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER));
2235
2236 dirty_mask &= ~(1 << buffer_index);
2237 }
2238 state->dirty_mask = 0;
2239 }
2240
2241 /* VS constants can be in VS/ES (same space) or LS if tess is enabled */
evergreen_emit_vs_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)2242 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2243 {
2244 if (rctx->vs_shader->current->shader.vs_as_ls) {
2245 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2246 EG_FETCH_CONSTANTS_OFFSET_LS,
2247 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2248 R_028F40_ALU_CONST_CACHE_LS_0,
2249 0 /* PKT3 flags */);
2250 } else {
2251 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2252 EG_FETCH_CONSTANTS_OFFSET_VS,
2253 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2254 R_028980_ALU_CONST_CACHE_VS_0,
2255 0 /* PKT3 flags */);
2256 }
2257 }
2258
evergreen_emit_gs_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)2259 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2260 {
2261 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
2262 EG_FETCH_CONSTANTS_OFFSET_GS,
2263 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
2264 R_0289C0_ALU_CONST_CACHE_GS_0,
2265 0 /* PKT3 flags */);
2266 }
2267
evergreen_emit_ps_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)2268 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2269 {
2270 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
2271 EG_FETCH_CONSTANTS_OFFSET_PS,
2272 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2273 R_028940_ALU_CONST_CACHE_PS_0,
2274 0 /* PKT3 flags */);
2275 }
2276
evergreen_emit_cs_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)2277 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2278 {
2279 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
2280 EG_FETCH_CONSTANTS_OFFSET_CS,
2281 R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
2282 R_028F40_ALU_CONST_CACHE_LS_0,
2283 RADEON_CP_PACKET3_COMPUTE_MODE);
2284 }
2285
2286 /* tes constants can be emitted to VS or ES - which are common */
evergreen_emit_tes_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)2287 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2288 {
2289 if (!rctx->tes_shader)
2290 return;
2291 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
2292 EG_FETCH_CONSTANTS_OFFSET_VS,
2293 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2294 R_028980_ALU_CONST_CACHE_VS_0,
2295 0);
2296 }
2297
evergreen_emit_tcs_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)2298 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2299 {
2300 if (!rctx->tes_shader)
2301 return;
2302 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
2303 EG_FETCH_CONSTANTS_OFFSET_HS,
2304 R_028F80_ALU_CONST_BUFFER_SIZE_HS_0,
2305 R_028F00_ALU_CONST_CACHE_HS_0,
2306 0);
2307 }
2308
evergreen_setup_scratch_buffers(struct r600_context * rctx)2309 void evergreen_setup_scratch_buffers(struct r600_context *rctx) {
2310 static const struct {
2311 unsigned ring_base;
2312 unsigned item_size;
2313 unsigned ring_size;
2314 } regs[EG_NUM_HW_STAGES] = {
2315 [R600_HW_STAGE_PS] = { R_008C68_SQ_PSTMP_RING_BASE, R_028914_SQ_PSTMP_RING_ITEMSIZE, R_008C6C_SQ_PSTMP_RING_SIZE },
2316 [R600_HW_STAGE_VS] = { R_008C60_SQ_VSTMP_RING_BASE, R_028910_SQ_VSTMP_RING_ITEMSIZE, R_008C64_SQ_VSTMP_RING_SIZE },
2317 [R600_HW_STAGE_GS] = { R_008C58_SQ_GSTMP_RING_BASE, R_02890C_SQ_GSTMP_RING_ITEMSIZE, R_008C5C_SQ_GSTMP_RING_SIZE },
2318 [R600_HW_STAGE_ES] = { R_008C50_SQ_ESTMP_RING_BASE, R_028908_SQ_ESTMP_RING_ITEMSIZE, R_008C54_SQ_ESTMP_RING_SIZE },
2319 [EG_HW_STAGE_LS] = { R_008E10_SQ_LSTMP_RING_BASE, R_028830_SQ_LSTMP_RING_ITEMSIZE, R_008E14_SQ_LSTMP_RING_SIZE },
2320 [EG_HW_STAGE_HS] = { R_008E18_SQ_HSTMP_RING_BASE, R_028834_SQ_HSTMP_RING_ITEMSIZE, R_008E1C_SQ_HSTMP_RING_SIZE }
2321 };
2322
2323 for (unsigned i = 0; i < EG_NUM_HW_STAGES; i++) {
2324 struct r600_pipe_shader *stage = rctx->hw_shader_stages[i].shader;
2325
2326 if (stage && unlikely(stage->scratch_space_needed)) {
2327 r600_setup_scratch_area_for_shader(rctx, stage,
2328 &rctx->scratch_buffers[i], regs[i].ring_base, regs[i].item_size, regs[i].ring_size);
2329 }
2330 }
2331 }
2332
evergreen_emit_sampler_views(struct r600_context * rctx,struct r600_samplerview_state * state,unsigned resource_id_base,unsigned pkt_flags)2333 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2334 struct r600_samplerview_state *state,
2335 unsigned resource_id_base, unsigned pkt_flags)
2336 {
2337 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2338 uint32_t dirty_mask = state->dirty_mask;
2339
2340 while (dirty_mask) {
2341 struct r600_pipe_sampler_view *rview;
2342 unsigned resource_index = u_bit_scan(&dirty_mask);
2343 unsigned reloc;
2344
2345 rview = state->views[resource_index];
2346 assert(rview);
2347
2348 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
2349 radeon_emit(cs, (resource_id_base + resource_index) * 8);
2350 radeon_emit_array(cs, rview->tex_resource_words, 8);
2351
2352 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2353 RADEON_USAGE_READ |
2354 r600_get_sampler_view_priority(rview->tex_resource));
2355 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2356 radeon_emit(cs, reloc);
2357
2358 if (!rview->skip_mip_address_reloc) {
2359 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
2360 radeon_emit(cs, reloc);
2361 }
2362 }
2363 state->dirty_mask = 0;
2364 }
2365
evergreen_emit_vs_sampler_views(struct r600_context * rctx,struct r600_atom * atom)2366 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2367 {
2368 if (rctx->vs_shader->current->shader.vs_as_ls) {
2369 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2370 EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0);
2371 } else {
2372 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2373 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2374 }
2375 }
2376
evergreen_emit_gs_sampler_views(struct r600_context * rctx,struct r600_atom * atom)2377 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2378 {
2379 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2380 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0);
2381 }
2382
evergreen_emit_tcs_sampler_views(struct r600_context * rctx,struct r600_atom * atom)2383 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2384 {
2385 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2386 EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0);
2387 }
2388
evergreen_emit_tes_sampler_views(struct r600_context * rctx,struct r600_atom * atom)2389 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2390 {
2391 if (!rctx->tes_shader)
2392 return;
2393 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2394 EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0);
2395 }
2396
evergreen_emit_ps_sampler_views(struct r600_context * rctx,struct r600_atom * atom)2397 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2398 {
2399 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2400 EG_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS, 0);
2401 }
2402
evergreen_emit_cs_sampler_views(struct r600_context * rctx,struct r600_atom * atom)2403 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2404 {
2405 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2406 EG_FETCH_CONSTANTS_OFFSET_CS + R600_MAX_CONST_BUFFERS, RADEON_CP_PACKET3_COMPUTE_MODE);
2407 }
2408
cayman_convert_border_color(union pipe_color_union * in,union pipe_color_union * out,struct pipe_sampler_view * view)2409 static void cayman_convert_border_color(union pipe_color_union *in,
2410 union pipe_color_union *out,
2411 struct pipe_sampler_view *view)
2412 {
2413 enum pipe_format format = view->format;
2414 const struct util_format_description *d = util_format_description(format);
2415
2416 if ((!util_format_is_alpha(format) &&
2417 !util_format_is_luminance(format) &&
2418 !util_format_is_luminance_alpha(format) &&
2419 !util_format_is_intensity(format) &&
2420 //!util_format_is_depth_or_stencil(format) &&
2421 (format != PIPE_FORMAT_RGTC1_SNORM) &&
2422 (format != PIPE_FORMAT_RGTC1_UNORM) &&
2423 (format != PIPE_FORMAT_RGTC2_SNORM) &&
2424 (format != PIPE_FORMAT_RGTC2_UNORM) &&
2425 !(d->channel[0].size < 8) &&
2426 (d->nr_channels > 2)) ||
2427 (util_format_is_srgb(format) ||
2428 util_format_is_s3tc(format))
2429 ) {
2430 const float values[PIPE_SWIZZLE_MAX] = {
2431 in->f[0], in->f[1], in->f[2], in->f[3], 0.0f, 1.0f, 0.0f /* none */
2432 };
2433
2434 STATIC_ASSERT(PIPE_SWIZZLE_0 == 4);
2435 STATIC_ASSERT(PIPE_SWIZZLE_1 == 5);
2436 STATIC_ASSERT(PIPE_SWIZZLE_NONE == 6);
2437 STATIC_ASSERT(PIPE_SWIZZLE_MAX == 7);
2438
2439 out->f[0] = values[view->swizzle_r];
2440 out->f[1] = values[view->swizzle_g];
2441 out->f[2] = values[view->swizzle_b];
2442 out->f[3] = values[view->swizzle_a];
2443 } else {
2444 memcpy(out->f, in->f, 4 * sizeof(float));
2445 }
2446 }
2447
evergreen_convert_border_color(union pipe_color_union * in,union pipe_color_union * out,struct pipe_sampler_view * view)2448 static void evergreen_convert_border_color(union pipe_color_union *in,
2449 union pipe_color_union *out,
2450 struct pipe_sampler_view *view)
2451 {
2452 enum pipe_format format = view->format;
2453 const struct util_format_description *d = util_format_description(format);
2454
2455 int swizzle[4] = { view->swizzle_r, view->swizzle_g, view->swizzle_b,
2456 view->swizzle_a };
2457
2458 bool is_lai = util_format_is_alpha(format) ||
2459 util_format_is_luminance(format) ||
2460 util_format_is_luminance_alpha(format) ||
2461 util_format_is_intensity(format) ||
2462 d->channel[0].size < 8;
2463
2464 if (is_lai) {
2465 for (int i = 0; i < 4; ++i) {
2466 swizzle[i] = i;
2467 }
2468 }
2469
2470 if (!util_format_is_depth_or_stencil(format)) {
2471
2472 for (int i = 0; i < 4; ++i) {
2473
2474 if (swizzle[i] == 4) {
2475 out->f[i] = 0.0f;
2476 continue;
2477 }
2478
2479 if (swizzle[i] == 5) {
2480 out->f[i] = 1.0f;
2481 continue;
2482 }
2483
2484 if (util_format_is_pure_integer(format)) {
2485 int cs = d->channel[d->swizzle[i]].size;
2486 if (d->channel[d->swizzle[i]].type == UTIL_FORMAT_TYPE_SIGNED)
2487 out->f[i] = ((double)(in->i[swizzle[i]])) / ((1ul << (cs - 1)) - 1 );
2488 else if (d->channel[d->swizzle[i]].type == UTIL_FORMAT_TYPE_UNSIGNED)
2489 out->f[i] = ((double)(in->ui[swizzle[i]])) / ((1ul << cs) - 1 );
2490 else
2491 out->f[i] = 0;
2492 } else {
2493 out->f[i] = in->f[swizzle[i]];
2494 }
2495 }
2496
2497 } else {
2498 switch (format) {
2499 case PIPE_FORMAT_X24S8_UINT:
2500 case PIPE_FORMAT_X32_S8X24_UINT:
2501 out->f[0] = (double)(in->ui[0]) / 255.0;
2502 out->f[1] = out->f[2] = out->f[3] = 0.0f;
2503 break;
2504 default:
2505 memcpy(out->f, in->f, 4 * sizeof(float));
2506 }
2507 }
2508 }
2509
evergreen_emit_sampler_states(struct r600_context * rctx,struct r600_textures_info * texinfo,unsigned resource_id_base,unsigned border_index_reg,unsigned pkt_flags)2510 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2511 struct r600_textures_info *texinfo,
2512 unsigned resource_id_base,
2513 unsigned border_index_reg,
2514 unsigned pkt_flags)
2515 {
2516 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2517 uint32_t dirty_mask = texinfo->states.dirty_mask;
2518 union pipe_color_union border_color = {{0,0,0,1}};
2519 union pipe_color_union *border_color_ptr = &border_color;
2520
2521 while (dirty_mask) {
2522 struct r600_pipe_sampler_state *rstate;
2523 unsigned i = u_bit_scan(&dirty_mask);
2524
2525 rstate = texinfo->states.states[i];
2526 assert(rstate);
2527
2528 if (rstate->border_color_use) {
2529 struct r600_pipe_sampler_view *rview = texinfo->views.views[i];
2530 if (rview) {
2531 if (rctx->b.gfx_level < CAYMAN) {
2532 evergreen_convert_border_color(&rstate->border_color,
2533 &border_color, &rview->base);
2534 } else {
2535 cayman_convert_border_color(&rstate->border_color,
2536 &border_color, &rview->base);
2537 }
2538 } else {
2539 border_color_ptr = &rstate->border_color;
2540 }
2541 }
2542
2543 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
2544 radeon_emit(cs, (resource_id_base + i) * 3);
2545 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
2546
2547 if (rstate->border_color_use) {
2548 radeon_set_config_reg_seq(cs, border_index_reg, 5);
2549 radeon_emit(cs, i);
2550 radeon_emit_array(cs, border_color_ptr->ui, 4);
2551 }
2552 }
2553 texinfo->states.dirty_mask = 0;
2554 }
2555
evergreen_emit_vs_sampler_states(struct r600_context * rctx,struct r600_atom * atom)2556 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2557 {
2558 if (rctx->vs_shader->current->shader.vs_as_ls) {
2559 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2560 R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2561 } else {
2562 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2563 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2564 }
2565 }
2566
evergreen_emit_gs_sampler_states(struct r600_context * rctx,struct r600_atom * atom)2567 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2568 {
2569 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2570 R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
2571 }
2572
evergreen_emit_tcs_sampler_states(struct r600_context * rctx,struct r600_atom * atom)2573 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2574 {
2575 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2576 R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0);
2577 }
2578
evergreen_emit_tes_sampler_states(struct r600_context * rctx,struct r600_atom * atom)2579 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2580 {
2581 if (!rctx->tes_shader)
2582 return;
2583 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2584 R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
2585 }
2586
evergreen_emit_ps_sampler_states(struct r600_context * rctx,struct r600_atom * atom)2587 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2588 {
2589 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2590 R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
2591 }
2592
evergreen_emit_cs_sampler_states(struct r600_context * rctx,struct r600_atom * atom)2593 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2594 {
2595 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2596 R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
2597 RADEON_CP_PACKET3_COMPUTE_MODE);
2598 }
2599
evergreen_emit_sample_mask(struct r600_context * rctx,struct r600_atom * a)2600 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2601 {
2602 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2603 uint8_t mask = s->sample_mask;
2604
2605 radeon_set_context_reg(&rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2606 mask | (mask << 8) | (mask << 16) | (mask << 24));
2607 }
2608
cayman_emit_sample_mask(struct r600_context * rctx,struct r600_atom * a)2609 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2610 {
2611 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2612 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2613 uint16_t mask = s->sample_mask;
2614
2615 radeon_set_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2616 radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2617 radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2618 }
2619
evergreen_emit_vertex_fetch_shader(struct r600_context * rctx,struct r600_atom * a)2620 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2621 {
2622 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2623 struct r600_cso_state *state = (struct r600_cso_state*)a;
2624 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2625
2626 if (!shader)
2627 return;
2628
2629 radeon_set_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
2630 (shader->buffer->gpu_address + shader->offset) >> 8);
2631 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2632 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2633 RADEON_USAGE_READ |
2634 RADEON_PRIO_SHADER_BINARY));
2635 }
2636
evergreen_emit_shader_stages(struct r600_context * rctx,struct r600_atom * a)2637 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2638 {
2639 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2640 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2641
2642 uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0;
2643
2644 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2645 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2646 primid = 1;
2647 }
2648
2649 if (state->geom_enable) {
2650 uint32_t cut_val;
2651
2652 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2653 cut_val = V_028A40_GS_CUT_128;
2654 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2655 cut_val = V_028A40_GS_CUT_256;
2656 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2657 cut_val = V_028A40_GS_CUT_512;
2658 else
2659 cut_val = V_028A40_GS_CUT_1024;
2660
2661 v = S_028B54_GS_EN(1) |
2662 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2663 if (!rctx->tes_shader)
2664 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
2665
2666 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2667 S_028A40_CUT_MODE(cut_val);
2668
2669 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2670 primid = 1;
2671 }
2672
2673 if (rctx->tes_shader) {
2674 uint32_t type, partitioning, topology;
2675 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2676 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2677 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2678 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2679 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2680 switch (tes_prim_mode) {
2681 case MESA_PRIM_LINES:
2682 type = V_028B6C_TESS_ISOLINE;
2683 break;
2684 case MESA_PRIM_TRIANGLES:
2685 type = V_028B6C_TESS_TRIANGLE;
2686 break;
2687 case MESA_PRIM_QUADS:
2688 type = V_028B6C_TESS_QUAD;
2689 break;
2690 default:
2691 assert(0);
2692 return;
2693 }
2694
2695 switch (tes_spacing) {
2696 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
2697 partitioning = V_028B6C_PART_FRAC_ODD;
2698 break;
2699 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
2700 partitioning = V_028B6C_PART_FRAC_EVEN;
2701 break;
2702 case PIPE_TESS_SPACING_EQUAL:
2703 partitioning = V_028B6C_PART_INTEGER;
2704 break;
2705 default:
2706 assert(0);
2707 return;
2708 }
2709
2710 if (tes_point_mode)
2711 topology = V_028B6C_OUTPUT_POINT;
2712 else if (tes_prim_mode == MESA_PRIM_LINES)
2713 topology = V_028B6C_OUTPUT_LINE;
2714 else if (tes_vertex_order_cw)
2715 /* XXX follow radeonsi and invert */
2716 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2717 else
2718 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2719
2720 tf_param = S_028B6C_TYPE(type) |
2721 S_028B6C_PARTITIONING(partitioning) |
2722 S_028B6C_TOPOLOGY(topology);
2723 }
2724
2725 if (rctx->tes_shader) {
2726 v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2727 S_028B54_HS_EN(1);
2728 if (!state->geom_enable)
2729 v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2730 else
2731 v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
2732 }
2733
2734 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 );
2735 radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
2736 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
2737 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
2738 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param);
2739 }
2740
evergreen_emit_gs_rings(struct r600_context * rctx,struct r600_atom * a)2741 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2742 {
2743 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2744 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2745 struct r600_resource *rbuffer;
2746
2747 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2748 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2749 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2750
2751 if (state->enable) {
2752 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2753 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
2754 rbuffer->gpu_address >> 8);
2755 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2756 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2757 RADEON_USAGE_READWRITE |
2758 RADEON_PRIO_SHADER_RINGS));
2759 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
2760 state->esgs_ring.buffer_size >> 8);
2761
2762 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2763 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
2764 rbuffer->gpu_address >> 8);
2765 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2766 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2767 RADEON_USAGE_READWRITE |
2768 RADEON_PRIO_SHADER_RINGS));
2769 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2770 state->gsvs_ring.buffer_size >> 8);
2771 } else {
2772 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2773 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2774 }
2775
2776 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2777 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2778 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2779 }
2780
cayman_init_common_regs(struct r600_command_buffer * cb,enum amd_gfx_level gfx_level,enum radeon_family ctx_family,int ctx_drm_minor)2781 void cayman_init_common_regs(struct r600_command_buffer *cb,
2782 enum amd_gfx_level gfx_level,
2783 enum radeon_family ctx_family,
2784 int ctx_drm_minor)
2785 {
2786 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2787 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2788 /* always set the temp clauses */
2789 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2790
2791 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2792 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2793 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2794
2795 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2796
2797 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
2798 r600_store_value(cb, 0);
2799 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
2800
2801 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2802 }
2803
cayman_init_atom_start_cs(struct r600_context * rctx)2804 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2805 {
2806 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2807 int i;
2808
2809 r600_init_command_buffer(cb, 338);
2810
2811 /* This must be first. */
2812 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2813 r600_store_value(cb, 0x80000000);
2814 r600_store_value(cb, 0x80000000);
2815
2816 /* We're setting config registers here. */
2817 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2818 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2819
2820 /* This enables pipeline stat & streamout queries.
2821 * They are only disabled by blits.
2822 */
2823 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2824 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2825
2826 cayman_init_common_regs(cb, rctx->b.gfx_level,
2827 rctx->b.family, rctx->screen->b.info.drm_minor);
2828
2829 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2830 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2831
2832 /* remove LS/HS from one SIMD for hw workaround */
2833 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
2834 r600_store_value(cb, 0xffffffff);
2835 r600_store_value(cb, 0xffffffff);
2836 r600_store_value(cb, 0xfffffffe);
2837
2838 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2839 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2840 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2841 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2842 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2843 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2844 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2845
2846 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2847 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2848 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2849 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2850 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2851
2852 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2853 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2854 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2855 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2856 r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2857 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2858 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2859 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2860 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2861 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2862 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2863 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2864 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2865 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2866
2867 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
2868
2869 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2870
2871 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2872 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2873 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2874
2875 r600_store_context_reg(cb, R_028724_GDS_ADDR_SIZE, 0x3fff);
2876 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
2877 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
2878 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2879
2880 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2881
2882 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2883 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2884 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2885
2886 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2887
2888 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2889
2890 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2891
2892 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2893 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2894 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2895 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2896
2897 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2898 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2899
2900 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2901 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2902
2903 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2904 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2905 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2906
2907 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2908 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2909 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2910
2911 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2912 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2913 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2914 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2915 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2916 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2917
2918 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2919
2920 /* to avoid GPU doing any preloading of constant from random address */
2921 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2922 for (i = 0; i < 16; i++)
2923 r600_store_value(cb, 0);
2924
2925 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2926 for (i = 0; i < 16; i++)
2927 r600_store_value(cb, 0);
2928
2929 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2930 for (i = 0; i < 16; i++)
2931 r600_store_value(cb, 0);
2932
2933 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
2934 for (i = 0; i < 16; i++)
2935 r600_store_value(cb, 0);
2936
2937 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
2938 for (i = 0; i < 16; i++)
2939 r600_store_value(cb, 0);
2940
2941 if (rctx->screen->b.has_streamout) {
2942 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2943 }
2944
2945 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
2946 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
2947 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2948 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
2949 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
2950 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
2951
2952 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
2953 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
2954 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
2955 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
2956 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2957 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2958 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
2959 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
2960 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
2961 }
2962
evergreen_init_common_regs(struct r600_context * rctx,struct r600_command_buffer * cb,enum amd_gfx_level gfx_level,enum radeon_family ctx_family,int ctx_drm_minor)2963 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2964 enum amd_gfx_level gfx_level,
2965 enum radeon_family ctx_family,
2966 int ctx_drm_minor)
2967 {
2968 int ps_prio;
2969 int vs_prio;
2970 int gs_prio;
2971 int es_prio;
2972
2973 int hs_prio;
2974 int cs_prio;
2975 int ls_prio;
2976
2977 unsigned tmp;
2978
2979 ps_prio = 0;
2980 vs_prio = 1;
2981 gs_prio = 2;
2982 es_prio = 3;
2983 hs_prio = 3;
2984 ls_prio = 3;
2985 cs_prio = 0;
2986
2987 rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2988 rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2989 rctx->r6xx_num_clause_temp_gprs = 4;
2990 rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2991 rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2992 rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2993 rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2994
2995 tmp = 0;
2996 switch (ctx_family) {
2997 case CHIP_CEDAR:
2998 case CHIP_PALM:
2999 case CHIP_SUMO:
3000 case CHIP_SUMO2:
3001 case CHIP_CAICOS:
3002 break;
3003 default:
3004 tmp |= S_008C00_VC_ENABLE(1);
3005 break;
3006 }
3007 tmp |= S_008C00_EXPORT_SRC_C(1);
3008 tmp |= S_008C00_CS_PRIO(cs_prio);
3009 tmp |= S_008C00_LS_PRIO(ls_prio);
3010 tmp |= S_008C00_HS_PRIO(hs_prio);
3011 tmp |= S_008C00_PS_PRIO(ps_prio);
3012 tmp |= S_008C00_VS_PRIO(vs_prio);
3013 tmp |= S_008C00_GS_PRIO(gs_prio);
3014 tmp |= S_008C00_ES_PRIO(es_prio);
3015
3016 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1);
3017 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
3018
3019 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
3020 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
3021 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
3022
3023 /* The cs checker requires this register to be set. */
3024 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
3025
3026 r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
3027 r600_store_value(cb, 0);
3028 r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
3029
3030 return;
3031 }
3032
evergreen_init_atom_start_cs(struct r600_context * rctx)3033 void evergreen_init_atom_start_cs(struct r600_context *rctx)
3034 {
3035 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
3036 int num_ps_threads;
3037 int num_vs_threads;
3038 int num_gs_threads;
3039 int num_es_threads;
3040 int num_hs_threads;
3041 int num_ls_threads;
3042
3043 int num_ps_stack_entries;
3044 int num_vs_stack_entries;
3045 int num_gs_stack_entries;
3046 int num_es_stack_entries;
3047 int num_hs_stack_entries;
3048 int num_ls_stack_entries;
3049 enum radeon_family family;
3050 unsigned tmp, i;
3051
3052 if (rctx->b.gfx_level == CAYMAN) {
3053 cayman_init_atom_start_cs(rctx);
3054 return;
3055 }
3056
3057 r600_init_command_buffer(cb, 338);
3058
3059 /* This must be first. */
3060 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
3061 r600_store_value(cb, 0x80000000);
3062 r600_store_value(cb, 0x80000000);
3063
3064 /* We're setting config registers here. */
3065 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
3066 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3067
3068 /* This enables pipeline stat & streamout queries.
3069 * They are only disabled by blits.
3070 */
3071 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
3072 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
3073
3074 evergreen_init_common_regs(rctx, cb, rctx->b.gfx_level,
3075 rctx->b.family, rctx->screen->b.info.drm_minor);
3076
3077 family = rctx->b.family;
3078 switch (family) {
3079 case CHIP_CEDAR:
3080 default:
3081 num_ps_threads = 96;
3082 num_vs_threads = 16;
3083 num_gs_threads = 16;
3084 num_es_threads = 16;
3085 num_hs_threads = 16;
3086 num_ls_threads = 16;
3087 num_ps_stack_entries = 42;
3088 num_vs_stack_entries = 42;
3089 num_gs_stack_entries = 42;
3090 num_es_stack_entries = 42;
3091 num_hs_stack_entries = 42;
3092 num_ls_stack_entries = 42;
3093 break;
3094 case CHIP_REDWOOD:
3095 num_ps_threads = 128;
3096 num_vs_threads = 20;
3097 num_gs_threads = 20;
3098 num_es_threads = 20;
3099 num_hs_threads = 20;
3100 num_ls_threads = 20;
3101 num_ps_stack_entries = 42;
3102 num_vs_stack_entries = 42;
3103 num_gs_stack_entries = 42;
3104 num_es_stack_entries = 42;
3105 num_hs_stack_entries = 42;
3106 num_ls_stack_entries = 42;
3107 break;
3108 case CHIP_JUNIPER:
3109 num_ps_threads = 128;
3110 num_vs_threads = 20;
3111 num_gs_threads = 20;
3112 num_es_threads = 20;
3113 num_hs_threads = 20;
3114 num_ls_threads = 20;
3115 num_ps_stack_entries = 85;
3116 num_vs_stack_entries = 85;
3117 num_gs_stack_entries = 85;
3118 num_es_stack_entries = 85;
3119 num_hs_stack_entries = 85;
3120 num_ls_stack_entries = 85;
3121 break;
3122 case CHIP_CYPRESS:
3123 case CHIP_HEMLOCK:
3124 num_ps_threads = 128;
3125 num_vs_threads = 20;
3126 num_gs_threads = 20;
3127 num_es_threads = 20;
3128 num_hs_threads = 20;
3129 num_ls_threads = 20;
3130 num_ps_stack_entries = 85;
3131 num_vs_stack_entries = 85;
3132 num_gs_stack_entries = 85;
3133 num_es_stack_entries = 85;
3134 num_hs_stack_entries = 85;
3135 num_ls_stack_entries = 85;
3136 break;
3137 case CHIP_PALM:
3138 num_ps_threads = 96;
3139 num_vs_threads = 16;
3140 num_gs_threads = 16;
3141 num_es_threads = 16;
3142 num_hs_threads = 16;
3143 num_ls_threads = 16;
3144 num_ps_stack_entries = 42;
3145 num_vs_stack_entries = 42;
3146 num_gs_stack_entries = 42;
3147 num_es_stack_entries = 42;
3148 num_hs_stack_entries = 42;
3149 num_ls_stack_entries = 42;
3150 break;
3151 case CHIP_SUMO:
3152 num_ps_threads = 96;
3153 num_vs_threads = 25;
3154 num_gs_threads = 25;
3155 num_es_threads = 25;
3156 num_hs_threads = 16;
3157 num_ls_threads = 16;
3158 num_ps_stack_entries = 42;
3159 num_vs_stack_entries = 42;
3160 num_gs_stack_entries = 42;
3161 num_es_stack_entries = 42;
3162 num_hs_stack_entries = 42;
3163 num_ls_stack_entries = 42;
3164 break;
3165 case CHIP_SUMO2:
3166 num_ps_threads = 96;
3167 num_vs_threads = 25;
3168 num_gs_threads = 25;
3169 num_es_threads = 25;
3170 num_hs_threads = 16;
3171 num_ls_threads = 16;
3172 num_ps_stack_entries = 85;
3173 num_vs_stack_entries = 85;
3174 num_gs_stack_entries = 85;
3175 num_es_stack_entries = 85;
3176 num_hs_stack_entries = 85;
3177 num_ls_stack_entries = 85;
3178 break;
3179 case CHIP_BARTS:
3180 num_ps_threads = 128;
3181 num_vs_threads = 20;
3182 num_gs_threads = 20;
3183 num_es_threads = 20;
3184 num_hs_threads = 20;
3185 num_ls_threads = 20;
3186 num_ps_stack_entries = 85;
3187 num_vs_stack_entries = 85;
3188 num_gs_stack_entries = 85;
3189 num_es_stack_entries = 85;
3190 num_hs_stack_entries = 85;
3191 num_ls_stack_entries = 85;
3192 break;
3193 case CHIP_TURKS:
3194 num_ps_threads = 128;
3195 num_vs_threads = 20;
3196 num_gs_threads = 20;
3197 num_es_threads = 20;
3198 num_hs_threads = 20;
3199 num_ls_threads = 20;
3200 num_ps_stack_entries = 42;
3201 num_vs_stack_entries = 42;
3202 num_gs_stack_entries = 42;
3203 num_es_stack_entries = 42;
3204 num_hs_stack_entries = 42;
3205 num_ls_stack_entries = 42;
3206 break;
3207 case CHIP_CAICOS:
3208 num_ps_threads = 96;
3209 num_vs_threads = 10;
3210 num_gs_threads = 10;
3211 num_es_threads = 10;
3212 num_hs_threads = 10;
3213 num_ls_threads = 10;
3214 num_ps_stack_entries = 42;
3215 num_vs_stack_entries = 42;
3216 num_gs_stack_entries = 42;
3217 num_es_stack_entries = 42;
3218 num_hs_stack_entries = 42;
3219 num_ls_stack_entries = 42;
3220 break;
3221 }
3222
3223 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
3224 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
3225 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
3226 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
3227
3228 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
3229 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
3230
3231 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
3232 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
3233 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
3234
3235 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
3236 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
3237 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
3238
3239 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
3240 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
3241 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
3242
3243 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
3244 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
3245 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3246
3247 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
3248 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
3249
3250 /* remove LS/HS from one SIMD for hw workaround */
3251 r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3);
3252 r600_store_value(cb, 0xffffffff);
3253 r600_store_value(cb, 0xffffffff);
3254 r600_store_value(cb, 0xfffffffe);
3255
3256 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
3257 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
3258
3259 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
3260 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
3261 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
3262 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
3263 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
3264 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
3265 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
3266
3267 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3268 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
3269 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
3270 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
3271 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
3272
3273 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
3274 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
3275 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
3276 r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
3277 r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
3278 r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */
3279 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
3280 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
3281 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
3282 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
3283 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
3284 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
3285 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
3286 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
3287
3288 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
3289
3290 r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0);
3291
3292 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
3293 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
3294 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
3295
3296 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
3297
3298 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
3299
3300 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
3301 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3302 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3303
3304 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
3305 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
3306
3307 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
3308 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
3309 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
3310 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
3311
3312 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
3313 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
3314 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
3315
3316 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
3317 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
3318 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
3319
3320 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3321 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3322 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3323 r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3324 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
3325 r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3326 r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
3327
3328 /* to avoid GPU doing any preloading of constant from random address */
3329 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
3330 for (i = 0; i < 16; i++)
3331 r600_store_value(cb, 0);
3332
3333 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
3334 for (i = 0; i < 16; i++)
3335 r600_store_value(cb, 0);
3336
3337 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
3338 for (i = 0; i < 16; i++)
3339 r600_store_value(cb, 0);
3340
3341 r600_store_context_reg_seq(cb, R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, 16);
3342 for (i = 0; i < 16; i++)
3343 r600_store_value(cb, 0);
3344
3345 r600_store_context_reg_seq(cb, R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, 16);
3346 for (i = 0; i < 16; i++)
3347 r600_store_value(cb, 0);
3348
3349 r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
3350
3351 if (rctx->screen->b.has_streamout) {
3352 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3353 }
3354
3355 r600_store_context_reg(cb, R_028010_DB_RENDER_OVERRIDE2, 0);
3356 r600_store_context_reg(cb, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3357 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
3358 r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2);
3359 r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */
3360 r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */
3361
3362 r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2);
3363 r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */
3364 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
3365
3366 if (rctx->b.family == CHIP_CAICOS) {
3367 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2);
3368 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3369 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3370 r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0);
3371 } else {
3372 r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7);
3373 r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */
3374 r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */
3375 r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */
3376 r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */
3377 r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */
3378 r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */
3379 r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */
3380 }
3381
3382 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
3383 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
3384 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
3385 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF);
3386 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF);
3387 }
3388
evergreen_update_ps_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)3389 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3390 {
3391 struct r600_context *rctx = (struct r600_context *)ctx;
3392 struct r600_command_buffer *cb = &shader->command_buffer;
3393 struct r600_shader *rshader = &shader->shader;
3394 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
3395 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
3396 int ninterp = 0;
3397 bool have_perspective = false, have_linear = false;
3398 static const unsigned spi_baryc_enable_bit[6] = {
3399 S_0286E0_PERSP_SAMPLE_ENA(1),
3400 S_0286E0_PERSP_CENTER_ENA(1),
3401 S_0286E0_PERSP_CENTROID_ENA(1),
3402 S_0286E0_LINEAR_SAMPLE_ENA(1),
3403 S_0286E0_LINEAR_CENTER_ENA(1),
3404 S_0286E0_LINEAR_CENTROID_ENA(1)
3405 };
3406 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
3407 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
3408 uint32_t spi_ps_input_cntl[32];
3409
3410 /* Pull any state we use out of rctx. Make sure that any additional
3411 * state added to this list is also checked in the caller in
3412 * r600_update_derived_state().
3413 */
3414 bool sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3415 bool flatshade = rctx->rasterizer ? rctx->rasterizer->flatshade : 0;
3416 bool msaa = rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0;
3417
3418 if (!cb->buf) {
3419 r600_init_command_buffer(cb, 64);
3420 } else {
3421 cb->num_dw = 0;
3422 }
3423
3424 for (i = 0; i < rshader->ninput; i++) {
3425 const gl_varying_slot varying_slot = rshader->input[i].varying_slot;
3426
3427 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
3428 POSITION goes via GPRs from the SC so isn't counted */
3429 if (varying_slot == VARYING_SLOT_POS)
3430 pos_index = i;
3431 else if (varying_slot == VARYING_SLOT_FACE) {
3432 if (face_index == -1)
3433 face_index = i;
3434 }
3435 else if (rshader->input[i].system_value == SYSTEM_VALUE_SAMPLE_MASK_IN) {
3436 if (face_index == -1)
3437 face_index = i; /* lives in same register, same enable bit */
3438 }
3439 else if (rshader->input[i].system_value == SYSTEM_VALUE_SAMPLE_ID) {
3440 fixed_pt_position_index = i;
3441 }
3442 else {
3443 ninterp++;
3444 int k = eg_get_interpolator_index(
3445 rshader->input[i].interpolate,
3446 rshader->input[i].interpolate_location);
3447 if (k >= 0) {
3448 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3449 have_perspective |= k < 3;
3450 have_linear |= !(k < 3);
3451 if (rshader->input[i].uses_interpolate_at_centroid) {
3452 k = eg_get_interpolator_index(
3453 rshader->input[i].interpolate,
3454 TGSI_INTERPOLATE_LOC_CENTROID);
3455 spi_baryc_cntl |= spi_baryc_enable_bit[k];
3456 }
3457 }
3458 }
3459
3460 sid = rshader->input[i].spi_sid;
3461
3462 if (sid) {
3463 tmp = S_028644_SEMANTIC(sid);
3464
3465 /* D3D 9 behaviour. GL is undefined */
3466 if (varying_slot == VARYING_SLOT_COL0)
3467 tmp |= S_028644_DEFAULT_VAL(3);
3468
3469 if (varying_slot == VARYING_SLOT_POS ||
3470 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3471 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR && flatshade)) {
3472 tmp |= S_028644_FLAT_SHADE(1);
3473 }
3474
3475 if (varying_slot == VARYING_SLOT_PNTC ||
3476 (varying_slot >= VARYING_SLOT_TEX0 && varying_slot <= VARYING_SLOT_TEX7 &&
3477 (sprite_coord_enable & (1 << ((int)varying_slot - (int)VARYING_SLOT_TEX0))))) {
3478 tmp |= S_028644_PT_SPRITE_TEX(1);
3479 }
3480
3481 spi_ps_input_cntl[num++] = tmp;
3482 }
3483 }
3484
3485 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, num);
3486 r600_store_array(cb, num, spi_ps_input_cntl);
3487
3488 exports_ps = 0;
3489 for (i = 0; i < rshader->noutput; i++) {
3490 switch (rshader->output[i].frag_result) {
3491 case FRAG_RESULT_DEPTH:
3492 z_export = 1;
3493 exports_ps |= 1;
3494 break;
3495 case FRAG_RESULT_STENCIL:
3496 stencil_export = 1;
3497 exports_ps |= 1;
3498 break;
3499 case FRAG_RESULT_SAMPLE_MASK:
3500 if (msaa)
3501 mask_export = 1;
3502 exports_ps |= 1;
3503 break;
3504 default:
3505 break;
3506 }
3507 }
3508 if (rshader->uses_kill)
3509 db_shader_control |= S_02880C_KILL_ENABLE(1);
3510
3511 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3512 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3513 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
3514
3515 if (shader->selector->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
3516 db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
3517 S_02880C_EXEC_ON_NOOP(shader->selector->info.writes_memory);
3518 } else if (shader->selector->info.writes_memory) {
3519 db_shader_control |= S_02880C_EXEC_ON_HIER_FAIL(1);
3520 }
3521
3522 switch (rshader->ps_conservative_z) {
3523 default: /* fall through */
3524 case FRAG_DEPTH_LAYOUT_ANY:
3525 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3526 break;
3527 case FRAG_DEPTH_LAYOUT_GREATER:
3528 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3529 break;
3530 case FRAG_DEPTH_LAYOUT_LESS:
3531 db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3532 break;
3533 }
3534
3535 num_cout = rshader->ps_export_highest + 1;
3536
3537 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3538 if (!exports_ps) {
3539 /* always at least export 1 component per pixel */
3540 exports_ps = 2;
3541 }
3542 shader->nr_ps_color_outputs = num_cout;
3543 shader->ps_color_export_mask = rshader->ps_color_export_mask;
3544 if (ninterp == 0) {
3545 ninterp = 1;
3546 have_perspective = true;
3547 }
3548 if (!spi_baryc_cntl)
3549 spi_baryc_cntl |= spi_baryc_enable_bit[0];
3550
3551 if (!have_perspective && !have_linear)
3552 have_perspective = true;
3553
3554 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3555 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3556 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3557 spi_input_z = 0;
3558 if (pos_index != -1) {
3559 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3560 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
3561 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3562 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
3563 }
3564
3565 spi_ps_in_control_1 = 0;
3566 if (face_index != -1) {
3567 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3568 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3569 }
3570 if (fixed_pt_position_index != -1) {
3571 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
3572 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
3573 }
3574
3575 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
3576 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
3577 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
3578
3579 r600_store_context_reg(cb, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
3580 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
3581 r600_store_context_reg(cb, R_02884C_SQ_PGM_EXPORTS_PS, exports_ps);
3582
3583 r600_store_context_reg_seq(cb, R_028840_SQ_PGM_START_PS, 2);
3584 r600_store_value(cb, shader->bo->gpu_address >> 8);
3585 r600_store_value(cb, /* R_028844_SQ_PGM_RESOURCES_PS */
3586 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3587 S_028844_PRIME_CACHE_ON_DRAW(1) |
3588 S_028844_DX10_CLAMP(1) |
3589 S_028844_STACK_SIZE(rshader->bc.nstack));
3590 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3591
3592 shader->db_shader_control = db_shader_control;
3593 shader->ps_depth_export = z_export | stencil_export | mask_export;
3594
3595 shader->sprite_coord_enable = sprite_coord_enable;
3596 shader->flatshade = flatshade;
3597 shader->msaa = msaa;
3598 }
3599
evergreen_update_es_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)3600 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3601 {
3602 struct r600_command_buffer *cb = &shader->command_buffer;
3603 struct r600_shader *rshader = &shader->shader;
3604
3605 r600_init_command_buffer(cb, 32);
3606
3607 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
3608 S_028890_NUM_GPRS(rshader->bc.ngpr) |
3609 S_028890_DX10_CLAMP(1) |
3610 S_028890_STACK_SIZE(rshader->bc.nstack));
3611 r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
3612 shader->bo->gpu_address >> 8);
3613 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3614 }
3615
evergreen_update_gs_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)3616 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3617 {
3618 struct r600_command_buffer *cb = &shader->command_buffer;
3619 struct r600_shader *rshader = &shader->shader;
3620 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3621 unsigned gsvs_itemsizes[4] = {
3622 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3623 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3624 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3625 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3626 };
3627
3628 r600_init_command_buffer(cb, 64);
3629
3630 /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
3631
3632
3633 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
3634 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3635 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
3636 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3637
3638 r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
3639 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3640 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3641 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
3642 r600_store_value(cb, cp_shader->ring_item_sizes[0] >> 2);
3643 r600_store_value(cb, cp_shader->ring_item_sizes[1] >> 2);
3644 r600_store_value(cb, cp_shader->ring_item_sizes[2] >> 2);
3645 r600_store_value(cb, cp_shader->ring_item_sizes[3] >> 2);
3646
3647 r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
3648 (rshader->ring_item_sizes[0]) >> 2);
3649
3650 r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
3651 gsvs_itemsizes[0] +
3652 gsvs_itemsizes[1] +
3653 gsvs_itemsizes[2] +
3654 gsvs_itemsizes[3]);
3655
3656 r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
3657 r600_store_value(cb, gsvs_itemsizes[0]);
3658 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
3659 r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] + gsvs_itemsizes[2]);
3660
3661 /* FIXME calculate these values somehow ??? */
3662 r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
3663 r600_store_value(cb, 0x80); /* GS_PER_ES */
3664 r600_store_value(cb, 0x100); /* ES_PER_GS */
3665 r600_store_value(cb, 0x2); /* GS_PER_VS */
3666
3667 r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
3668 S_028878_NUM_GPRS(rshader->bc.ngpr) |
3669 S_028878_DX10_CLAMP(1) |
3670 S_028878_STACK_SIZE(rshader->bc.nstack));
3671 r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
3672 shader->bo->gpu_address >> 8);
3673 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3674 }
3675
3676
evergreen_update_vs_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)3677 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3678 {
3679 struct r600_command_buffer *cb = &shader->command_buffer;
3680 struct r600_shader *rshader = &shader->shader;
3681 unsigned spi_vs_out_id[10] = {};
3682 unsigned i;
3683
3684 for (i = 0; i < rshader->noutput; i++) {
3685 const int param = rshader->output[i].export_param;
3686 if (param < 0)
3687 continue;
3688 unsigned *const param_spi_vs_out_id = &spi_vs_out_id[param / 4];
3689 const unsigned param_shift = (param & 3) * 8;
3690 assert(!(*param_spi_vs_out_id & (0xFFu << param_shift)));
3691 *param_spi_vs_out_id |= (unsigned)rshader->output[i].spi_sid << param_shift;
3692 }
3693
3694 r600_init_command_buffer(cb, 32);
3695
3696 r600_store_context_reg_seq(cb, R_02861C_SPI_VS_OUT_ID_0, 10);
3697 for (i = 0; i < 10; i++) {
3698 r600_store_value(cb, spi_vs_out_id[i]);
3699 }
3700
3701 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
3702 S_0286C4_VS_EXPORT_COUNT(rshader->highest_export_param));
3703 r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
3704 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3705 S_028860_DX10_CLAMP(1) |
3706 S_028860_STACK_SIZE(rshader->bc.nstack));
3707 if (rshader->vs_position_window_space) {
3708 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3709 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
3710 } else {
3711 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
3712 S_028818_VTX_W0_FMT(1) |
3713 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3714 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3715 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3716
3717 }
3718 r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
3719 shader->bo->gpu_address >> 8);
3720 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3721
3722 shader->pa_cl_vs_out_cntl =
3723 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->cc_dist_mask & 0x0F) != 0) |
3724 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->cc_dist_mask & 0xF0) != 0) |
3725 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3726 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
3727 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
3728 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
3729 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
3730 }
3731
evergreen_update_hs_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)3732 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3733 {
3734 struct r600_command_buffer *cb = &shader->command_buffer;
3735 struct r600_shader *rshader = &shader->shader;
3736
3737 r600_init_command_buffer(cb, 32);
3738 r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS,
3739 S_0288BC_NUM_GPRS(rshader->bc.ngpr) |
3740 S_0288BC_DX10_CLAMP(1) |
3741 S_0288BC_STACK_SIZE(rshader->bc.nstack));
3742 r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS,
3743 shader->bo->gpu_address >> 8);
3744 }
3745
evergreen_update_ls_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)3746 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3747 {
3748 struct r600_command_buffer *cb = &shader->command_buffer;
3749 struct r600_shader *rshader = &shader->shader;
3750
3751 r600_init_command_buffer(cb, 32);
3752 r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS,
3753 S_0288D4_NUM_GPRS(rshader->bc.ngpr) |
3754 S_0288D4_DX10_CLAMP(1) |
3755 S_0288D4_STACK_SIZE(rshader->bc.nstack));
3756 r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS,
3757 shader->bo->gpu_address >> 8);
3758 }
evergreen_create_resolve_blend(struct r600_context * rctx)3759 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3760 {
3761 struct pipe_blend_state blend;
3762
3763 memset(&blend, 0, sizeof(blend));
3764 blend.independent_blend_enable = true;
3765 blend.rt[0].colormask = 0xf;
3766 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3767 }
3768
evergreen_create_decompress_blend(struct r600_context * rctx)3769 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3770 {
3771 struct pipe_blend_state blend;
3772 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3773 V_028808_CB_FMASK_DECOMPRESS : V_028808_CB_DECOMPRESS;
3774
3775 memset(&blend, 0, sizeof(blend));
3776 blend.independent_blend_enable = true;
3777 blend.rt[0].colormask = 0xf;
3778 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3779 }
3780
evergreen_create_fastclear_blend(struct r600_context * rctx)3781 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3782 {
3783 struct pipe_blend_state blend;
3784 unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
3785
3786 memset(&blend, 0, sizeof(blend));
3787 blend.independent_blend_enable = true;
3788 blend.rt[0].colormask = 0xf;
3789 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3790 }
3791
evergreen_create_db_flush_dsa(struct r600_context * rctx)3792 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3793 {
3794 struct pipe_depth_stencil_alpha_state dsa = {{{0}}};
3795
3796 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3797 }
3798
evergreen_update_db_shader_control(struct r600_context * rctx)3799 void evergreen_update_db_shader_control(struct r600_context * rctx)
3800 {
3801 bool dual_export;
3802 unsigned db_shader_control;
3803
3804 if (!rctx->ps_shader) {
3805 return;
3806 }
3807
3808 dual_export = rctx->framebuffer.export_16bpc &&
3809 !rctx->ps_shader->current->ps_depth_export;
3810
3811 db_shader_control = rctx->ps_shader->current->db_shader_control |
3812 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3813 S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
3814 V_02880C_EXPORT_DB_FULL) |
3815 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3816
3817 /* When alpha test is enabled we can't trust the hw to make the proper
3818 * decision on the order in which ztest should be run related to fragment
3819 * shader execution.
3820 *
3821 * If alpha test is enabled perform early z rejection (RE_Z) but don't early
3822 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
3823 * execution and thus after alpha test so if discarded by the alpha test
3824 * the z value is not written.
3825 * If ReZ is enabled, and the zfunc/zenable/zwrite values change you can
3826 * get a hang unless you flush the DB in between. For now just use
3827 * LATE_Z.
3828 */
3829 if (rctx->alphatest_state.sx_alpha_test_control || rctx->ps_shader->info.writes_memory) {
3830 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
3831 } else {
3832 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3833 }
3834
3835 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3836 rctx->db_misc_state.db_shader_control = db_shader_control;
3837 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3838 }
3839 }
3840
evergreen_dma_copy_tile(struct r600_context * rctx,struct pipe_resource * dst,unsigned dst_level,unsigned dst_x,unsigned dst_y,unsigned dst_z,struct pipe_resource * src,unsigned src_level,unsigned src_x,unsigned src_y,unsigned src_z,unsigned copy_height,unsigned pitch,unsigned bpp)3841 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3842 struct pipe_resource *dst,
3843 unsigned dst_level,
3844 unsigned dst_x,
3845 unsigned dst_y,
3846 unsigned dst_z,
3847 struct pipe_resource *src,
3848 unsigned src_level,
3849 unsigned src_x,
3850 unsigned src_y,
3851 unsigned src_z,
3852 unsigned copy_height,
3853 unsigned pitch,
3854 unsigned bpp)
3855 {
3856 struct radeon_cmdbuf *cs = &rctx->b.dma.cs;
3857 struct r600_texture *rsrc = (struct r600_texture*)src;
3858 struct r600_texture *rdst = (struct r600_texture*)dst;
3859 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
3860 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
3861 unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
3862 uint64_t base, addr;
3863
3864 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3865 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3866 assert(dst_mode != src_mode);
3867
3868 /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
3869 if (util_format_has_depth(util_format_description(src->format)))
3870 non_disp_tiling = 1;
3871
3872 y = 0;
3873 sub_cmd = EG_DMA_COPY_TILED;
3874 lbpp = util_logbase2(bpp);
3875 pitch_tile_max = ((pitch / bpp) / 8) - 1;
3876 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3877
3878 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
3879 /* T2L */
3880 array_mode = evergreen_array_mode(src_mode);
3881 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
3882 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3883 /* linear height must be the same as the slice tile max height, it's ok even
3884 * if the linear destination/source have smaller height as the size of the
3885 * dma packet will be using the copy_height which is always smaller or equal
3886 * to the linear height
3887 */
3888 height = u_minify(rsrc->resource.b.b.height0, src_level);
3889 detile = 1;
3890 x = src_x;
3891 y = src_y;
3892 z = src_z;
3893 base = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
3894 addr = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
3895 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3896 addr += dst_y * pitch + dst_x * bpp;
3897 bank_h = eg_bank_wh(rsrc->surface.u.legacy.bankh);
3898 bank_w = eg_bank_wh(rsrc->surface.u.legacy.bankw);
3899 mt_aspect = eg_macro_tile_aspect(rsrc->surface.u.legacy.mtilea);
3900 tile_split = eg_tile_split(rsrc->surface.u.legacy.tile_split);
3901 base += rsrc->resource.gpu_address;
3902 addr += rdst->resource.gpu_address;
3903 } else {
3904 /* L2T */
3905 array_mode = evergreen_array_mode(dst_mode);
3906 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
3907 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3908 /* linear height must be the same as the slice tile max height, it's ok even
3909 * if the linear destination/source have smaller height as the size of the
3910 * dma packet will be using the copy_height which is always smaller or equal
3911 * to the linear height
3912 */
3913 height = u_minify(rdst->resource.b.b.height0, dst_level);
3914 detile = 0;
3915 x = dst_x;
3916 y = dst_y;
3917 z = dst_z;
3918 base = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
3919 addr = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
3920 addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z;
3921 addr += src_y * pitch + src_x * bpp;
3922 bank_h = eg_bank_wh(rdst->surface.u.legacy.bankh);
3923 bank_w = eg_bank_wh(rdst->surface.u.legacy.bankw);
3924 mt_aspect = eg_macro_tile_aspect(rdst->surface.u.legacy.mtilea);
3925 tile_split = eg_tile_split(rdst->surface.u.legacy.tile_split);
3926 base += rdst->resource.gpu_address;
3927 addr += rsrc->resource.gpu_address;
3928 }
3929
3930 size = (copy_height * pitch) / 4;
3931 ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
3932 r600_need_dma_space(&rctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
3933
3934 for (i = 0; i < ncopy; i++) {
3935 cheight = copy_height;
3936 if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
3937 cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
3938 }
3939 size = (cheight * pitch) / 4;
3940 /* emit reloc before writing cs so that cs is always in consistent state */
3941 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3942 RADEON_USAGE_READ);
3943 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3944 RADEON_USAGE_WRITE);
3945 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size));
3946 radeon_emit(cs, base >> 8);
3947 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
3948 (lbpp << 24) | (bank_h << 21) |
3949 (bank_w << 18) | (mt_aspect << 16));
3950 radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16));
3951 radeon_emit(cs, (slice_tile_max << 0));
3952 radeon_emit(cs, (x << 0) | (z << 18));
3953 radeon_emit(cs, (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28));
3954 radeon_emit(cs, addr & 0xfffffffc);
3955 radeon_emit(cs, (addr >> 32UL) & 0xff);
3956 copy_height -= cheight;
3957 addr += cheight * pitch;
3958 y += cheight;
3959 }
3960 }
3961
evergreen_dma_copy(struct pipe_context * ctx,struct pipe_resource * dst,unsigned dst_level,unsigned dstx,unsigned dsty,unsigned dstz,struct pipe_resource * src,unsigned src_level,const struct pipe_box * src_box)3962 static void evergreen_dma_copy(struct pipe_context *ctx,
3963 struct pipe_resource *dst,
3964 unsigned dst_level,
3965 unsigned dstx, unsigned dsty, unsigned dstz,
3966 struct pipe_resource *src,
3967 unsigned src_level,
3968 const struct pipe_box *src_box)
3969 {
3970 struct r600_context *rctx = (struct r600_context *)ctx;
3971 struct r600_texture *rsrc = (struct r600_texture*)src;
3972 struct r600_texture *rdst = (struct r600_texture*)dst;
3973 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
3974 unsigned src_w, dst_w;
3975 unsigned src_x, src_y;
3976 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
3977
3978 if (rctx->b.dma.cs.priv == NULL) {
3979 goto fallback;
3980 }
3981
3982 if (rctx->cmd_buf_is_compute) {
3983 rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
3984 rctx->cmd_buf_is_compute = false;
3985 }
3986
3987 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
3988 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3989 return;
3990 }
3991
3992 if (src_box->depth > 1 ||
3993 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
3994 dstz, rsrc, src_level, src_box))
3995 goto fallback;
3996
3997 src_x = util_format_get_nblocksx(src->format, src_box->x);
3998 dst_x = util_format_get_nblocksx(src->format, dst_x);
3999 src_y = util_format_get_nblocksy(src->format, src_box->y);
4000 dst_y = util_format_get_nblocksy(src->format, dst_y);
4001
4002 bpp = rdst->surface.bpe;
4003 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
4004 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
4005 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
4006 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
4007 copy_height = src_box->height / rsrc->surface.blk_h;
4008
4009 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
4010 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
4011
4012 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
4013 /* FIXME evergreen can do partial blit */
4014 goto fallback;
4015 }
4016 /* the x test here are currently useless (because we don't support partial blit)
4017 * but keep them around so we don't forget about those
4018 */
4019 if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
4020 goto fallback;
4021 }
4022
4023 /* 128 bpp surfaces require non_disp_tiling for both
4024 * tiled and linear buffers on cayman. However, async
4025 * DMA only supports it on the tiled side. As such
4026 * the tile order is backwards after a L2T/T2L packet.
4027 */
4028 if ((rctx->b.gfx_level == CAYMAN) &&
4029 (src_mode != dst_mode) &&
4030 (util_format_get_blocksize(src->format) >= 16)) {
4031 goto fallback;
4032 }
4033
4034 if (src_mode == dst_mode) {
4035 uint64_t dst_offset, src_offset;
4036 /* simple dma blit would do NOTE code here assume :
4037 * src_box.x/y == 0
4038 * dst_x/y == 0
4039 * dst_pitch == src_pitch
4040 */
4041 src_offset= (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
4042 src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;
4043 src_offset += src_y * src_pitch + src_x * bpp;
4044 dst_offset = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
4045 dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
4046 dst_offset += dst_y * dst_pitch + dst_x * bpp;
4047 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
4048 src_box->height * src_pitch);
4049 } else {
4050 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
4051 src, src_level, src_x, src_y, src_box->z,
4052 copy_height, dst_pitch, bpp);
4053 }
4054 return;
4055
4056 fallback:
4057 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
4058 src, src_level, src_box);
4059 }
4060
evergreen_set_tess_state(struct pipe_context * ctx,const float default_outer_level[4],const float default_inner_level[2])4061 static void evergreen_set_tess_state(struct pipe_context *ctx,
4062 const float default_outer_level[4],
4063 const float default_inner_level[2])
4064 {
4065 struct r600_context *rctx = (struct r600_context *)ctx;
4066
4067 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
4068 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
4069 rctx->driver_consts[PIPE_SHADER_TESS_CTRL].tcs_default_levels_dirty = true;
4070 }
4071
evergreen_set_patch_vertices(struct pipe_context * ctx,uint8_t patch_vertices)4072 static void evergreen_set_patch_vertices(struct pipe_context *ctx, uint8_t patch_vertices)
4073 {
4074 struct r600_context *rctx = (struct r600_context *)ctx;
4075
4076 rctx->patch_vertices = patch_vertices;
4077 }
4078
evergreen_setup_immed_buffer(struct r600_context * rctx,struct r600_image_view * rview,enum pipe_format pformat)4079 static void evergreen_setup_immed_buffer(struct r600_context *rctx,
4080 struct r600_image_view *rview,
4081 enum pipe_format pformat)
4082 {
4083 struct r600_screen *rscreen = (struct r600_screen *)rctx->b.b.screen;
4084 uint32_t immed_size = rscreen->b.info.max_se * 256 * 64 * util_format_get_blocksize(pformat);
4085 struct eg_buf_res_params buf_params;
4086 bool skip_reloc = false;
4087 struct r600_resource *resource = (struct r600_resource *)rview->base.resource;
4088 if (!resource->immed_buffer) {
4089 eg_resource_alloc_immed(&rscreen->b, resource, immed_size);
4090 }
4091
4092 memset(&buf_params, 0, sizeof(buf_params));
4093 buf_params.pipe_format = pformat;
4094 buf_params.size = resource->immed_buffer->b.b.width0;
4095 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
4096 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
4097 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
4098 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
4099 buf_params.uncached = 1;
4100 evergreen_fill_buffer_resource_words(rctx, &resource->immed_buffer->b.b,
4101 &buf_params, &skip_reloc,
4102 rview->immed_resource_words);
4103 }
4104
evergreen_set_hw_atomic_buffers(struct pipe_context * ctx,unsigned start_slot,unsigned count,const struct pipe_shader_buffer * buffers)4105 static void evergreen_set_hw_atomic_buffers(struct pipe_context *ctx,
4106 unsigned start_slot,
4107 unsigned count,
4108 const struct pipe_shader_buffer *buffers)
4109 {
4110 struct r600_context *rctx = (struct r600_context *)ctx;
4111 struct r600_atomic_buffer_state *astate;
4112 unsigned i, idx;
4113
4114 astate = &rctx->atomic_buffer_state;
4115
4116 /* we'd probably like to expand this to 8 later so put the logic in */
4117 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
4118 const struct pipe_shader_buffer *buf;
4119 struct pipe_shader_buffer *abuf;
4120
4121 abuf = &astate->buffer[i];
4122
4123 if (!buffers || !buffers[idx].buffer) {
4124 pipe_resource_reference(&abuf->buffer, NULL);
4125 continue;
4126 }
4127 buf = &buffers[idx];
4128
4129 pipe_resource_reference(&abuf->buffer, buf->buffer);
4130 abuf->buffer_offset = buf->buffer_offset;
4131 abuf->buffer_size = buf->buffer_size;
4132 }
4133 }
4134
evergreen_set_shader_buffers(struct pipe_context * ctx,enum pipe_shader_type shader,unsigned start_slot,unsigned count,const struct pipe_shader_buffer * buffers,unsigned writable_bitmask)4135 static void evergreen_set_shader_buffers(struct pipe_context *ctx,
4136 enum pipe_shader_type shader, unsigned start_slot,
4137 unsigned count,
4138 const struct pipe_shader_buffer *buffers,
4139 unsigned writable_bitmask)
4140 {
4141 struct r600_context *rctx = (struct r600_context *)ctx;
4142 struct r600_image_state *istate = NULL;
4143 struct r600_image_view *rview;
4144 struct r600_tex_color_info color;
4145 struct eg_buf_res_params buf_params;
4146 struct r600_resource *resource;
4147 unsigned i, idx;
4148 unsigned old_mask;
4149
4150 if ((shader != PIPE_SHADER_FRAGMENT &&
4151 shader != PIPE_SHADER_COMPUTE) || count == 0)
4152 return;
4153
4154 if (shader == PIPE_SHADER_FRAGMENT)
4155 istate = &rctx->fragment_buffers;
4156 else if (shader == PIPE_SHADER_COMPUTE)
4157 istate = &rctx->compute_buffers;
4158
4159 old_mask = istate->enabled_mask;
4160 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
4161 const struct pipe_shader_buffer *buf;
4162 unsigned res_type;
4163
4164 rview = &istate->views[i];
4165
4166 if (!buffers || !buffers[idx].buffer) {
4167 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL);
4168 istate->enabled_mask &= ~(1 << i);
4169 continue;
4170 }
4171
4172 buf = &buffers[idx];
4173 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, buf->buffer);
4174
4175 resource = (struct r600_resource *)rview->base.resource;
4176
4177 evergreen_setup_immed_buffer(rctx, rview, PIPE_FORMAT_R32_UINT);
4178
4179 color.offset = 0;
4180 color.view = 0;
4181 evergreen_set_color_surface_buffer(rctx, resource,
4182 PIPE_FORMAT_R32_UINT,
4183 buf->buffer_offset,
4184 buf->buffer_offset + buf->buffer_size,
4185 &color);
4186
4187 res_type = V_028C70_BUFFER;
4188
4189 rview->cb_color_base = color.offset;
4190 rview->cb_color_dim = color.dim;
4191 rview->cb_color_info = color.info |
4192 S_028C70_RAT(1) |
4193 S_028C70_RESOURCE_TYPE(res_type);
4194 rview->cb_color_pitch = color.pitch;
4195 rview->cb_color_slice = color.slice;
4196 rview->cb_color_view = color.view;
4197 rview->cb_color_attrib = color.attrib;
4198 rview->cb_color_fmask = color.fmask;
4199 rview->cb_color_fmask_slice = color.fmask_slice;
4200
4201 memset(&buf_params, 0, sizeof(buf_params));
4202 buf_params.pipe_format = PIPE_FORMAT_R32_UINT;
4203 buf_params.offset = buf->buffer_offset;
4204 buf_params.size = buf->buffer_size;
4205 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
4206 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
4207 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
4208 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
4209 buf_params.force_swizzle = true;
4210 buf_params.uncached = 1;
4211 buf_params.size_in_bytes = true;
4212 evergreen_fill_buffer_resource_words(rctx, &resource->b.b,
4213 &buf_params,
4214 &rview->skip_mip_address_reloc,
4215 rview->resource_words);
4216
4217 istate->enabled_mask |= (1 << i);
4218 }
4219
4220 istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46;
4221
4222 if (old_mask != istate->enabled_mask)
4223 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
4224
4225 /* construct the target mask */
4226 if (rctx->cb_misc_state.buffer_rat_enabled_mask != istate->enabled_mask) {
4227 rctx->cb_misc_state.buffer_rat_enabled_mask = istate->enabled_mask;
4228 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
4229 }
4230
4231 if (shader == PIPE_SHADER_FRAGMENT)
4232 r600_mark_atom_dirty(rctx, &istate->atom);
4233 }
4234
evergreen_set_shader_images(struct pipe_context * ctx,enum pipe_shader_type shader,unsigned start_slot,unsigned count,unsigned unbind_num_trailing_slots,const struct pipe_image_view * images)4235 static void evergreen_set_shader_images(struct pipe_context *ctx,
4236 enum pipe_shader_type shader, unsigned start_slot,
4237 unsigned count, unsigned unbind_num_trailing_slots,
4238 const struct pipe_image_view *images)
4239 {
4240 struct r600_context *rctx = (struct r600_context *)ctx;
4241 unsigned i;
4242 struct r600_image_view *rview;
4243 struct pipe_resource *image;
4244 struct r600_resource *resource;
4245 struct r600_tex_color_info color;
4246 struct eg_buf_res_params buf_params;
4247 struct eg_tex_res_params tex_params;
4248 unsigned old_mask;
4249 struct r600_image_state *istate = NULL;
4250 int idx;
4251 if (shader != PIPE_SHADER_FRAGMENT && shader != PIPE_SHADER_COMPUTE)
4252 return;
4253 if (!count && !unbind_num_trailing_slots)
4254 return;
4255
4256 if (shader == PIPE_SHADER_FRAGMENT)
4257 istate = &rctx->fragment_images;
4258 else if (shader == PIPE_SHADER_COMPUTE)
4259 istate = &rctx->compute_images;
4260
4261 assert (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE);
4262
4263 old_mask = istate->enabled_mask;
4264 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
4265 unsigned res_type;
4266 const struct pipe_image_view *iview;
4267 rview = &istate->views[i];
4268
4269 if (!images || !images[idx].resource) {
4270 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL);
4271 istate->enabled_mask &= ~(1 << i);
4272 istate->compressed_colortex_mask &= ~(1 << i);
4273 istate->compressed_depthtex_mask &= ~(1 << i);
4274 continue;
4275 }
4276
4277 iview = &images[idx];
4278 image = iview->resource;
4279 resource = (struct r600_resource *)image;
4280
4281 r600_context_add_resource_size(ctx, image);
4282
4283 struct pipe_resource *const pipe_saved = rview->base.resource;
4284 rview->base = *iview;
4285 rview->base.resource = pipe_saved;
4286 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, image);
4287
4288 evergreen_setup_immed_buffer(rctx, rview, iview->format);
4289
4290 bool is_buffer = image->target == PIPE_BUFFER;
4291 struct r600_texture *rtex = (struct r600_texture *)image;
4292 if (!is_buffer && rtex->db_compatible)
4293 istate->compressed_depthtex_mask |= 1 << i;
4294 else
4295 istate->compressed_depthtex_mask &= ~(1 << i);
4296
4297 if (!is_buffer && rtex->cmask.size)
4298 istate->compressed_colortex_mask |= 1 << i;
4299 else
4300 istate->compressed_colortex_mask &= ~(1 << i);
4301 if (!is_buffer) {
4302
4303 evergreen_set_color_surface_common(rctx, rtex,
4304 iview->u.tex.level,
4305 iview->u.tex.first_layer,
4306 iview->u.tex.last_layer,
4307 iview->format,
4308 &color);
4309 color.dim = S_028C78_WIDTH_MAX(u_minify(image->width0, iview->u.tex.level) - 1) |
4310 S_028C78_HEIGHT_MAX(u_minify(image->height0, iview->u.tex.level) - 1);
4311 } else {
4312 color.offset = 0;
4313 color.view = 0;
4314 evergreen_set_color_surface_buffer(rctx, resource,
4315 iview->format,
4316 iview->u.buf.offset,
4317 iview->u.buf.size,
4318 &color);
4319 }
4320
4321 switch (image->target) {
4322 case PIPE_BUFFER:
4323 res_type = V_028C70_BUFFER;
4324 break;
4325 case PIPE_TEXTURE_1D:
4326 res_type = V_028C70_TEXTURE1D;
4327 break;
4328 case PIPE_TEXTURE_1D_ARRAY:
4329 res_type = V_028C70_TEXTURE1DARRAY;
4330 break;
4331 case PIPE_TEXTURE_2D:
4332 case PIPE_TEXTURE_RECT:
4333 res_type = V_028C70_TEXTURE2D;
4334 break;
4335 case PIPE_TEXTURE_3D:
4336 res_type = V_028C70_TEXTURE3D;
4337 break;
4338 case PIPE_TEXTURE_2D_ARRAY:
4339 case PIPE_TEXTURE_CUBE:
4340 case PIPE_TEXTURE_CUBE_ARRAY:
4341 res_type = V_028C70_TEXTURE2DARRAY;
4342 break;
4343 default:
4344 assert(0);
4345 res_type = 0;
4346 break;
4347 }
4348
4349 rview->cb_color_base = color.offset;
4350 rview->cb_color_dim = color.dim;
4351 rview->cb_color_info = color.info |
4352 S_028C70_RAT(1) |
4353 S_028C70_RESOURCE_TYPE(res_type);
4354 rview->cb_color_pitch = color.pitch;
4355 rview->cb_color_slice = color.slice;
4356 rview->cb_color_view = color.view;
4357 rview->cb_color_attrib = color.attrib;
4358 rview->cb_color_fmask = color.fmask;
4359 rview->cb_color_fmask_slice = color.fmask_slice;
4360
4361 if (image->target != PIPE_BUFFER) {
4362 memset(&tex_params, 0, sizeof(tex_params));
4363 tex_params.pipe_format = iview->format;
4364 tex_params.force_level = 0;
4365 tex_params.width0 = image->width0;
4366 tex_params.height0 = image->height0;
4367 tex_params.first_level = iview->u.tex.level;
4368 tex_params.last_level = iview->u.tex.level;
4369 tex_params.first_layer = iview->u.tex.first_layer;
4370 tex_params.last_layer = iview->u.tex.last_layer;
4371 tex_params.target = image->target;
4372 tex_params.swizzle[0] = PIPE_SWIZZLE_X;
4373 tex_params.swizzle[1] = PIPE_SWIZZLE_Y;
4374 tex_params.swizzle[2] = PIPE_SWIZZLE_Z;
4375 tex_params.swizzle[3] = PIPE_SWIZZLE_W;
4376 evergreen_fill_tex_resource_words(rctx, &resource->b.b, &tex_params,
4377 &rview->skip_mip_address_reloc,
4378 rview->resource_words);
4379
4380 } else {
4381 memset(&buf_params, 0, sizeof(buf_params));
4382 buf_params.pipe_format = iview->format;
4383 buf_params.size = iview->u.buf.size;
4384 buf_params.offset = iview->u.buf.offset;
4385 buf_params.swizzle[0] = PIPE_SWIZZLE_X;
4386 buf_params.swizzle[1] = PIPE_SWIZZLE_Y;
4387 buf_params.swizzle[2] = PIPE_SWIZZLE_Z;
4388 buf_params.swizzle[3] = PIPE_SWIZZLE_W;
4389 evergreen_fill_buffer_resource_words(rctx, &resource->b.b,
4390 &buf_params,
4391 &rview->skip_mip_address_reloc,
4392 rview->resource_words);
4393 }
4394 istate->enabled_mask |= (1 << i);
4395 }
4396
4397 for (i = start_slot + count, idx = 0;
4398 i < start_slot + count + unbind_num_trailing_slots; i++, idx++) {
4399 rview = &istate->views[i];
4400
4401 pipe_resource_reference((struct pipe_resource **)&rview->base.resource, NULL);
4402 istate->enabled_mask &= ~(1 << i);
4403 istate->compressed_colortex_mask &= ~(1 << i);
4404 istate->compressed_depthtex_mask &= ~(1 << i);
4405 }
4406
4407 istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46;
4408 istate->dirty_buffer_constants = true;
4409 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
4410 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
4411 R600_CONTEXT_FLUSH_AND_INV_CB_META;
4412
4413 if (old_mask != istate->enabled_mask)
4414 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
4415
4416 if (rctx->cb_misc_state.image_rat_enabled_mask != istate->enabled_mask) {
4417 rctx->cb_misc_state.image_rat_enabled_mask = istate->enabled_mask;
4418 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
4419 }
4420
4421 if (shader == PIPE_SHADER_FRAGMENT)
4422 r600_mark_atom_dirty(rctx, &istate->atom);
4423 }
4424
evergreen_get_pipe_constant_buffer(struct r600_context * rctx,enum pipe_shader_type shader,uint slot,struct pipe_constant_buffer * cbuf)4425 static void evergreen_get_pipe_constant_buffer(struct r600_context *rctx,
4426 enum pipe_shader_type shader, uint slot,
4427 struct pipe_constant_buffer *cbuf)
4428 {
4429 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
4430 struct pipe_constant_buffer *cb;
4431 cbuf->user_buffer = NULL;
4432
4433 cb = &state->cb[slot];
4434
4435 cbuf->buffer_size = cb->buffer_size;
4436 pipe_resource_reference(&cbuf->buffer, cb->buffer);
4437 }
4438
evergreen_get_shader_buffers(struct r600_context * rctx,enum pipe_shader_type shader,uint start_slot,uint count,struct pipe_shader_buffer * sbuf)4439 static void evergreen_get_shader_buffers(struct r600_context *rctx,
4440 enum pipe_shader_type shader,
4441 uint start_slot, uint count,
4442 struct pipe_shader_buffer *sbuf)
4443 {
4444 assert(shader == PIPE_SHADER_COMPUTE);
4445 int idx, i;
4446 struct r600_image_state *istate = &rctx->compute_buffers;
4447 struct r600_image_view *rview;
4448
4449 for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
4450
4451 rview = &istate->views[i];
4452
4453 pipe_resource_reference(&sbuf[idx].buffer, rview->base.resource);
4454 if (rview->base.resource) {
4455 uint64_t rview_va = ((struct r600_resource *)rview->base.resource)->gpu_address;
4456
4457 uint64_t prog_va = rview->resource_words[0];
4458
4459 prog_va += ((uint64_t)G_030008_BASE_ADDRESS_HI(rview->resource_words[2])) << 32;
4460 prog_va -= rview_va;
4461
4462 sbuf[idx].buffer_offset = prog_va & 0xffffffff;
4463 sbuf[idx].buffer_size = rview->resource_words[1] + 1;;
4464 } else {
4465 sbuf[idx].buffer_offset = 0;
4466 sbuf[idx].buffer_size = 0;
4467 }
4468 }
4469 }
4470
evergreen_save_qbo_state(struct pipe_context * ctx,struct r600_qbo_state * st)4471 static void evergreen_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
4472 {
4473 struct r600_context *rctx = (struct r600_context *)ctx;
4474 st->saved_compute = rctx->cs_shader_state.shader;
4475
4476 /* save constant buffer 0 */
4477 evergreen_get_pipe_constant_buffer(rctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
4478 /* save ssbo 0 */
4479 evergreen_get_shader_buffers(rctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
4480 }
4481
4482
evergreen_init_state_functions(struct r600_context * rctx)4483 void evergreen_init_state_functions(struct r600_context *rctx)
4484 {
4485 unsigned id = 1;
4486 unsigned i;
4487 /* !!!
4488 * To avoid GPU lockup registers must be emitted in a specific order
4489 * (no kidding ...). The order below is important and have been
4490 * partially inferred from analyzing fglrx command stream.
4491 *
4492 * Don't reorder atom without carefully checking the effect (GPU lockup
4493 * or piglit regression).
4494 * !!!
4495 */
4496 if (rctx->b.gfx_level == EVERGREEN) {
4497 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
4498 rctx->config_state.dyn_gpr_enabled = true;
4499 }
4500 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
4501 r600_init_atom(rctx, &rctx->fragment_images.atom, id++, evergreen_emit_fragment_image_state, 0);
4502 r600_init_atom(rctx, &rctx->compute_images.atom, id++, evergreen_emit_compute_image_state, 0);
4503 r600_init_atom(rctx, &rctx->fragment_buffers.atom, id++, evergreen_emit_fragment_buffer_state, 0);
4504 r600_init_atom(rctx, &rctx->compute_buffers.atom, id++, evergreen_emit_compute_buffer_state, 0);
4505 /* shader const */
4506 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
4507 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
4508 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
4509 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
4510 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
4511 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
4512 /* shader program */
4513 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
4514 /* sampler */
4515 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
4516 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
4517 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
4518 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
4519 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
4520 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
4521 /* resources */
4522 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
4523 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
4524 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
4525 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
4526 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
4527 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
4528 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
4529 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
4530
4531 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
4532
4533 if (rctx->b.gfx_level == EVERGREEN) {
4534 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
4535 } else {
4536 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
4537 }
4538 rctx->sample_mask.sample_mask = ~0;
4539
4540 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
4541 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
4542 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
4543 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
4544 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
4545 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
4546 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
4547 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
4548 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
4549 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 9);
4550 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
4551 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
4552 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
4553 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
4554 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
4555 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
4556 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
4557 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
4558 for (i = 0; i < EG_NUM_HW_STAGES; i++)
4559 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
4560 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
4561 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
4562
4563 rctx->b.b.create_blend_state = evergreen_create_blend_state;
4564 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
4565 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
4566 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
4567 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
4568 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
4569 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
4570 rctx->b.b.set_min_samples = evergreen_set_min_samples;
4571 rctx->b.b.set_tess_state = evergreen_set_tess_state;
4572 rctx->b.b.set_patch_vertices = evergreen_set_patch_vertices;
4573 rctx->b.b.set_hw_atomic_buffers = evergreen_set_hw_atomic_buffers;
4574 rctx->b.b.set_shader_images = evergreen_set_shader_images;
4575 rctx->b.b.set_shader_buffers = evergreen_set_shader_buffers;
4576 if (rctx->b.gfx_level == EVERGREEN)
4577 rctx->b.b.get_sample_position = evergreen_get_sample_position;
4578 else
4579 rctx->b.b.get_sample_position = cayman_get_sample_position;
4580 rctx->b.dma_copy = evergreen_dma_copy;
4581 rctx->b.save_qbo_state = evergreen_save_qbo_state;
4582
4583 evergreen_init_compute_state_functions(rctx);
4584 }
4585
4586 /**
4587 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
4588 *
4589 * The information about LDS and other non-compile-time parameters is then
4590 * written to the const buffer.
4591
4592 * const buffer contains -
4593 * uint32_t input_patch_size
4594 * uint32_t input_vertex_size
4595 * uint32_t num_tcs_input_cp
4596 * uint32_t num_tcs_output_cp;
4597 * uint32_t output_patch_size
4598 * uint32_t output_vertex_size
4599 * uint32_t output_patch0_offset
4600 * uint32_t perpatch_output_offset
4601 * and the same constbuf is bound to LS/HS/VS(ES).
4602 */
evergreen_setup_tess_constants(struct r600_context * rctx,const struct pipe_draw_info * info,unsigned * num_patches)4603 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
4604 {
4605 struct pipe_constant_buffer constbuf = {0};
4606 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
4607 struct r600_pipe_shader_selector *ls = rctx->vs_shader;
4608 unsigned num_tcs_input_cp = rctx->patch_vertices;
4609 unsigned num_tcs_outputs;
4610 unsigned num_tcs_output_cp;
4611 unsigned num_tcs_patch_outputs;
4612 unsigned num_tcs_inputs;
4613 unsigned input_vertex_size, output_vertex_size;
4614 unsigned input_patch_size, pervertex_output_patch_size, output_patch_size;
4615 unsigned output_patch0_offset, perpatch_output_offset, lds_size;
4616 uint32_t values[8];
4617 unsigned num_waves;
4618 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
4619 unsigned wave_divisor = (16 * num_pipes);
4620
4621 *num_patches = 1;
4622
4623 if (!rctx->tes_shader) {
4624 rctx->lds_alloc = 0;
4625 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
4626 R600_LDS_INFO_CONST_BUFFER, false, NULL);
4627 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
4628 R600_LDS_INFO_CONST_BUFFER, false, NULL);
4629 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
4630 R600_LDS_INFO_CONST_BUFFER, false, NULL);
4631 return;
4632 }
4633
4634 if (rctx->lds_alloc != 0 &&
4635 rctx->last_ls == ls &&
4636 rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
4637 rctx->last_tcs == tcs)
4638 return;
4639
4640 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask);
4641
4642 if (rctx->tcs_shader) {
4643 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask);
4644 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
4645 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask);
4646 } else {
4647 num_tcs_outputs = num_tcs_inputs;
4648 num_tcs_output_cp = num_tcs_input_cp;
4649 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
4650 }
4651
4652 /* size in bytes */
4653 input_vertex_size = num_tcs_inputs * 16;
4654 output_vertex_size = num_tcs_outputs * 16;
4655
4656 input_patch_size = num_tcs_input_cp * input_vertex_size;
4657
4658 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
4659 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
4660
4661 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
4662 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
4663
4664 lds_size = output_patch0_offset + output_patch_size * *num_patches;
4665
4666 values[0] = input_patch_size;
4667 values[1] = input_vertex_size;
4668 values[2] = num_tcs_input_cp;
4669 values[3] = num_tcs_output_cp;
4670
4671 values[4] = output_patch_size;
4672 values[5] = output_vertex_size;
4673 values[6] = output_patch0_offset;
4674 values[7] = perpatch_output_offset;
4675
4676 /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES *
4677 LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */
4678 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor);
4679
4680 rctx->lds_alloc = (lds_size | (num_waves << 14));
4681
4682 rctx->last_ls = ls;
4683 rctx->last_tcs = tcs;
4684 rctx->last_num_tcs_input_cp = num_tcs_input_cp;
4685
4686 constbuf.user_buffer = values;
4687 constbuf.buffer_size = 8 * 4;
4688
4689 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
4690 R600_LDS_INFO_CONST_BUFFER, false, &constbuf);
4691 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
4692 R600_LDS_INFO_CONST_BUFFER, false, &constbuf);
4693 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
4694 R600_LDS_INFO_CONST_BUFFER, true, &constbuf);
4695 }
4696
evergreen_get_ls_hs_config(struct r600_context * rctx,const struct pipe_draw_info * info,unsigned num_patches)4697 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
4698 const struct pipe_draw_info *info,
4699 unsigned num_patches)
4700 {
4701 unsigned num_output_cp;
4702
4703 if (!rctx->tes_shader)
4704 return 0;
4705
4706 num_output_cp = rctx->tcs_shader ?
4707 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
4708 rctx->patch_vertices;
4709
4710 return S_028B58_NUM_PATCHES(num_patches) |
4711 S_028B58_HS_NUM_INPUT_CP(rctx->patch_vertices) |
4712 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
4713 }
4714
evergreen_set_ls_hs_config(struct r600_context * rctx,struct radeon_cmdbuf * cs,uint32_t ls_hs_config)4715 void evergreen_set_ls_hs_config(struct r600_context *rctx,
4716 struct radeon_cmdbuf *cs,
4717 uint32_t ls_hs_config)
4718 {
4719 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
4720 }
4721
evergreen_set_lds_alloc(struct r600_context * rctx,struct radeon_cmdbuf * cs,uint32_t lds_alloc)4722 void evergreen_set_lds_alloc(struct r600_context *rctx,
4723 struct radeon_cmdbuf *cs,
4724 uint32_t lds_alloc)
4725 {
4726 radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc);
4727 }
4728
4729 /* on evergreen if you are running tessellation you need to disable dynamic
4730 GPRs to workaround a hardware bug.*/
evergreen_adjust_gprs(struct r600_context * rctx)4731 bool evergreen_adjust_gprs(struct r600_context *rctx)
4732 {
4733 unsigned num_gprs[EG_NUM_HW_STAGES];
4734 unsigned def_gprs[EG_NUM_HW_STAGES];
4735 unsigned cur_gprs[EG_NUM_HW_STAGES];
4736 unsigned new_gprs[EG_NUM_HW_STAGES];
4737 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
4738 unsigned max_gprs;
4739 unsigned i;
4740 unsigned total_gprs;
4741 unsigned tmp[3];
4742 bool rework = false, set_default = false, set_dirty = false;
4743 max_gprs = 0;
4744 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4745 def_gprs[i] = rctx->default_gprs[i];
4746 max_gprs += def_gprs[i];
4747 }
4748 max_gprs += def_num_clause_temp_gprs * 2;
4749
4750 /* if we have no TESS and dyn gpr is enabled then do nothing. */
4751 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
4752 if (rctx->config_state.dyn_gpr_enabled)
4753 return true;
4754
4755 /* transition back to dyn gpr enabled state */
4756 rctx->config_state.dyn_gpr_enabled = true;
4757 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4758 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4759 return true;
4760 }
4761
4762
4763 /* gather required shader gprs */
4764 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4765 if (rctx->hw_shader_stages[i].shader)
4766 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
4767 else
4768 num_gprs[i] = 0;
4769 }
4770
4771 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4772 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4773 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4774 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4775 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4776 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4777
4778 total_gprs = 0;
4779 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4780 new_gprs[i] = num_gprs[i];
4781 total_gprs += num_gprs[i];
4782 }
4783
4784 if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs)))
4785 return false;
4786
4787 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4788 if (new_gprs[i] > cur_gprs[i]) {
4789 rework = true;
4790 break;
4791 }
4792 }
4793
4794 if (rctx->config_state.dyn_gpr_enabled) {
4795 set_dirty = true;
4796 rctx->config_state.dyn_gpr_enabled = false;
4797 }
4798
4799 if (rework) {
4800 set_default = true;
4801 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4802 if (new_gprs[i] > def_gprs[i])
4803 set_default = false;
4804 }
4805
4806 if (set_default) {
4807 for (i = 0; i < EG_NUM_HW_STAGES; i++) {
4808 new_gprs[i] = def_gprs[i];
4809 }
4810 } else {
4811 unsigned ps_value = max_gprs;
4812
4813 ps_value -= (def_num_clause_temp_gprs * 2);
4814 for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++)
4815 ps_value -= new_gprs[i];
4816
4817 new_gprs[R600_HW_STAGE_PS] = ps_value;
4818 }
4819
4820 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
4821 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
4822 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
4823
4824 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
4825 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
4826
4827 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
4828 S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]);
4829
4830 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
4831 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
4832 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
4833 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
4834 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
4835 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
4836 set_dirty = true;
4837 }
4838 }
4839
4840
4841 if (set_dirty) {
4842 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4843 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4844 }
4845 return true;
4846 }
4847
4848 #define AC_ENCODE_TRACE_POINT(id) (0xcafe0000 | ((id) & 0xffff))
4849
eg_trace_emit(struct r600_context * rctx)4850 void eg_trace_emit(struct r600_context *rctx)
4851 {
4852 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
4853 unsigned reloc;
4854
4855 if (rctx->b.gfx_level < EVERGREEN)
4856 return;
4857
4858 /* This must be done after r600_need_cs_space. */
4859 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4860 (struct r600_resource*)rctx->trace_buf, RADEON_USAGE_WRITE |
4861 RADEON_PRIO_CP_DMA);
4862
4863 rctx->trace_id++;
4864 radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rctx->trace_buf,
4865 RADEON_USAGE_READWRITE | RADEON_PRIO_FENCE_TRACE);
4866 radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
4867 radeon_emit(cs, rctx->trace_buf->gpu_address);
4868 radeon_emit(cs, rctx->trace_buf->gpu_address >> 32 | MEM_WRITE_32_BITS | MEM_WRITE_CONFIRM);
4869 radeon_emit(cs, rctx->trace_id);
4870 radeon_emit(cs, 0);
4871 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4872 radeon_emit(cs, reloc);
4873 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4874 radeon_emit(cs, AC_ENCODE_TRACE_POINT(rctx->trace_id));
4875 }
4876
evergreen_emit_set_append_cnt(struct r600_context * rctx,struct r600_shader_atomic * atomic,struct r600_resource * resource,uint32_t pkt_flags)4877 static void evergreen_emit_set_append_cnt(struct r600_context *rctx,
4878 struct r600_shader_atomic *atomic,
4879 struct r600_resource *resource,
4880 uint32_t pkt_flags)
4881 {
4882 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
4883 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4884 resource,
4885 RADEON_USAGE_READ |
4886 RADEON_PRIO_SHADER_RW_BUFFER);
4887 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4888 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
4889
4890 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4 - EVERGREEN_CONTEXT_REG_OFFSET) >> 2;
4891
4892 radeon_emit(cs, PKT3(PKT3_SET_APPEND_CNT, 2, 0) | pkt_flags);
4893 radeon_emit(cs, (reg_val << 16) | 0x3);
4894 radeon_emit(cs, dst_offset & 0xfffffffc);
4895 radeon_emit(cs, (dst_offset >> 32) & 0xff);
4896 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4897 radeon_emit(cs, reloc);
4898 }
4899
evergreen_emit_event_write_eos(struct r600_context * rctx,struct r600_shader_atomic * atomic,struct r600_resource * resource,uint32_t pkt_flags)4900 static void evergreen_emit_event_write_eos(struct r600_context *rctx,
4901 struct r600_shader_atomic *atomic,
4902 struct r600_resource *resource,
4903 uint32_t pkt_flags)
4904 {
4905 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
4906 uint32_t event = EVENT_TYPE_PS_DONE;
4907 uint32_t base_reg_0 = R_02872C_GDS_APPEND_COUNT_0;
4908 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4909 resource,
4910 RADEON_USAGE_WRITE |
4911 RADEON_PRIO_SHADER_RW_BUFFER);
4912 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4913 uint32_t reg_val = (base_reg_0 + atomic->hw_idx * 4) >> 2;
4914
4915 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4916 event = EVENT_TYPE_CS_DONE;
4917
4918 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4919 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4920 radeon_emit(cs, (dst_offset) & 0xffffffff);
4921 radeon_emit(cs, (0 << 29) | ((dst_offset >> 32) & 0xff));
4922 radeon_emit(cs, reg_val);
4923 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4924 radeon_emit(cs, reloc);
4925 }
4926
cayman_emit_event_write_eos(struct r600_context * rctx,struct r600_shader_atomic * atomic,struct r600_resource * resource,uint32_t pkt_flags)4927 static void cayman_emit_event_write_eos(struct r600_context *rctx,
4928 struct r600_shader_atomic *atomic,
4929 struct r600_resource *resource,
4930 uint32_t pkt_flags)
4931 {
4932 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
4933 uint32_t event = EVENT_TYPE_PS_DONE;
4934 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4935 resource,
4936 RADEON_USAGE_WRITE |
4937 RADEON_PRIO_SHADER_RW_BUFFER);
4938 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4939
4940 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
4941 event = EVENT_TYPE_CS_DONE;
4942
4943 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
4944 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
4945 radeon_emit(cs, (dst_offset) & 0xffffffff);
4946 radeon_emit(cs, (1 << 29) | ((dst_offset >> 32) & 0xff));
4947 radeon_emit(cs, (atomic->hw_idx) | (1 << 16));
4948 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4949 radeon_emit(cs, reloc);
4950 }
4951
4952 /* writes count from a buffer into GDS */
cayman_write_count_to_gds(struct r600_context * rctx,struct r600_shader_atomic * atomic,struct r600_resource * resource,uint32_t pkt_flags)4953 static void cayman_write_count_to_gds(struct r600_context *rctx,
4954 struct r600_shader_atomic *atomic,
4955 struct r600_resource *resource,
4956 uint32_t pkt_flags)
4957 {
4958 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
4959 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4960 resource,
4961 RADEON_USAGE_READ |
4962 RADEON_PRIO_SHADER_RW_BUFFER);
4963 uint64_t dst_offset = resource->gpu_address + (atomic->start * 4);
4964
4965 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0) | pkt_flags);
4966 radeon_emit(cs, dst_offset & 0xffffffff);
4967 radeon_emit(cs, PKT3_CP_DMA_CP_SYNC | PKT3_CP_DMA_DST_SEL(1) | ((dst_offset >> 32) & 0xff));// GDS
4968 radeon_emit(cs, atomic->hw_idx * 4);
4969 radeon_emit(cs, 0);
4970 radeon_emit(cs, PKT3_CP_DMA_CMD_DAS | 4);
4971 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
4972 radeon_emit(cs, reloc);
4973 }
4974
evergreen_emit_atomic_buffer_setup_count(struct r600_context * rctx,struct r600_pipe_shader * cs_shader,struct r600_shader_atomic * combined_atomics,uint8_t * atomic_used_mask_p)4975 void evergreen_emit_atomic_buffer_setup_count(struct r600_context *rctx,
4976 struct r600_pipe_shader *cs_shader,
4977 struct r600_shader_atomic *combined_atomics,
4978 uint8_t *atomic_used_mask_p)
4979 {
4980 uint8_t atomic_used_mask = 0;
4981 int i, j, k;
4982 bool is_compute = cs_shader ? true : false;
4983
4984 for (i = 0; i < (is_compute ? 1 : EG_NUM_HW_STAGES); i++) {
4985 uint8_t num_atomic_stage;
4986 struct r600_pipe_shader *pshader;
4987
4988 if (is_compute)
4989 pshader = cs_shader;
4990 else
4991 pshader = rctx->hw_shader_stages[i].shader;
4992 if (!pshader)
4993 continue;
4994
4995 num_atomic_stage = pshader->shader.nhwatomic_ranges;
4996 if (!num_atomic_stage)
4997 continue;
4998
4999 for (j = 0; j < num_atomic_stage; j++) {
5000 struct r600_shader_atomic *atomic = &pshader->shader.atomics[j];
5001 int natomics = atomic->end - atomic->start + 1;
5002
5003 for (k = 0; k < natomics; k++) {
5004 /* seen this in a previous stage */
5005 if (atomic_used_mask & (1u << (atomic->hw_idx + k)))
5006 continue;
5007
5008 combined_atomics[atomic->hw_idx + k].hw_idx = atomic->hw_idx + k;
5009 combined_atomics[atomic->hw_idx + k].buffer_id = atomic->buffer_id;
5010 combined_atomics[atomic->hw_idx + k].start = atomic->start + k;
5011 combined_atomics[atomic->hw_idx + k].end = combined_atomics[atomic->hw_idx + k].start + 1;
5012 atomic_used_mask |= (1u << (atomic->hw_idx + k));
5013 }
5014 }
5015 }
5016 *atomic_used_mask_p = atomic_used_mask;
5017 }
5018
evergreen_emit_atomic_buffer_setup(struct r600_context * rctx,bool is_compute,struct r600_shader_atomic * combined_atomics,uint8_t atomic_used_mask)5019 void evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
5020 bool is_compute,
5021 struct r600_shader_atomic *combined_atomics,
5022 uint8_t atomic_used_mask)
5023 {
5024 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
5025 unsigned pkt_flags = 0;
5026 uint32_t mask;
5027
5028 if (is_compute)
5029 pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
5030
5031 mask = atomic_used_mask;
5032 if (!mask)
5033 return;
5034
5035 while (mask) {
5036 unsigned atomic_index = u_bit_scan(&mask);
5037 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index];
5038 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer);
5039 assert(resource);
5040
5041 if (rctx->b.gfx_level == CAYMAN)
5042 cayman_write_count_to_gds(rctx, atomic, resource, pkt_flags);
5043 else
5044 evergreen_emit_set_append_cnt(rctx, atomic, resource, pkt_flags);
5045 }
5046 }
5047
evergreen_emit_atomic_buffer_save(struct r600_context * rctx,bool is_compute,struct r600_shader_atomic * combined_atomics,uint8_t * atomic_used_mask_p)5048 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
5049 bool is_compute,
5050 struct r600_shader_atomic *combined_atomics,
5051 uint8_t *atomic_used_mask_p)
5052 {
5053 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
5054 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
5055 uint32_t pkt_flags = 0;
5056 uint32_t event = EVENT_TYPE_PS_DONE;
5057 uint32_t mask;
5058 uint64_t dst_offset;
5059 unsigned reloc;
5060
5061 if (is_compute)
5062 pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
5063
5064 mask = *atomic_used_mask_p;
5065 if (!mask)
5066 return;
5067
5068 while (mask) {
5069 unsigned atomic_index = u_bit_scan(&mask);
5070 struct r600_shader_atomic *atomic = &combined_atomics[atomic_index];
5071 struct r600_resource *resource = r600_resource(astate->buffer[atomic->buffer_id].buffer);
5072 assert(resource);
5073
5074 if (rctx->b.gfx_level == CAYMAN)
5075 cayman_emit_event_write_eos(rctx, atomic, resource, pkt_flags);
5076 else
5077 evergreen_emit_event_write_eos(rctx, atomic, resource, pkt_flags);
5078 }
5079
5080 if (pkt_flags == RADEON_CP_PACKET3_COMPUTE_MODE)
5081 event = EVENT_TYPE_CS_DONE;
5082
5083 ++rctx->append_fence_id;
5084 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
5085 r600_resource(rctx->append_fence),
5086 RADEON_USAGE_READWRITE |
5087 RADEON_PRIO_SHADER_RW_BUFFER);
5088 dst_offset = r600_resource(rctx->append_fence)->gpu_address;
5089 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0) | pkt_flags);
5090 radeon_emit(cs, EVENT_TYPE(event) | EVENT_INDEX(6));
5091 radeon_emit(cs, dst_offset & 0xffffffff);
5092 radeon_emit(cs, (2 << 29) | ((dst_offset >> 32) & 0xff));
5093 radeon_emit(cs, rctx->append_fence_id);
5094 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
5095 radeon_emit(cs, reloc);
5096
5097 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0) | pkt_flags);
5098 radeon_emit(cs, WAIT_REG_MEM_GEQUAL | WAIT_REG_MEM_MEMORY | (1 << 8));
5099 radeon_emit(cs, dst_offset & 0xffffffff);
5100 radeon_emit(cs, ((dst_offset >> 32) & 0xff));
5101 radeon_emit(cs, rctx->append_fence_id);
5102 radeon_emit(cs, 0xffffffff);
5103 radeon_emit(cs, 0xa);
5104 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
5105 radeon_emit(cs, reloc);
5106 }
5107