1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 /* Register map for Exynos5 FIMD */ 4 5 #ifndef CPU_SAMSUNG_EXYNOS5250_FIMD_H 6 #define CPU_SAMSUNG_EXYNOS5250_FIMD_H 7 8 #include <soc/cpu.h> 9 10 /* FIMD register map */ 11 struct exynos5_fimd { 12 /* This is an incomplete list. Add registers as and when required */ 13 unsigned int vidcon0; 14 unsigned char res1[0x1c]; 15 unsigned int wincon0; 16 unsigned int wincon1; 17 unsigned int wincon2; 18 unsigned int wincon3; 19 unsigned int wincon4; 20 unsigned int shadowcon; 21 unsigned char res2[0x8]; 22 unsigned int vidosd0a; 23 unsigned int vidosd0b; 24 unsigned int vidosd0c; 25 unsigned char res3[0x54]; 26 unsigned int vidw00add0b0; 27 unsigned char res4[0x2c]; 28 unsigned int vidw00add1b0; 29 unsigned char res5[0x2c]; 30 unsigned int vidw00add2; 31 unsigned char res6[0x3c]; 32 unsigned int w1keycon0; 33 unsigned int w1keycon1; 34 unsigned int w2keycon0; 35 unsigned int w2keycon1; 36 unsigned int w3keycon0; 37 unsigned int w3keycon1; 38 unsigned int w4keycon0; 39 unsigned int w4keycon1; 40 unsigned char res7[0x20]; 41 unsigned int win0map; 42 unsigned char res8[0xdc]; 43 unsigned int blendcon; 44 unsigned char res9[0x18]; 45 unsigned int dpclkcon; 46 }; 47 check_member(exynos5_fimd, dpclkcon, 0x27c); 48 49 static struct exynos5_fimd * const exynos_fimd = (void *)EXYNOS5_FIMD_BASE; 50 51 #define W0_SHADOW_PROTECT (0x1 << 10) 52 #define COMPKEY_F 0xffffff 53 #define ENVID_F_ON (0x1 << 0) 54 #define ENVID_ON (0x1 << 1) 55 #define CLKVAL_F 0xb 56 #define CLKVAL_F_OFFSET 6 57 58 /* 59 * Structure containing display panel specific data for FIMD 60 */ 61 struct exynos5_fimd_panel { 62 unsigned int is_dp:1; /* Display Panel interface is eDP */ 63 unsigned int is_mipi:1; /* Display Panel interface is MIPI */ 64 unsigned int fixvclk:2; /* VCLK hold scheme at data underflow */ 65 66 /* 67 * Polarity of the VCLK active edge 68 * 0-falling 69 * 1-rising 70 */ 71 unsigned int ivclk:1; 72 unsigned int clkval_f; /* Divider to create pixel clock */ 73 74 unsigned int upper_margin; /* Vertical Backporch */ 75 unsigned int lower_margin; /* Vertical frontporch */ 76 unsigned int vsync; /* Vertical Sync Pulse Width */ 77 unsigned int left_margin; /* Horizontal Backporch */ 78 unsigned int right_margin; /* Horizontal Frontporch */ 79 unsigned int hsync; /* Horizontal Sync Pulse Width */ 80 unsigned int xres; /* X Resolution */ 81 unsigned int yres; /* Y Resolution */ 82 }; 83 84 /* LCDIF Register Map */ 85 struct exynos5_disp_ctrl { 86 unsigned int vidout_con; 87 unsigned int vidcon1; 88 unsigned char res1[0x8]; 89 unsigned int vidtcon0; 90 unsigned int vidtcon1; 91 unsigned int vidtcon2; 92 unsigned int vidtcon3; 93 unsigned char res2[0x184]; 94 unsigned int trigcon; 95 }; 96 check_member(exynos5_disp_ctrl, trigcon, 0x1a4); 97 98 static struct exynos5_disp_ctrl * const exynos_disp_ctrl = 99 (void *)EXYNOS5_DISP1_CTRL_BASE; 100 101 #define VCLK_RISING_EDGE (1 << 7) 102 #define VCLK_RUNNING (1 << 9) 103 104 #define CHANNEL0_EN (1 << 0) 105 106 #define VSYNC_PULSE_WIDTH_VAL 0x3 107 #define VSYNC_PULSE_WIDTH_OFFSET 0 108 #define V_FRONT_PORCH_VAL 0x3 109 #define V_FRONT_PORCH_OFFSET 8 110 #define V_BACK_PORCH_VAL 0x3 111 #define V_BACK_PORCH_OFFSET 16 112 113 #define HSYNC_PULSE_WIDTH_VAL 0x3 114 #define HSYNC_PULSE_WIDTH_OFFSET 0 115 #define H_FRONT_PORCH_VAL 0x3 116 #define H_FRONT_PORCH_OFFSET 8 117 #define H_BACK_PORCH_VAL 0x3 118 #define H_BACK_PORCH_OFFSET 16 119 120 #define HOZVAL_OFFSET 0 121 #define LINEVAL_OFFSET 11 122 123 #define BPPMODE_F_RGB_16BIT_565 0x5 124 #define BPPMODE_F_OFFSET 2 125 #define ENWIN_F_ENABLE (1 << 0) 126 #define HALF_WORD_SWAP_EN (1 << 16) 127 128 #define OSD_RIGHTBOTX_F_OFFSET 11 129 #define OSD_RIGHTBOTY_F_OFFSET 0 130 #endif 131