1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef CPU_SAMSUNG_EXYNOS5250_DMC_H 4 #define CPU_SAMSUNG_EXYNOS5250_DMC_H 5 6 #ifndef __ASSEMBLER__ 7 8 #include <soc/cpu.h> 9 10 struct exynos5_dmc { 11 unsigned int concontrol; 12 unsigned int memcontrol; 13 unsigned int memconfig0; 14 unsigned int memconfig1; 15 unsigned int directcmd; 16 unsigned int prechconfig; 17 unsigned int phycontrol0; 18 unsigned char res1[0xc]; 19 unsigned int pwrdnconfig; 20 unsigned int timingpzq; 21 unsigned int timingref; 22 unsigned int timingrow; 23 unsigned int timingdata; 24 unsigned int timingpower; 25 unsigned int phystatus; 26 unsigned char res2[0x4]; 27 unsigned int chipstatus_ch0; 28 unsigned int chipstatus_ch1; 29 unsigned char res3[0x4]; 30 unsigned int mrstatus; 31 unsigned char res4[0x8]; 32 unsigned int qoscontrol0; 33 unsigned char resr5[0x4]; 34 unsigned int qoscontrol1; 35 unsigned char res6[0x4]; 36 unsigned int qoscontrol2; 37 unsigned char res7[0x4]; 38 unsigned int qoscontrol3; 39 unsigned char res8[0x4]; 40 unsigned int qoscontrol4; 41 unsigned char res9[0x4]; 42 unsigned int qoscontrol5; 43 unsigned char res10[0x4]; 44 unsigned int qoscontrol6; 45 unsigned char res11[0x4]; 46 unsigned int qoscontrol7; 47 unsigned char res12[0x4]; 48 unsigned int qoscontrol8; 49 unsigned char res13[0x4]; 50 unsigned int qoscontrol9; 51 unsigned char res14[0x4]; 52 unsigned int qoscontrol10; 53 unsigned char res15[0x4]; 54 unsigned int qoscontrol11; 55 unsigned char res16[0x4]; 56 unsigned int qoscontrol12; 57 unsigned char res17[0x4]; 58 unsigned int qoscontrol13; 59 unsigned char res18[0x4]; 60 unsigned int qoscontrol14; 61 unsigned char res19[0x4]; 62 unsigned int qoscontrol15; 63 unsigned char res20[0x14]; 64 unsigned int ivcontrol; 65 unsigned int wrtra_config; 66 unsigned int rdlvl_config; 67 unsigned char res21[0x8]; 68 unsigned int brbrsvconfig; 69 unsigned int brbqosconfig; 70 unsigned int membaseconfig0; 71 unsigned int membaseconfig1; 72 unsigned char res22[0xc]; 73 unsigned int wrlvl_config; 74 unsigned char res23[0xc]; 75 unsigned int perevcontrol; 76 unsigned int perev0config; 77 unsigned int perev1config; 78 unsigned int perev2config; 79 unsigned int perev3config; 80 unsigned char res24[0xdebc]; 81 unsigned int pmnc_ppc_a; 82 unsigned char res25[0xc]; 83 unsigned int cntens_ppc_a; 84 unsigned char res26[0xc]; 85 unsigned int cntenc_ppc_a; 86 unsigned char res27[0xc]; 87 unsigned int intens_ppc_a; 88 unsigned char res28[0xc]; 89 unsigned int intenc_ppc_a; 90 unsigned char res29[0xc]; 91 unsigned int flag_ppc_a; 92 unsigned char res30[0xac]; 93 unsigned int ccnt_ppc_a; 94 unsigned char res31[0xc]; 95 unsigned int pmcnt0_ppc_a; 96 unsigned char res32[0xc]; 97 unsigned int pmcnt1_ppc_a; 98 unsigned char res33[0xc]; 99 unsigned int pmcnt2_ppc_a; 100 unsigned char res34[0xc]; 101 unsigned int pmcnt3_ppc_a; 102 }; 103 check_member(exynos5_dmc, pmcnt3_ppc_a, 0xe140); 104 105 static struct exynos5_dmc * const exynos_dmc = (void *)EXYNOS5_DMC_CTRL_BASE; 106 107 struct exynos5_phy_control { 108 unsigned int phy_con0; 109 unsigned int phy_con1; 110 unsigned int phy_con2; 111 unsigned int phy_con3; 112 unsigned int phy_con4; 113 unsigned char res1[4]; 114 unsigned int phy_con6; 115 unsigned char res2[4]; 116 unsigned int phy_con8; 117 unsigned int phy_con9; 118 unsigned int phy_con10; 119 unsigned char res3[4]; 120 unsigned int phy_con12; 121 unsigned int phy_con13; 122 unsigned int phy_con14; 123 unsigned int phy_con15; 124 unsigned int phy_con16; 125 unsigned char res4[4]; /* NOT a mistake. Yes, it doesn't make sense. */ 126 unsigned int phy_con17; 127 unsigned int phy_con18; 128 unsigned int phy_con19; 129 unsigned int phy_con20; 130 unsigned int phy_con21; 131 unsigned int phy_con22; 132 unsigned int phy_con23; 133 unsigned int phy_con24; 134 unsigned int phy_con25; 135 unsigned int phy_con26; 136 unsigned int phy_con27; 137 unsigned int phy_con28; 138 unsigned int phy_con29; 139 unsigned int phy_con30; 140 unsigned int phy_con31; 141 unsigned int phy_con32; 142 unsigned int phy_con33; 143 unsigned int phy_con34; 144 unsigned int phy_con35; 145 unsigned int phy_con36; 146 unsigned int phy_con37; 147 unsigned int phy_con38; 148 unsigned int phy_con39; 149 unsigned int phy_con40; 150 unsigned int phy_con41; 151 unsigned int phy_con42; 152 }; 153 check_member(exynos5_phy_control, phy_con42, 0xac); 154 155 static struct exynos5_phy_control * const exynos_phy0_control = 156 (void *)EXYNOS5_DMC_PHY0_BASE; 157 static struct exynos5_phy_control * const exynos_phy1_control = 158 (void *)EXYNOS5_DMC_PHY1_BASE; 159 160 enum ddr_mode { 161 DDR_MODE_DDR2, 162 DDR_MODE_DDR3, 163 DDR_MODE_LPDDR2, 164 DDR_MODE_LPDDR3, 165 166 DDR_MODE_COUNT, 167 }; 168 169 /* For reasons unknown, people are in the habit of taking a 32-bit 170 * field with 2 possible values and packing it with, say, 2 bits. A 171 * non-robust encoding, using only 2 bits of a 32-bit field, is 172 * incredibly difficult to deal with when things go wrong, because 173 * there are a lot of things that get expressed as 0, 1, or 2. If 174 * you're scanning with jtag or dumping memory it is really hard to 175 * tell when you've hit the beginning of the struct. So, let's be a 176 * bit smart here. First, while it's common to let the enum count 177 * entries for you, when there are two of them, we can do the 178 * counting. And, let's set the values to something we can easily scan 179 * for in memory. Since '1' and '2' are rather common, we pick 180 * something that's actually of some value when things go wrong. This 181 * setup motivated by a use case: something's going wrong and having a 182 * manuf name of '1' or '2' is completely useless! 183 */ 184 enum mem_manuf { 185 MEM_MANUF_AUTODETECT, 186 MEM_MANUF_ELPIDA = 0xe7b1da, 187 MEM_MANUF_SAMSUNG = 0x5a5096, 188 189 MEM_MANUF_COUNT = 2, // fancy that. 190 }; 191 192 enum { 193 MEM_TIMINGS_MSR_COUNT = 4, 194 }; 195 196 #define DMC_INTERLEAVE_SIZE 0x1f 197 198 /* CONCONTROL register fields */ 199 #define CONCONTROL_DFI_INIT_START_SHIFT 28 200 #define CONCONTROL_RD_FETCH_SHIFT 12 201 #define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT) 202 #define CONCONTROL_AREF_EN_SHIFT 5 203 204 /* PRECHCONFIG register field */ 205 #define PRECHCONFIG_TP_CNT_SHIFT 24 206 207 /* PWRDNCONFIG register field */ 208 #define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0 209 #define PWRDNCONFIG_DSREF_CYC_SHIFT 16 210 211 /* PHY_CON0 register fields */ 212 #define PHY_CON0_T_WRRDCMD_SHIFT 17 213 #define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT) 214 #define PHY_CON0_CTRL_DDR_MODE_SHIFT 11 215 216 /* PHY_CON1 register fields */ 217 #define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0 218 219 /* PHY_CON12 register fields */ 220 #define PHY_CON12_CTRL_START_POINT_SHIFT 24 221 #define PHY_CON12_CTRL_INC_SHIFT 16 222 #define PHY_CON12_CTRL_FORCE_SHIFT 8 223 #define PHY_CON12_CTRL_START_SHIFT 6 224 #define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT) 225 #define PHY_CON12_CTRL_DLL_ON_SHIFT 5 226 #define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT) 227 #define PHY_CON12_CTRL_REF_SHIFT 1 228 229 /* PHY_CON16 register fields */ 230 #define PHY_CON16_ZQ_MODE_DDS_SHIFT 24 231 #define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT) 232 233 #define PHY_CON16_ZQ_MODE_TERM_SHIFT 21 234 #define PHY_CON16_ZQ_MODE_TERM_MASK (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT) 235 236 #define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19) 237 238 /* PHY_CON42 register fields */ 239 #define PHY_CON42_CTRL_BSTLEN_SHIFT 8 240 #define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT) 241 242 #define PHY_CON42_CTRL_RDLAT_SHIFT 0 243 #define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT) 244 245 /* These are the memory timings for a particular memory type and speed */ 246 struct mem_timings { 247 enum mem_manuf mem_manuf; /* Memory manufacturer */ 248 enum ddr_mode mem_type; /* Memory type */ 249 unsigned int frequency_mhz; /* Frequency of memory in MHz */ 250 251 /* Here follow the timing parameters for the selected memory */ 252 uint8_t apll_mdiv; 253 uint8_t apll_pdiv; 254 uint8_t apll_sdiv; 255 uint8_t mpll_mdiv; 256 uint8_t mpll_pdiv; 257 uint8_t mpll_sdiv; 258 uint8_t cpll_mdiv; 259 uint8_t cpll_pdiv; 260 uint8_t cpll_sdiv; 261 uint8_t gpll_pdiv; 262 uint16_t gpll_mdiv; 263 uint8_t gpll_sdiv; 264 uint8_t epll_mdiv; 265 uint8_t epll_pdiv; 266 uint8_t epll_sdiv; 267 uint8_t vpll_mdiv; 268 uint8_t vpll_pdiv; 269 uint8_t vpll_sdiv; 270 uint8_t bpll_mdiv; 271 uint8_t bpll_pdiv; 272 uint8_t bpll_sdiv; 273 uint8_t use_bpll; /* 1 to use BPLL for cdrex, 0 to use MPLL */ 274 uint8_t pclk_cdrex_ratio; 275 unsigned int direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; 276 277 unsigned int timing_ref; 278 unsigned int timing_row; 279 unsigned int timing_data; 280 unsigned int timing_power; 281 282 /* DQS, DQ, DEBUG offsets */ 283 unsigned int phy0_dqs; 284 unsigned int phy1_dqs; 285 unsigned int phy0_dq; 286 unsigned int phy1_dq; 287 uint8_t phy0_tFS; 288 uint8_t phy1_tFS; 289 uint8_t phy0_pulld_dqs; 290 uint8_t phy1_pulld_dqs; 291 292 uint8_t lpddr3_ctrl_phy_reset; 293 uint8_t ctrl_start_point; 294 uint8_t ctrl_inc; 295 uint8_t ctrl_start; 296 uint8_t ctrl_dll_on; 297 uint8_t ctrl_ref; 298 299 uint8_t ctrl_force; 300 uint8_t ctrl_rdlat; 301 uint8_t ctrl_bstlen; 302 303 uint8_t fp_resync; 304 uint8_t iv_size; 305 uint8_t dfi_init_start; 306 uint8_t aref_en; 307 308 uint8_t rd_fetch; 309 310 uint8_t zq_mode_dds; 311 uint8_t zq_mode_term; 312 uint8_t zq_mode_noterm; /* 1 to allow termination disable */ 313 314 unsigned int memcontrol; 315 unsigned int memconfig; 316 317 unsigned int membaseconfig0; 318 unsigned int membaseconfig1; 319 unsigned int prechconfig_tp_cnt; 320 unsigned int dpwrdn_cyc; 321 unsigned int dsref_cyc; 322 unsigned int concontrol; 323 /* Channel and Chip Selection */ 324 uint8_t dmc_channels; /* number of memory channels */ 325 uint8_t chips_per_channel; /* number of chips per channel */ 326 uint8_t chips_to_configure; /* number of chips to configure */ 327 uint8_t send_zq_init; /* 1 to send this command */ 328 unsigned int impedance; /* drive strength impedance */ 329 uint8_t gate_leveling_enable; /* check gate leveling is enabled */ 330 }; 331 332 /** 333 * Get the correct memory timings for our selected memory type and speed. 334 * 335 * @return pointer to the memory timings that we should use 336 */ 337 struct mem_timings *get_mem_timings(void); 338 339 #endif 340 #endif 341