1 /*
2 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
3 * Copyright (c) 2024, Altera Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 #include <assert.h>
8 #include <common/debug.h>
9 #include <drivers/delay_timer.h>
10 #include <errno.h>
11 #include <lib/mmio.h>
12 #include <platform_def.h>
13
14 #include "ncore_ccu.h"
15 #include "socfpga_mailbox.h"
16 #include "socfpga_plat_def.h"
17 #include "socfpga_system_manager.h"
18
19 uint32_t poll_active_bit(uint32_t dir);
20
21 #define SMMU_DMI 1
22 #define CCU_DMI0_DMIUSMCMCR SOCFPGA_CCU_NOC_REG_BASE + 0x7340
23 #define CCU_DMI0_DMIUSMCMAR SOCFPGA_CCU_NOC_REG_BASE + 0x7344
24 #define CCU_DMI0_DMIUSMCMCR_MNTOP GENMASK(3, 0)
25 #define MAX_DISTRIBUTED_MEM_INTERFACE 2
26 #define FLUSH_ALL_ENTRIES 0x4
27 #define CCU_DMI0_DMIUSMCMCR_ARRAY_ID GENMASK(21, 16)
28 #define ARRAY_ID_TAG 0x0
29 #define ARRAY_ID_DATA 0x1
30 #define CACHE_OPERATION_DONE BIT(0)
31 #define TIMEOUT_200MS 200
32
33 #define __bf_shf(x) (__builtin_ffsll(x) - 1)
34
35 #define FIELD_PREP(_mask, _val) \
36 ({ \
37 ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \
38 })
39
40 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
41 ncore_ccu_reg_t ncore_ccu_modules[] = {
42 {"caiu0@1c000000", 0x1C000000, 0x00001000},
43 {"ncaiu0@1c001000", 0x1C001000, 0x00001000},
44 {"ncaiu1@1c002000", 0x1C002000, 0x00001000},
45 {"ncaiu2@1c003000", 0x1C003000, 0x00001000},
46 {"ncaiu3@1c004000", 0x1C004000, 0x00001000},
47 {"dce0@1c005000", 0x1C005000, 0x00001000},
48 {"dce1@1c006000", 0x1C006000, 0x00001000},
49 {"dmi0@1c007000", 0x1C007000, 0x00001000},
50 {"dmi1@1c008000", 0x1C008000, 0x00001000},
51 {"noc_fw_l4_per@10d21000", 0x10D21000, 0x0000008C},
52 {"noc_fw_l4_sys@10d21100", 0x10D21100, 0x00000098},
53 {"noc_fw_lwsoc2fpga@10d21300", 0x10D21300, 0x00000004},
54 {"noc_fw_soc2fpga@10d21200", 0x10D21200, 0x00000004},
55 {"noc_fw_tcu@10d21400", 0x10D21400, 0x00000004}
56 };
57
58 ncore_ccu_t ccu_caiu0[] = {
59 /* CAIUAMIGR */
60 {0x000003C0, 0x00000003, 0x0000001F},
61 /* CAIUMIFSR */
62 {0x000003C4, 0x00000000, 0x07070777},
63 /* DII1_MPFEREGS */
64 {0x00000414, 0x00018000, 0xFFFFFFFF},
65 {0x00000418, 0x00000000, 0x000000FF},
66 {0x00000410, 0xC0E00200, 0xC1F03E1F},
67 /* DII2_GICREGS */
68 {0x00000424, 0x0001D000, 0xFFFFFFFF},
69 {0x00000428, 0x00000000, 0x000000FF},
70 {0x00000420, 0xC0800400, 0xC1F03E1F},
71 /* NCAIU0_LWSOC2FPGA */
72 {0x00000444, 0x00020000, 0xFFFFFFFF},
73 {0x00000448, 0x00000000, 0x000000FF},
74 {0x00000440, 0xC1100006, 0xC1F03E1F},
75 /* NCAIU0_SOC2FPGA_1G */
76 {0x00000454, 0x00040000, 0xFFFFFFFF},
77 {0x00000458, 0x00000000, 0x000000FF},
78 {0x00000450, 0xC1200006, 0xC1F03E1F},
79 /* DMI_SDRAM_2G */
80 {0x00000464, 0x00080000, 0xFFFFFFFF},
81 {0x00000468, 0x00000000, 0x000000FF},
82 {0x00000460, 0x81300006, 0xC1F03E1F},
83 /* NCAIU0_SOC2FPGA_16G */
84 {0x00000474, 0x00400000, 0xFFFFFFFF},
85 {0x00000478, 0x00000000, 0x000000FF},
86 {0x00000470, 0xC1600006, 0xC1F03E1F},
87 /* DMI_SDRAM_30G */
88 {0x00000484, 0x00800000, 0xFFFFFFFF},
89 {0x00000488, 0x00000000, 0x000000FF},
90 {0x00000480, 0x81700006, 0xC1F03E1F},
91 /* NCAIU0_SOC2FPGA_256G */
92 {0x00000494, 0x04000000, 0xFFFFFFFF},
93 {0x00000498, 0x00000000, 0x000000FF},
94 {0x00000490, 0xC1A00006, 0xC1F03E1F},
95 /* DMI_SDRAM_480G */
96 {0x000004A4, 0x08000000, 0xFFFFFFFF},
97 {0x000004A8, 0x00000000, 0x000000FF},
98 {0x000004A0, 0x81B00006, 0xC1F03E1F}
99 };
100
101 ncore_ccu_t ccu_ncaiu0[] = {
102 /* NCAIU0AMIGR */
103 {0x000003C0, 0x00000003, 0x0000001F},
104 /* NCAIU0MIFSR */
105 {0x000003C4, 0x00000000, 0x07070777},
106 /* PSS */
107 {0x00000404, 0x00010000, 0xFFFFFFFF},
108 {0x00000408, 0x00000000, 0x000000FF},
109 {0x00000400, 0xC0F00000, 0xC1F03E1F},
110 /* DII1_MPFEREGS */
111 {0x00000414, 0x00018000, 0xFFFFFFFF},
112 {0x00000418, 0x00000000, 0x000000FF},
113 {0x00000410, 0xC0E00200, 0xC1F03E1F},
114 /* NCAIU0_LWSOC2FPGA */
115 {0x00000444, 0x00020000, 0xFFFFFFFF},
116 {0x00000448, 0x00000000, 0x000000FF},
117 {0x00000440, 0xC1100006, 0xC1F03E1F},
118 /* NCAIU0_SOC2FPGA_1G */
119 {0x00000454, 0x00040000, 0xFFFFFFFF},
120 {0x00000458, 0x00000000, 0x000000FF},
121 {0x00000450, 0xC1200006, 0xC1F03E1F},
122 /* DMI_SDRAM_2G */
123 {0x00000464, 0x00080000, 0xFFFFFFFF},
124 {0x00000468, 0x00000000, 0x000000FF},
125 {0x00000460, 0x81300006, 0xC1F03E1F},
126 /* NCAIU0_SOC2FPGA_16G */
127 {0x00000474, 0x00400000, 0xFFFFFFFF},
128 {0x00000478, 0x00000000, 0x000000FF},
129 {0x00000470, 0xC1600006, 0xC1F03E1F},
130 /* DMI_SDRAM_30G */
131 {0x00000484, 0x00800000, 0xFFFFFFFF},
132 {0x00000488, 0x00000000, 0x000000FF},
133 {0x00000480, 0x81700006, 0xC1F03E1F},
134 /* NCAIU0_SOC2FPGA_256G */
135 {0x00000494, 0x04000000, 0xFFFFFFFF},
136 {0x00000498, 0x00000000, 0x000000FF},
137 {0x00000490, 0xC1A00006, 0xC1F03E1F},
138 /* DMI_SDRAM_480G */
139 {0x000004A4, 0x08000000, 0xFFFFFFFF},
140 {0x000004A8, 0x00000000, 0x000000FF},
141 {0x000004A0, 0x81B00006, 0xC1F03E1F}
142 };
143
144 ncore_ccu_t ccu_ncaiu1[] = {
145 /* NCAIU1AMIGR */
146 {0x000003C0, 0x00000003, 0x0000001F},
147 /* NCAIU1MIFSR */
148 {0x000003C4, 0x00000000, 0x07070777},
149 /* DMI_SDRAM_2G */
150 {0x00000464, 0x00080000, 0xFFFFFFFF},
151 {0x00000468, 0x00000000, 0x000000FF},
152 {0x00000460, 0x81300006, 0xC1F03E1F},
153 /* DMI_SDRAM_30G */
154 {0x00000484, 0x00800000, 0xFFFFFFFF},
155 {0x00000488, 0x00000000, 0x000000FF},
156 {0x00000480, 0x81700006, 0xC1F03E1F},
157 /* DMI_SDRAM_480G */
158 {0x000004A4, 0x08000000, 0xFFFFFFFF},
159 {0x000004A8, 0x00000000, 0x000000FF},
160 {0x000004A0, 0x81B00006, 0xC1F03E1F}
161 };
162
163 ncore_ccu_t ccu_ncaiu2[] = {
164 /* NCAIU2AMIGR */
165 {0x000003C0, 0x00000003, 0x0000001F},
166 /* NCAIU2MIFSR */
167 {0x000003C4, 0x00000000, 0x07070777},
168 /* DMI_SDRAM_2G */
169 {0x00000464, 0x00080000, 0xFFFFFFFF},
170 {0x00000468, 0x00000000, 0x000000FF},
171 {0x00000460, 0x81300006, 0xC1F03E1F},
172 /* DMI_SDRAM_30G */
173 {0x00000484, 0x00800000, 0xFFFFFFFF},
174 {0x00000488, 0x00000000, 0x000000FF},
175 {0x00000480, 0x81700006, 0xC1F03E1F},
176 /* DMI_SDRAM_480G */
177 {0x000004A4, 0x08000000, 0xFFFFFFFF},
178 {0x000004A8, 0x00000000, 0x000000FF},
179 {0x000004A0, 0x81B00006, 0xC1F03E1F}
180 };
181
182 ncore_ccu_t ccu_ncaiu3[] = {
183 /* NCAIU3AMIGR */
184 {0x000003C0, 0x00000003, 0x0000001F},
185 /* NCAIU3MIFSR */
186 {0x000003C4, 0x00000000, 0x07070777},
187 /* DII1_MPFEREGS */
188 {0x00000414, 0x00018000, 0xFFFFFFFF},
189 {0x00000418, 0x00000000, 0x000000FF},
190 {0x00000410, 0xC0E00200, 0xC1F03E1F},
191 /* DMI_SDRAM_2G */
192 {0x00000464, 0x00080000, 0xFFFFFFFF},
193 {0x00000468, 0x00000000, 0x000000FF},
194 {0x00000460, 0x81300006, 0xC1F03E1F},
195 /* DMI_SDRAM_30G */
196 {0x00000484, 0x00800000, 0xFFFFFFFF},
197 {0x00000488, 0x00000000, 0x000000FF},
198 {0x00000480, 0x81700006, 0xC1F03E1F},
199 /* DMI_SDRAM_480G */
200 {0x000004A4, 0x08000000, 0xFFFFFFFF},
201 {0x000004A8, 0x00000000, 0x000000FF},
202 {0x000004A0, 0x81B00006, 0xC1F03E1F}
203 };
204
205 ncore_ccu_t ccu_dce0[] = {
206 /* DCEUAMIGR0 */
207 {0x000003C0, 0x00000003, 0x0000001F},
208 /* DCEUMIFSR0 */
209 {0x000003C4, 0x00000000, 0x07070777},
210 /* DMI_SDRAM_2G */
211 {0x00000464, 0x00080000, 0xFFFFFFFF},
212 {0x00000468, 0x00000000, 0x000000FF},
213 {0x00000460, 0x81300006, 0xC1F03E1F},
214 /* DMI_SDRAM_30G */
215 {0x00000484, 0x00800000, 0xFFFFFFFF},
216 {0x00000488, 0x00000000, 0x000000FF},
217 {0x00000480, 0x81700006, 0xC1F03E1F},
218 /* DMI_SDRAM_480G */
219 {0x000004A4, 0x08000000, 0xFFFFFFFF},
220 {0x000004A8, 0x00000000, 0x000000FF},
221 {0x000004A0, 0x81B00006, 0xC1F03E1F}
222 };
223
224 ncore_ccu_t ccu_dce1[] = {
225 /* DCEUAMIGR1 */
226 {0x000003C0, 0x00000003, 0x0000001F},
227 /* DCEUMIFSR1 */
228 {0x000003C4, 0x00000000, 0x07070777},
229 /* DMI_SDRAM_2G */
230 {0x00000464, 0x00080000, 0xFFFFFFFF},
231 {0x00000468, 0x00000000, 0x000000FF},
232 {0x00000460, 0x81300006, 0xC1F03E1F},
233 /* DMI_SDRAM_30G */
234 {0x00000484, 0x00800000, 0xFFFFFFFF},
235 {0x00000488, 0x00000000, 0x000000FF},
236 {0x00000480, 0x81700006, 0xC1F03E1F},
237 /* DMI_SDRAM_480G */
238 {0x000004A4, 0x08000000, 0xFFFFFFFF},
239 {0x000004A8, 0x00000000, 0x000000FF},
240 {0x000004A0, 0x81B00006, 0xC1F03E1F}
241 };
242
243 ncore_ccu_t ccu_dmi0[] = {
244 /* DMIUSMCTCR */
245 {0x00000300, 0x00000001, 0x00000003},
246 {0x00000300, 0x00000003, 0x00000003}
247 };
248
249 ncore_ccu_t ccu_dmi1[] = {
250 /* DMIUSMCTCR */
251 {0x00000300, 0x00000001, 0x00000003},
252 {0x00000300, 0x00000003, 0x00000003}
253 };
254
255 ncore_ccu_t ccu_noc_fw_l4_per[] = {
256 /* NAND */
257 {0x00000000, 0x01010001, 0x01010001},
258 /* USB0 */
259 {0x0000000C, 0x01010001, 0x01010001},
260 /* USB1 */
261 {0x00000010, 0x01010001, 0x01010001},
262 /* SPI_MAIN0 */
263 {0x0000001C, 0x01010301, 0x01010301},
264 /* SPI_MAIN1 */
265 {0x00000020, 0x01010301, 0x01010301},
266 /* SPI_SECONDARY0 */
267 {0x00000024, 0x01010301, 0x01010301},
268 /* SPI_SECONDARY1 */
269 {0x00000028, 0x01010301, 0x01010301},
270 /* EMAC0 */
271 {0x0000002C, 0x01010001, 0x01010001},
272 /* EMAC1 */
273 {0x00000030, 0x01010001, 0x01010001},
274 /* EMAC2 */
275 {0x00000034, 0x01010001, 0x01010001},
276 /* SDMMC */
277 {0x00000040, 0x01010001, 0x01010001},
278 /* GPIO0 */
279 {0x00000044, 0x01010301, 0x01010301},
280 /* GPIO1 */
281 {0x00000048, 0x01010301, 0x01010301},
282 /* I2C0 */
283 {0x00000050, 0x01010301, 0x01010301},
284 /* I2C1 */
285 {0x00000054, 0x01010301, 0x01010301},
286 /* I2C2 */
287 {0x00000058, 0x01010301, 0x01010301},
288 /* I2C3 */
289 {0x0000005C, 0x01010301, 0x01010301},
290 /* I2C4 */
291 {0x00000060, 0x01010301, 0x01010301},
292 /* SP_TIMER0 */
293 {0x00000064, 0x01010301, 0x01010301},
294 /* SP_TIMER1 */
295 {0x00000068, 0x01010301, 0x01010301},
296 /* UART0 */
297 {0x0000006C, 0x01010301, 0x01010301},
298 /* UART1 */
299 {0x00000070, 0x01010301, 0x01010301},
300 /* I3C0 */
301 {0x00000074, 0x01010301, 0x01010301},
302 /* I3C1 */
303 {0x00000078, 0x01010301, 0x01010301},
304 /* DMA0 */
305 {0x0000007C, 0x01010001, 0x01010001},
306 /* DMA1 */
307 {0x00000080, 0x01010001, 0x01010001},
308 /* COMBO_PHY */
309 {0x00000084, 0x01010001, 0x01010001},
310 /* NAND_SDMA */
311 {0x00000088, 0x01010301, 0x01010301}
312 };
313
314 ncore_ccu_t ccu_noc_fw_l4_sys[] = {
315 /* DMA_ECC */
316 {0x00000008, 0x01010001, 0x01010001},
317 /* EMAC0RX_ECC */
318 {0x0000000C, 0x01010001, 0x01010001},
319 /* EMAC0TX_ECC */
320 {0x00000010, 0x01010001, 0x01010001},
321 /* EMAC1RX_ECC */
322 {0x00000014, 0x01010001, 0x01010001},
323 /* EMAC1TX_ECC */
324 {0x00000018, 0x01010001, 0x01010001},
325 /* EMAC2RX_ECC */
326 {0x0000001C, 0x01010001, 0x01010001},
327 /* EMAC2TX_ECC */
328 {0x00000020, 0x01010001, 0x01010001},
329 /* NAND_ECC */
330 {0x0000002C, 0x01010001, 0x01010001},
331 /* NAND_READ_ECC */
332 {0x00000030, 0x01010001, 0x01010001},
333 /* NAND_WRITE_ECC */
334 {0x00000034, 0x01010001, 0x01010001},
335 /* OCRAM_ECC */
336 {0x00000038, 0x01010001, 0x01010001},
337 /* SDMMC_ECC */
338 {0x00000040, 0x01010001, 0x01010001},
339 /* USB0_ECC */
340 {0x00000044, 0x01010001, 0x01010001},
341 /* USB1_CACHEECC */
342 {0x00000048, 0x01010001, 0x01010001},
343 /* CLOCK_MANAGER */
344 {0x0000004C, 0x01010001, 0x01010001},
345 /* IO_MANAGER */
346 {0x00000054, 0x01010001, 0x01010001},
347 /* RESET_MANAGER */
348 {0x00000058, 0x01010001, 0x01010001},
349 /* SYSTEM_MANAGER */
350 {0x0000005C, 0x01010001, 0x01010001},
351 /* OSC0_TIMER */
352 {0x00000060, 0x01010301, 0x01010301},
353 /* OSC1_TIMER0*/
354 {0x00000064, 0x01010301, 0x01010301},
355 /* WATCHDOG0 */
356 {0x00000068, 0x01010301, 0x01010301},
357 /* WATCHDOG1 */
358 {0x0000006C, 0x01010301, 0x01010301},
359 /* WATCHDOG2 */
360 {0x00000070, 0x01010301, 0x01010301},
361 /* WATCHDOG3 */
362 {0x00000074, 0x01010301, 0x01010301},
363 /* DAP */
364 {0x00000078, 0x03010001, 0x03010001},
365 /* WATCHDOG4 */
366 {0x0000007C, 0x01010301, 0x01010301},
367 /* POWER_MANAGER */
368 {0x00000080, 0x01010001, 0x01010001},
369 /* USB1_RXECC */
370 {0x00000084, 0x01010001, 0x01010001},
371 /* USB1_TXECC */
372 {0x00000088, 0x01010001, 0x01010001},
373 /* L4_NOC_PROBES */
374 {0x00000090, 0x01010001, 0x01010001},
375 /* L4_NOC_QOS */
376 {0x00000094, 0x01010001, 0x01010001}
377 };
378
379 ncore_ccu_t ccu_noc_fw_lwsoc2fpga[] = {
380 /* LWSOC2FPGA_CSR */
381 {0x00000000, 0x0FFE0301, 0x0FFE0301}
382 };
383
384 ncore_ccu_t ccu_noc_fw_soc2fpga[] = {
385 /* SOC2FPGA_CSR */
386 {0x00000000, 0x0FFE0301, 0x0FFE0301}
387 };
388
389 ncore_ccu_t ccu_noc_fw_tcu[] = {
390 /* TCU_CSR */
391 {0x00000000, 0x01010001, 0x01010001}
392 };
393
init_ncore_ccu(void)394 uint32_t init_ncore_ccu(void)
395 {
396 ncore_ccu_t *ccu_module_table = NULL;
397 uint32_t base;
398 uint32_t size;
399 uint32_t val;
400 uint32_t offset;
401 uint32_t mask;
402 uint32_t set_mask = 0U;
403 uint32_t reg = 0U;
404
405 for (int index = 0; index < ARRAY_SIZE(ncore_ccu_modules); index++) {
406 base = ncore_ccu_modules[index].base;
407 size = ncore_ccu_modules[index].size;
408
409 switch (index) {
410 case 0:
411 ccu_module_table = ccu_caiu0;
412 size = (sizeof(ccu_caiu0) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
413 break;
414
415 case 1:
416 ccu_module_table = ccu_ncaiu0;
417 size = (sizeof(ccu_ncaiu0) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
418 break;
419
420 case 2:
421 ccu_module_table = ccu_ncaiu1;
422 size = (sizeof(ccu_ncaiu1) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
423 break;
424
425 case 3:
426 ccu_module_table = ccu_ncaiu2;
427 size = (sizeof(ccu_ncaiu2) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
428 break;
429
430 case 4:
431 ccu_module_table = ccu_ncaiu3;
432 size = (sizeof(ccu_ncaiu3) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
433 break;
434
435 case 5:
436 ccu_module_table = ccu_dce0;
437 size = (sizeof(ccu_dce0) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
438 break;
439
440 case 6:
441 ccu_module_table = ccu_dce1;
442 size = (sizeof(ccu_dce1) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
443 break;
444
445 case 7:
446 ccu_module_table = ccu_dmi0;
447 size = (sizeof(ccu_dmi0) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
448 break;
449
450 case 8:
451 ccu_module_table = ccu_dmi1;
452 size = (sizeof(ccu_dmi1) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
453 break;
454
455 case 9:
456 ccu_module_table = ccu_noc_fw_l4_per;
457 size = (sizeof(ccu_noc_fw_l4_per) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
458 break;
459
460 case 10:
461 ccu_module_table = ccu_noc_fw_l4_sys;
462 size = (sizeof(ccu_noc_fw_l4_sys) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
463 break;
464
465 case 11:
466 ccu_module_table = ccu_noc_fw_lwsoc2fpga;
467 size = (sizeof(ccu_noc_fw_lwsoc2fpga) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
468 break;
469
470 case 12:
471 ccu_module_table = ccu_noc_fw_soc2fpga;
472 size = (sizeof(ccu_noc_fw_soc2fpga) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
473 break;
474
475 case 13:
476 ccu_module_table = ccu_noc_fw_tcu;
477 size = (sizeof(ccu_noc_fw_tcu) / CCU_WORD_BYTE) / CCU_OFFSET_VAL_MASK;
478 break;
479
480 default:
481 break;
482 }
483
484 VERBOSE("CCU node base addr 0x%x, name %s, size 0x%x and module table %p\n",
485 base, ncore_ccu_modules[index].name, size, (uint32_t *)ccu_module_table);
486
487 /*
488 * First element: offset
489 * Second element: val
490 * Third element: mask
491 */
492 for (int i = 0; i < size; i++) {
493 offset = ccu_module_table[i].offset;
494 val = ccu_module_table[i].val;
495
496 /* Reads the masking bit value from the list */
497 mask = ccu_module_table[i].mask;
498
499 if (mask != 0) {
500 if (mask == 0xFFFFFFFF) {
501 reg = base + offset;
502 mmio_write_32((uintptr_t)reg, val);
503 } else {
504 /* Mask the value with the masking bits */
505 set_mask = val & mask;
506 reg = base + offset;
507
508 /* Clears and sets specific bits in the register */
509 mmio_clrsetbits_32((uintptr_t)reg, mask, set_mask);
510 }
511 }
512
513 }
514
515 }
516
517 return 0;
518 }
519 #endif
520
521 static coh_ss_id_t subsystem_id;
get_subsystem_id(void)522 void get_subsystem_id(void)
523 {
524 uint32_t snoop_filter, directory, coh_agent;
525 snoop_filter = CSIDR_NUM_SF(mmio_read_32(NCORE_CCU_CSR(NCORE_CSIDR)));
526 directory = CSUIDR_NUM_DIR(mmio_read_32(NCORE_CCU_CSR(NCORE_CSUIDR)));
527 coh_agent = CSUIDR_NUM_CAI(mmio_read_32(NCORE_CCU_CSR(NCORE_CSUIDR)));
528 subsystem_id.num_snoop_filter = snoop_filter + 1;
529 subsystem_id.num_directory = directory;
530 subsystem_id.num_coh_agent = coh_agent;
531 }
532
directory_init(void)533 uint32_t directory_init(void)
534 {
535 uint32_t dir_sf_mtn, dir_sf_en;
536 uint32_t dir, sf, ret;
537 for (dir = 0; dir < subsystem_id.num_directory; dir++) {
538 for (sf = 0; sf < subsystem_id.num_snoop_filter; sf++) {
539 dir_sf_mtn = DIRECTORY_UNIT(dir, NCORE_DIRUSFMCR);
540 dir_sf_en = DIRECTORY_UNIT(dir, NCORE_DIRUSFER);
541 /* Initialize All Entries */
542 mmio_write_32(dir_sf_mtn, SNOOP_FILTER_ID(sf));
543 /* Poll Active Bit */
544 ret = poll_active_bit(dir);
545 if (ret != 0) {
546 ERROR("Timeout during active bit polling\n");
547 return -ETIMEDOUT;
548 }
549 /* Disable snoop filter, a bit per snoop filter */
550 mmio_clrbits_32(dir_sf_en, BIT(sf));
551 }
552 }
553 return 0;
554 }
555
coherent_agent_intfc_init(void)556 uint32_t coherent_agent_intfc_init(void)
557 {
558 uint32_t dir, ca, ca_id, ca_type, ca_snoop_en;
559 for (dir = 0; dir < subsystem_id.num_directory; dir++) {
560 for (ca = 0; ca < subsystem_id.num_coh_agent; ca++) {
561 ca_snoop_en = DIRECTORY_UNIT(ca, NCORE_DIRUCASER0);
562 ca_id = mmio_read_32(COH_AGENT_UNIT(ca, NCORE_CAIUIDR));
563 /* Coh Agent Snoop Enable */
564 if (CACHING_AGENT_BIT(ca_id))
565 mmio_setbits_32(ca_snoop_en, BIT(ca));
566 /* Coh Agent Snoop DVM Enable */
567 ca_type = CACHING_AGENT_TYPE(ca_id);
568 if (ca_type == ACE_W_DVM || ca_type == ACE_L_W_DVM)
569 mmio_setbits_32(NCORE_CCU_CSR(NCORE_CSADSER0),
570 BIT(ca));
571 }
572 }
573 return 0;
574 }
575
poll_active_bit(uint32_t dir)576 uint32_t poll_active_bit(uint32_t dir)
577 {
578 uint32_t timeout = 80000;
579 uint32_t poll_dir = DIRECTORY_UNIT(dir, NCORE_DIRUSFMAR);
580 while (timeout > 0) {
581 if (mmio_read_32(poll_dir) == 0)
582 return 0;
583 timeout--;
584 }
585 return -1;
586 }
587
bypass_ocram_firewall(void)588 void bypass_ocram_firewall(void)
589 {
590 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1),
591 OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
592 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF2),
593 OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
594 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF3),
595 OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
596 mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4),
597 OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
598 }
599
ncore_enable_ocram_firewall(void)600 void ncore_enable_ocram_firewall(void)
601 {
602 mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1),
603 OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
604 mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF2),
605 OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
606 mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF3),
607 OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
608 mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4),
609 OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
610 }
611
612 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
init_ncore_ccu(void)613 uint32_t init_ncore_ccu(void)
614 {
615 uint32_t status;
616 get_subsystem_id();
617 status = directory_init();
618 status = coherent_agent_intfc_init();
619 bypass_ocram_firewall();
620 return status;
621 }
622 #endif
623
setup_smmu_stream_id(void)624 void setup_smmu_stream_id(void)
625 {
626 /* Configure Stream ID for Agilex5 */
627 mmio_write_32(SOCFPGA_SYSMGR(DMA_TBU_STREAM_ID_AX_REG_0_DMA0), DMA0);
628 mmio_write_32(SOCFPGA_SYSMGR(DMA_TBU_STREAM_ID_AX_REG_0_DMA1), DMA1);
629 mmio_write_32(SOCFPGA_SYSMGR(SDM_TBU_STREAM_ID_AX_REG_1_SDM), SDM);
630 /* Reg map showing USB2 but Linux USB0? */
631 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_USB2), USB0);
632 /* Reg map showing USB3 but Linux USB1? */
633 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_USB3), USB1);
634 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_SDMMC), SDMMC);
635 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_NAND), NAND);
636 /* To confirm ETR - core sight debug*/
637 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_ETR), CORE_SIGHT_DEBUG);
638 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_TSN0), TSN0);
639 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_TSN1), TSN1);
640 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_TSN2), TSN2);
641 /* Enabled Stream ctrl register for Agilex5 */
642 mmio_write_32(SOCFPGA_SYSMGR(DMA_TBU_STREAM_CTRL_REG_0_DMA0), ENABLE_STREAMID);
643 mmio_write_32(SOCFPGA_SYSMGR(DMA_TBU_STREAM_CTRL_REG_0_DMA1), ENABLE_STREAMID);
644 mmio_write_32(SOCFPGA_SYSMGR(SDM_TBU_STREAM_CTRL_REG_1_SDM), ENABLE_STREAMID);
645 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_CTRL_REG_2_USB2), ENABLE_STREAMID);
646 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_CTRL_REG_2_USB3), ENABLE_STREAMID);
647 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_CTRL_REG_2_SDMMC), ENABLE_STREAMID);
648 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_CTRL_REG_2_NAND), ENABLE_STREAMID);
649 mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_CTRL_REG_2_ETR), ENABLE_STREAMID);
650 mmio_write_32(SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN0), ENABLE_STREAMID);
651 mmio_write_32(SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN1), ENABLE_STREAMID);
652 mmio_write_32(SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN2), ENABLE_STREAMID);
653 }
654
655 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
656 /* TODO: Temp added this here*/
poll_idle_status(uint32_t addr,uint32_t mask,uint32_t match,uint32_t delay_ms)657 static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_ms)
658 {
659 int time_out = delay_ms;
660
661 while (time_out-- > 0) {
662
663 if ((mmio_read_32(addr) & mask) == match) {
664 return 0;
665 }
666 udelay(1000);
667 }
668
669 return -ETIMEDOUT;
670 }
671
flush_l3_dcache(void)672 int flush_l3_dcache(void)
673 {
674 int i;
675 int ret = 0;
676
677 /* Flushing all entries in CCU system memory cache */
678 for (i = 0; i < MAX_DISTRIBUTED_MEM_INTERFACE; i++) {
679 mmio_write_32(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) |
680 FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_TAG),
681 (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000)));
682
683 /* Wait for cache maintenance operation done */
684 ret = poll_idle_status((CCU_DMI0_DMIUSMCMAR +
685 (i * 0x1000)), CACHE_OPERATION_DONE,
686 CACHE_OPERATION_DONE, TIMEOUT_200MS);
687
688 if (ret != 0) {
689 VERBOSE("%s: Timeout while waiting for flushing tag in DMI%d done\n",
690 __func__, i);
691 return ret;
692 }
693
694 mmio_write_32(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) |
695 FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_DATA),
696 (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000)));
697
698 /* Wait for cache maintenance operation done */
699 ret = poll_idle_status((CCU_DMI0_DMIUSMCMAR +
700 (i * 0x1000)), CACHE_OPERATION_DONE,
701 CACHE_OPERATION_DONE, TIMEOUT_200MS);
702
703 if (ret != 0) {
704 VERBOSE("%s: Timeout while waiting for flushing data in DMI%d done\n",
705 __func__, i);
706 }
707 }
708
709 return ret;
710 }
711 #endif
712