1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <device/pci_ops.h>
4 #include <southbridge/intel/i82801ix/i82801ix.h>
5 #include "gm45.h"
6
gm45_early_init(void)7 void gm45_early_init(void)
8 {
9 const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0);
10
11 /* Setup MCHBAR. */
12 pci_write_config32(d0f0, D0F0_MCHBAR_LO, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1);
13
14 /* Setup DMIBAR. */
15 pci_write_config32(d0f0, D0F0_DMIBAR_LO, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
16
17 /* Setup EPBAR. */
18 pci_write_config32(d0f0, D0F0_EPBAR_LO, CONFIG_FIXED_EPBAR_MMIO_BASE | 1);
19
20 pci_write_config32(d0f0, D0F0_PMBASE, DEFAULT_PMBASE | 1);
21
22 /* Set C0000-FFFFF to access RAM on both reads and writes */
23 pci_write_config8(d0f0, D0F0_PAM(0), 0x30);
24 pci_write_config8(d0f0, D0F0_PAM(1), 0x33);
25 pci_write_config8(d0f0, D0F0_PAM(2), 0x33);
26 pci_write_config8(d0f0, D0F0_PAM(3), 0x33);
27 pci_write_config8(d0f0, D0F0_PAM(4), 0x33);
28 pci_write_config8(d0f0, D0F0_PAM(5), 0x33);
29 pci_write_config8(d0f0, D0F0_PAM(6), 0x33);
30 }
31