1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <acpi/acpi.h>
4 #include <assert.h>
5 #include <bootmode.h>
6 #include <console/console.h>
7 #include <device/mmio.h>
8 #include <device/pci.h>
9 #include <device/pci_ids.h>
10 #include <drivers/intel/gma/i915.h>
11 #include <drivers/intel/gma/libgfxinit.h>
12 #include <drivers/intel/gma/opregion.h>
13 #include <intelblocks/cfg.h>
14 #include <intelblocks/graphics.h>
15 #include <fsp/graphics.h>
16 #include <soc/pci_devs.h>
17 #include <types.h>
18
19 /* Display Type:
20 * 0 - only internal display aka eDP attached
21 * 1 - only external display aka HDMI/USB-C attached
22 * 2 - dual display aka both internal and external display attached
23 */
24 enum display_type {
25 INTERNAL_DISPLAY_ONLY,
26 EXTERNAL_DISPLAY_ONLY,
27 DUAL_DISPLAY,
28 };
29
30 #define GFX_MBUS_CTL 0x4438C
31 #define GFX_MBUS_SEL(x) (GFX_MBUS_CTL + (x))
32 #define GFX_MBUS_JOIN BIT(31)
33 #define GFX_MBUS_HASHING_MODE BIT(30)
34 #define GFX_MBUS_JOIN_PIPE_SEL (BIT(28) | BIT(27) | BIT(26))
35
36 /* SoC Overrides */
graphics_soc_panel_init(struct device * dev)37 __weak void graphics_soc_panel_init(struct device *dev)
38 {
39 /*
40 * User needs to implement SoC override in case wishes
41 * to perform certain specific graphics initialization
42 */
43 }
44
45 __weak const struct i915_gpu_controller_info *
intel_igd_get_controller_info(const struct device * device)46 intel_igd_get_controller_info(const struct device *device)
47 {
48 return NULL;
49 }
50
graphics_get_ddi_func_ctrl(unsigned long reg)51 static uint32_t graphics_get_ddi_func_ctrl(unsigned long reg)
52 {
53 uint32_t ddi_func_ctrl = graphics_gtt_read(reg);
54 ddi_func_ctrl &= TRANS_DDI_PORT_MASK;
55
56 return ddi_func_ctrl;
57 }
58
59 /*
60 * Transcoders contain the timing generators for eDP, DP, and HDMI interfaces.
61 * Intel transcoders are based on Quick Sync Video, which offloads video
62 * encoding and decoding tasks from the CPU to the GPU.
63 *
64 * On Intel silicon, there are four display pipes (DDI-A to DDI-D) that support
65 * blending, color adjustments, scaling, and dithering.
66 *
67 * From the display block diagram perspective, the front end of the display
68 * contains the pipes. The pipes connect to the transcoder. The transcoder
69 * (except for wireless) connects to the DDIs to drive the IO/PHY.
70 *
71 * This logic checks if the DDI-A port is attached to the transcoder and
72 * enabled (bit 27). Traditionally, the on-board display (eDP) is attached to DDI-A.
73 * If the above conditions is met, then the on-board display is present and enabled.
74 *
75 * On platforms without an on-board display (i.e., value at bits 27-30 is between 2-9),
76 * meaning that DDI-A (eDP) is not enabled.
77 *
78 * Additionally, if bits 27-30 are all set to 0, this means that no DDI ports
79 * are enabled, and there is no display.
80 *
81 * Consider external display is present and enabled, if eDP/DDI-A is not enabled
82 * and transcoder is attached to any DDI port (bits 27-30 are not zero).
83 */
get_external_display_status(void)84 static enum display_type get_external_display_status(void)
85 {
86 /* Read the transcoder register for DDI-A (eDP) */
87 uint32_t ddi_a_func_ctrl = graphics_get_ddi_func_ctrl(TRANS_DDI_FUNC_CTL_A);
88 /* Read the transcoder register for DDI-B (HDMI) */
89 uint32_t ddi_b_func_ctrl = graphics_get_ddi_func_ctrl(TRANS_DDI_FUNC_CTL_B);
90
91 /*
92 * Check if transcoder is none or connected to DDI-A port (aka eDP).
93 * Report no external display in both cases.
94 */
95 if (ddi_a_func_ctrl == TRANS_DDI_PORT_NONE) {
96 return INTERNAL_DISPLAY_ONLY;
97 } else {
98 if (ddi_a_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_A) &&
99 (ddi_b_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_B)
100 #if CONFIG(INTEL_GMA_VERSION_2)
101 || ddi_b_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_USB_C1)
102 || ddi_b_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_USB_C2)
103 || ddi_b_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_USB_C3)
104 || ddi_b_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_USB_C4)
105 #endif
106 )) {
107 /*
108 * Dual display detected: both DDI-A(eDP) and
109 * DDI-B(HDMI) pipes are active
110 */
111 return DUAL_DISPLAY;
112 } else {
113 if (ddi_a_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_A))
114 return INTERNAL_DISPLAY_ONLY;
115 else
116 return EXTERNAL_DISPLAY_ONLY;
117 }
118 }
119 }
120
121 /* Check and report if an external display is attached */
fsp_soc_report_external_display(void)122 int fsp_soc_report_external_display(void)
123 {
124 return graphics_get_framebuffer_address() && get_external_display_status();
125 }
126
configure_ddi_a_bifurcation(void)127 static void configure_ddi_a_bifurcation(void)
128 {
129 u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
130 /* Only program if the buffer is not enabled yet. */
131 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE)
132 return;
133
134 if (CONFIG(SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION))
135 ddi_buf_ctl &= ~DDI_A_4_LANES;
136 else
137 ddi_buf_ctl |= DDI_A_4_LANES;
138
139 graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
140 }
141
gma_init(struct device * const dev)142 static void gma_init(struct device *const dev)
143 {
144 intel_gma_init_igd_opregion();
145
146 /* SoC specific panel init/configuration.
147 If FSP has already run/configured the IGD, we can assume the
148 panel/backlight control have already been set up sufficiently
149 and that we shouldn't attempt to reconfigure things. */
150 if (!CONFIG(RUN_FSP_GOP))
151 graphics_soc_panel_init(dev);
152
153 if (CONFIG(SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION) && !acpi_is_wakeup_s3())
154 configure_ddi_a_bifurcation();
155
156 /*
157 * GFX PEIM module inside FSP binary is taking care of graphics
158 * initialization based on RUN_FSP_GOP Kconfig option and input
159 * VBT file. Need to report the framebuffer info after PCI enumeration.
160 *
161 * In case of non-FSP solution, SoC need to select another
162 * Kconfig to perform GFX initialization.
163 */
164 if (CONFIG(RUN_FSP_GOP) && display_init_required()) {
165 const struct soc_intel_common_config *config = chip_get_common_soc_structure();
166 fsp_report_framebuffer_info(graphics_get_framebuffer_address(),
167 config->panel_orientation);
168 return;
169 }
170
171 if (!CONFIG(NO_GFX_INIT))
172 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
173
174 if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
175 if (!acpi_is_wakeup_s3() && display_init_required()) {
176 int lightup_ok;
177 gma_gfxinit(&lightup_ok);
178 gfx_set_init_done(lightup_ok);
179 }
180 } else {
181 /* Initialize PCI device, load/execute BIOS Option ROM */
182 pci_dev_init(dev);
183 }
184 }
185
gma_generate_ssdt(const struct device * device)186 static void gma_generate_ssdt(const struct device *device)
187 {
188 const struct i915_gpu_controller_info *gfx = intel_igd_get_controller_info(device);
189
190 if (gfx)
191 drivers_intel_gma_displays_ssdt_generate(gfx);
192 }
193
is_graphics_disabled(struct device * dev)194 static int is_graphics_disabled(struct device *dev)
195 {
196 /* Check if Graphics PCI device is disabled */
197 if (!dev || !dev->enabled)
198 return 1;
199
200 return 0;
201 }
202
graphics_get_bar(struct device * dev,unsigned long index)203 static uintptr_t graphics_get_bar(struct device *dev, unsigned long index)
204 {
205 struct resource *gm_res;
206
207 gm_res = probe_resource(dev, index);
208 if (!gm_res)
209 return 0;
210
211 return gm_res->base;
212 }
213
graphics_get_framebuffer_address(void)214 uintptr_t graphics_get_framebuffer_address(void)
215 {
216 uintptr_t memory_base;
217 struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
218
219 if (is_graphics_disabled(dev))
220 return 0;
221
222 memory_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_2);
223 if (!memory_base)
224 die_with_post_code(POSTCODE_HW_INIT_FAILURE,
225 "Graphic memory bar2 is not programmed!");
226
227 memory_base += CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET;
228
229 return memory_base;
230 }
231
graphics_get_gtt_base(void)232 static uintptr_t graphics_get_gtt_base(void)
233 {
234 static uintptr_t gtt_base;
235 struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
236
237 if (is_graphics_disabled(dev))
238 die("IGD is disabled!");
239 /*
240 * GFX PCI config space offset 0x10 know as Graphics
241 * Translation Table Memory Mapped Range Address
242 * (GTTMMADR)
243 */
244 if (!gtt_base) {
245 gtt_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_0);
246 if (!gtt_base)
247 die_with_post_code(POSTCODE_HW_INIT_FAILURE,
248 "GTTMMADR is not programmed!");
249 }
250 return gtt_base;
251 }
252
graphics_gtt_read(unsigned long reg)253 uint32_t graphics_gtt_read(unsigned long reg)
254 {
255 return read32p(graphics_get_gtt_base() + reg);
256 }
257
graphics_gtt_write(unsigned long reg,uint32_t data)258 void graphics_gtt_write(unsigned long reg, uint32_t data)
259 {
260 write32p(graphics_get_gtt_base() + reg, data);
261 }
262
graphics_gtt_rmw(unsigned long reg,uint32_t andmask,uint32_t ormask)263 void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask)
264 {
265 uint32_t val = graphics_gtt_read(reg);
266 val &= andmask;
267 val |= ormask;
268 graphics_gtt_write(reg, val);
269 }
270
graphics_dev_read_resources(struct device * dev)271 static void graphics_dev_read_resources(struct device *dev)
272 {
273 pci_dev_read_resources(dev);
274
275 if (CONFIG(SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO)) {
276 struct resource *res_bar0 = find_resource(dev, PCI_BASE_ADDRESS_0);
277 if (res_bar0->flags & IORESOURCE_PREFETCH)
278 res_bar0->flags &= ~IORESOURCE_PREFETCH;
279 }
280
281 /*
282 * If libhwbase static MMIO driver is used, IGD BAR 0 has to be set to
283 * CONFIG_GFX_GMA_DEFAULT_MMIO for the libgfxinit to operate properly.
284 */
285 if (CONFIG(MAINBOARD_USE_LIBGFXINIT) && CONFIG(HWBASE_STATIC_MMIO)) {
286 struct resource *res_bar0 = find_resource(dev, PCI_BASE_ADDRESS_0);
287 res_bar0->base = CONFIG_GFX_GMA_DEFAULT_MMIO;
288 res_bar0->flags |= IORESOURCE_ASSIGNED;
289 pci_dev_set_resources(dev);
290 res_bar0->flags |= IORESOURCE_FIXED;
291 }
292 }
293
graphics_join_mbus(void)294 static void graphics_join_mbus(void)
295 {
296 enum display_type type = get_external_display_status();
297 uint32_t hashing_mode = 0; /* 2x2 */
298 if (type == INTERNAL_DISPLAY_ONLY) {
299 hashing_mode = GFX_MBUS_HASHING_MODE; /* 1x4 */
300 /* Only eDP pipes is joining the MBUS */
301 graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_A), PIPE_A, GFX_MBUS_JOIN | hashing_mode);
302 } else if (type == DUAL_DISPLAY) {
303 /* All pipes are joining the MBUS */
304 graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_A), PIPE_A, GFX_MBUS_JOIN | hashing_mode);
305 graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_B), PIPE_B, GFX_MBUS_JOIN | hashing_mode);
306 graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_C), PIPE_C, GFX_MBUS_JOIN | hashing_mode);
307 #if CONFIG(INTEL_GMA_VERSION_2)
308 graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_D), PIPE_D, GFX_MBUS_JOIN | hashing_mode);
309 #endif
310 } else {
311 /* No pipe joins the MBUS */
312 graphics_gtt_rmw(GFX_MBUS_CTL, GFX_MBUS_JOIN_PIPE_SEL,
313 GFX_MBUS_JOIN | hashing_mode);
314 }
315 }
316
graphics_dev_final(struct device * dev)317 static void graphics_dev_final(struct device *dev)
318 {
319 pci_dev_request_bus_master(dev);
320
321 /*
322 * Call function to join the MBUS if GFX PEIM module inside FSP
323 * binary is taking care of graphics initialization based on
324 * RUN_FSP_GOP config option.
325 *
326 * Skip FW joining the MBUS in case of non-FSP solution.
327 */
328 if (CONFIG(RUN_FSP_GOP) && CONFIG(SOC_INTEL_GFX_MBUS_JOIN) && display_init_required())
329 graphics_join_mbus();
330 }
331
332 const struct device_operations graphics_ops = {
333 .read_resources = graphics_dev_read_resources,
334 .set_resources = pci_dev_set_resources,
335 .enable_resources = pci_dev_enable_resources,
336 .init = gma_init,
337 .final = graphics_dev_final,
338 .ops_pci = &pci_dev_ops_pci,
339 #if CONFIG(HAVE_ACPI_TABLES)
340 .acpi_fill_ssdt = gma_generate_ssdt,
341 #endif
342 .scan_bus = scan_generic_bus,
343 };
344
345 static const unsigned short pci_device_ids[] = {
346 PCI_DID_INTEL_PTL_GT2,
347 PCI_DID_INTEL_LNL_M_GT2,
348 PCI_DID_INTEL_RPL_U_GT1,
349 PCI_DID_INTEL_RPL_U_GT2,
350 PCI_DID_INTEL_RPL_U_GT3,
351 PCI_DID_INTEL_RPL_U_GT4,
352 PCI_DID_INTEL_RPL_U_GT5,
353 PCI_DID_INTEL_RPL_P_GT1,
354 PCI_DID_INTEL_RPL_P_GT2,
355 PCI_DID_INTEL_RPL_P_GT3,
356 PCI_DID_INTEL_RPL_P_GT4,
357 PCI_DID_INTEL_RPL_P_GT5,
358 PCI_DID_INTEL_MTL_M_GT2,
359 PCI_DID_INTEL_MTL_P_GT2_1,
360 PCI_DID_INTEL_MTL_P_GT2_2,
361 PCI_DID_INTEL_MTL_P_GT2_3,
362 PCI_DID_INTEL_MTL_P_GT2_4,
363 PCI_DID_INTEL_MTL_P_GT2_5,
364 PCI_DID_INTEL_APL_IGD_HD_505,
365 PCI_DID_INTEL_APL_IGD_HD_500,
366 PCI_DID_INTEL_CNL_GT2_ULX_1,
367 PCI_DID_INTEL_CNL_GT2_ULX_2,
368 PCI_DID_INTEL_CNL_GT2_ULX_3,
369 PCI_DID_INTEL_CNL_GT2_ULX_4,
370 PCI_DID_INTEL_CNL_GT2_ULT_1,
371 PCI_DID_INTEL_CNL_GT2_ULT_2,
372 PCI_DID_INTEL_CNL_GT2_ULT_3,
373 PCI_DID_INTEL_CNL_GT2_ULT_4,
374 PCI_DID_INTEL_GLK_IGD,
375 PCI_DID_INTEL_GLK_IGD_EU12,
376 PCI_DID_INTEL_WHL_GT1_ULT_1,
377 PCI_DID_INTEL_WHL_GT2_ULT_1,
378 PCI_DID_INTEL_AML_GT2_ULX,
379 PCI_DID_INTEL_CFL_H_GT2,
380 PCI_DID_INTEL_CFL_H_XEON_GT2,
381 PCI_DID_INTEL_CFL_S_GT1_1,
382 PCI_DID_INTEL_CFL_S_GT1_2,
383 PCI_DID_INTEL_CFL_S_GT2_1,
384 PCI_DID_INTEL_CFL_S_GT2_2,
385 PCI_DID_INTEL_CFL_S_GT2_3,
386 PCI_DID_INTEL_CFL_S_GT2_4,
387 PCI_DID_INTEL_CFL_S_GT2_5,
388 PCI_DID_INTEL_CML_GT1_ULT_1,
389 PCI_DID_INTEL_CML_GT1_ULT_2,
390 PCI_DID_INTEL_CML_GT2_ULT_1,
391 PCI_DID_INTEL_CML_GT2_ULT_2,
392 PCI_DID_INTEL_CML_GT1_ULT_3,
393 PCI_DID_INTEL_CML_GT1_ULT_4,
394 PCI_DID_INTEL_CML_GT2_ULT_5,
395 PCI_DID_INTEL_CML_GT2_ULT_6,
396 PCI_DID_INTEL_CML_GT2_ULT_7,
397 PCI_DID_INTEL_CML_GT2_ULT_8,
398 PCI_DID_INTEL_CML_GT2_ULT_3,
399 PCI_DID_INTEL_CML_GT2_ULT_4,
400 PCI_DID_INTEL_CML_GT1_ULX_1,
401 PCI_DID_INTEL_CML_GT2_ULX_1,
402 PCI_DID_INTEL_CML_GT1_S_1,
403 PCI_DID_INTEL_CML_GT1_S_2,
404 PCI_DID_INTEL_CML_GT2_S_1,
405 PCI_DID_INTEL_CML_GT2_S_2,
406 PCI_DID_INTEL_CML_GT1_H_1,
407 PCI_DID_INTEL_CML_GT1_H_2,
408 PCI_DID_INTEL_CML_GT2_H_1,
409 PCI_DID_INTEL_CML_GT2_H_2,
410 PCI_DID_INTEL_CML_GT2_S_G0,
411 PCI_DID_INTEL_CML_GT2_S_P0,
412 PCI_DID_INTEL_CML_GT2_H_R0,
413 PCI_DID_INTEL_CML_GT2_H_R1,
414 PCI_DID_INTEL_TGL_GT0,
415 PCI_DID_INTEL_TGL_GT1_H_32,
416 PCI_DID_INTEL_TGL_GT1_H_16,
417 PCI_DID_INTEL_TGL_GT2_ULT,
418 PCI_DID_INTEL_TGL_GT2_ULX,
419 PCI_DID_INTEL_TGL_GT3_ULT,
420 PCI_DID_INTEL_TGL_GT2_ULT_1,
421 PCI_DID_INTEL_EHL_GT1_1,
422 PCI_DID_INTEL_EHL_GT2_1,
423 PCI_DID_INTEL_EHL_GT1_2,
424 PCI_DID_INTEL_EHL_GT2_2,
425 PCI_DID_INTEL_EHL_GT1_2_1,
426 PCI_DID_INTEL_EHL_GT1_3,
427 PCI_DID_INTEL_EHL_GT2_3,
428 PCI_DID_INTEL_JSL_GT1,
429 PCI_DID_INTEL_JSL_GT2,
430 PCI_DID_INTEL_JSL_GT3,
431 PCI_DID_INTEL_JSL_GT4,
432 PCI_DID_INTEL_ADL_GT0,
433 PCI_DID_INTEL_ADL_GT1,
434 PCI_DID_INTEL_ADL_GT1_1,
435 PCI_DID_INTEL_ADL_GT1_2,
436 PCI_DID_INTEL_ADL_GT1_3,
437 PCI_DID_INTEL_ADL_GT1_4,
438 PCI_DID_INTEL_ADL_GT1_5,
439 PCI_DID_INTEL_ADL_GT1_6,
440 PCI_DID_INTEL_ADL_GT1_7,
441 PCI_DID_INTEL_ADL_GT1_8,
442 PCI_DID_INTEL_ADL_GT1_9,
443 PCI_DID_INTEL_ADL_P_GT2,
444 PCI_DID_INTEL_ADL_P_GT2_1,
445 PCI_DID_INTEL_ADL_P_GT2_2,
446 PCI_DID_INTEL_ADL_P_GT2_3,
447 PCI_DID_INTEL_ADL_P_GT2_4,
448 PCI_DID_INTEL_ADL_P_GT2_5,
449 PCI_DID_INTEL_ADL_P_GT2_6,
450 PCI_DID_INTEL_ADL_P_GT2_7,
451 PCI_DID_INTEL_ADL_P_GT2_8,
452 PCI_DID_INTEL_ADL_P_GT2_9,
453 PCI_DID_INTEL_ADL_S_GT1,
454 PCI_DID_INTEL_ADL_S_GT1_1,
455 PCI_DID_INTEL_ADL_S_GT2,
456 PCI_DID_INTEL_ADL_S_GT2_1,
457 PCI_DID_INTEL_ADL_S_GT2_2,
458 PCI_DID_INTEL_ADL_M_GT1,
459 PCI_DID_INTEL_ADL_M_GT2,
460 PCI_DID_INTEL_ADL_M_GT3,
461 PCI_DID_INTEL_ADL_N_GT1,
462 PCI_DID_INTEL_ADL_N_GT2,
463 PCI_DID_INTEL_ADL_N_GT3,
464 PCI_DID_INTEL_RPL_S_GT0,
465 PCI_DID_INTEL_RPL_S_GT1_1,
466 PCI_DID_INTEL_RPL_S_GT1_2,
467 PCI_DID_INTEL_RPL_S_GT1_3,
468 PCI_DID_INTEL_RPL_HX_GT1,
469 PCI_DID_INTEL_RPL_HX_GT2,
470 PCI_DID_INTEL_RPL_HX_GT3,
471 PCI_DID_INTEL_RPL_HX_GT4,
472 PCI_DID_INTEL_TWL_GT1_1,
473 PCI_DID_INTEL_TWL_GT1_2,
474 0,
475 };
476
477 static const struct pci_driver graphics_driver __pci_driver = {
478 .ops = &graphics_ops,
479 .vendor = PCI_VID_INTEL,
480 .devices = pci_device_ids,
481 };
482