1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <stdint.h>
4 #include <console/console.h>
5 #include <device/mmio.h>
6 #include <device/pci_def.h>
7 #include <device/pci_ops.h>
8
9 #include "haswell.h"
10
11 static bool peg_hidden[3];
12
haswell_setup_bars(void)13 static void haswell_setup_bars(void)
14 {
15 printk(BIOS_DEBUG, "Setting up static northbridge registers...");
16 /* Set up all hardcoded northbridge BARs */
17 pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1);
18 pci_write_config32(HOST_BRIDGE, EPBAR + 4, 0);
19 pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1);
20 pci_write_config32(HOST_BRIDGE, MCHBAR + 4, 0);
21 pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
22 pci_write_config32(HOST_BRIDGE, DMIBAR + 4, 0);
23
24 mchbar_write32(EDRAMBAR, EDRAM_BASE_ADDRESS | 1);
25 mchbar_write32(GDXCBAR, GDXC_BASE_ADDRESS | 1);
26
27 /* Set C0000-FFFFF to access RAM on both reads and writes */
28 pci_write_config8(HOST_BRIDGE, PAM0, 0x30);
29 pci_write_config8(HOST_BRIDGE, PAM1, 0x33);
30 pci_write_config8(HOST_BRIDGE, PAM2, 0x33);
31 pci_write_config8(HOST_BRIDGE, PAM3, 0x33);
32 pci_write_config8(HOST_BRIDGE, PAM4, 0x33);
33 pci_write_config8(HOST_BRIDGE, PAM5, 0x33);
34 pci_write_config8(HOST_BRIDGE, PAM6, 0x33);
35
36 printk(BIOS_DEBUG, " done.\n");
37 }
38
haswell_setup_igd(void)39 static void haswell_setup_igd(void)
40 {
41 bool igd_enabled;
42 u16 ggc;
43
44 printk(BIOS_DEBUG, "Initializing IGD...\n");
45
46 igd_enabled = !!(pci_read_config32(HOST_BRIDGE, DEVEN) & DEVEN_D2EN);
47
48 ggc = pci_read_config16(HOST_BRIDGE, GGC);
49 ggc &= ~0x3f8;
50 if (igd_enabled) {
51 ggc |= GGC_GTT_2MB | GGC_IGD_MEM_IN_32MB_UNITS(1);
52 ggc &= ~GGC_DISABLE_VGA_IO_DECODE;
53 } else {
54 ggc |= GGC_GTT_0MB | GGC_IGD_MEM_IN_32MB_UNITS(0) | GGC_DISABLE_VGA_IO_DECODE;
55 }
56 pci_write_config16(HOST_BRIDGE, GGC, ggc);
57
58 if (!igd_enabled) {
59 printk(BIOS_DEBUG, "IGD is disabled.\n");
60 return;
61 }
62
63 /* Enable 256MB aperture */
64 pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02);
65 }
66
start_peg2_link_training(const pci_devfn_t dev)67 static void start_peg2_link_training(const pci_devfn_t dev)
68 {
69 u32 mask;
70
71 switch (dev) {
72 case PCI_DEV(0, 1, 2):
73 mask = DEVEN_D1F2EN;
74 break;
75 case PCI_DEV(0, 1, 1):
76 mask = DEVEN_D1F1EN;
77 break;
78 case PCI_DEV(0, 1, 0):
79 mask = DEVEN_D1F0EN;
80 break;
81 default:
82 printk(BIOS_ERR, "Link training tried on a non-PEG device!\n");
83 return;
84 }
85
86 pci_update_config32(dev, 0xc24, ~(1 << 16), 1 << 5);
87 printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev)));
88
89 /*
90 * The MRC will perform PCI enumeration, and if it detects a VGA
91 * device in a PEG slot, it will disable the IGD and not reserve
92 * any memory for it. Since the memory map is locked by the time
93 * MRC finishes, the IGD can't be enabled afterwards. Wonderful.
94 *
95 * If one really wants to enable the Intel iGPU as primary, hide
96 * all PEG devices during MRC execution. This will trick the MRC
97 * into thinking there aren't any, and will enable the IGD. Note
98 * that PEG AFE settings will not be programmed, which may cause
99 * stability problems at higher PCIe link speeds. The most ideal
100 * way to fix this problem for good is to implement native init.
101 */
102 if (CONFIG(HASWELL_HIDE_PEG_FROM_MRC)) {
103 pci_update_config32(HOST_BRIDGE, DEVEN, ~mask, 0);
104 peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true;
105 printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n",
106 PCI_FUNC(PCI_DEV2DEVFN(dev)));
107 }
108 }
109
haswell_unhide_peg(void)110 void haswell_unhide_peg(void)
111 {
112 u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
113
114 for (u8 fn = 0; fn <= 2; fn++) {
115 if (peg_hidden[fn]) {
116 deven |= DEVEN_D1F0EN >> fn;
117 peg_hidden[fn] = false;
118 printk(BIOS_DEBUG, "Unhiding PEG1%d.\n", fn);
119 }
120 }
121
122 pci_write_config32(HOST_BRIDGE, DEVEN, deven);
123 }
124
haswell_setup_peg(void)125 static void haswell_setup_peg(void)
126 {
127 u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
128
129 if (deven & DEVEN_D1F2EN)
130 start_peg2_link_training(PCI_DEV(0, 1, 2));
131
132 if (deven & DEVEN_D1F1EN)
133 start_peg2_link_training(PCI_DEV(0, 1, 1));
134
135 if (deven & DEVEN_D1F0EN)
136 start_peg2_link_training(PCI_DEV(0, 1, 0));
137 }
138
haswell_setup_misc(void)139 static void haswell_setup_misc(void)
140 {
141 u32 reg32;
142
143 /* Erratum workarounds */
144 reg32 = mchbar_read32(SAPMCTL);
145 reg32 |= (1 << 9) | (1 << 10);
146 mchbar_write32(SAPMCTL, reg32);
147
148 /* Enable SA Clock Gating */
149 reg32 = mchbar_read32(SAPMCTL);
150 mchbar_write32(SAPMCTL, reg32 | 1);
151
152 reg32 = mchbar_read32(INTRDIRCTL);
153 reg32 |= (1 << 4) | (1 << 5);
154 mchbar_write32(INTRDIRCTL, reg32);
155 }
156
haswell_setup_iommu(void)157 static void haswell_setup_iommu(void)
158 {
159 const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
160
161 if (capid0_a & VTD_DISABLE)
162 return;
163
164 /* Setup BARs: zeroize top 32 bits; set enable bit */
165 mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
166 mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
167 mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
168 mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
169
170 /* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */
171 u32 reg32;
172 reg32 = read32p(GFXVT_BASE_ADDRESS + ARCHDIS);
173 write32p(GFXVT_BASE_ADDRESS + ARCHDIS, reg32 | DMAR_LCKDN | L3HIT2PEND_DIS);
174
175 /* Clear SPCAPCTRL */
176 reg32 = read32p(VTVC0_BASE_ADDRESS + ARCHDIS) & ~SPCAPCTRL;
177
178 /* Set GLBIOTLBINV, GLBCTXTINV; lock VTVC0BAR policy config registers */
179 write32p(VTVC0_BASE_ADDRESS + ARCHDIS,
180 reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV);
181 }
182
haswell_early_initialization(void)183 void haswell_early_initialization(void)
184 {
185 /* Setup all BARs required for early PCIe and raminit */
186 haswell_setup_bars();
187
188 /* Setup IOMMU BARs */
189 haswell_setup_iommu();
190
191 haswell_setup_peg();
192 haswell_setup_igd();
193
194 haswell_setup_misc();
195 }
196