1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 3 #ifndef _INT_GLOBAL_H 4 #define _INT_GLOBAL_H 5 6 #include "dramc_pi_api.h" 7 #include "dramc_int_slt.h" 8 9 /* 10 **************************************************************************************** 11 ** macro 12 **************************************************************************************** 13 */ 14 #define DVT_TEST_DUMMY_RD_SIDEBAND_FROM_SPM 0 15 //#define DVT_TEST_DUMMY_READ_FOR_DQS_GATING_TRACKING 16 //#define DVT_TEST_RX_DLY_HW_TRACKING 17 18 19 /* 20 **************************************************************************************** 21 ** ANA_init_config.c 22 **************************************************************************************** 23 */ 24 EXTERN void ANA_init(DRAMC_CTX_T *p); 25 EXTERN void RESETB_PULL_DN(DRAMC_CTX_T *p); 26 27 28 29 /* 30 **************************************************************************************** 31 ** DIG_NONSHUF_config.c 32 **************************************************************************************** 33 */ 34 EXTERN void DIG_STATIC_SETTING(DRAMC_CTX_T *p); 35 36 37 /* 38 **************************************************************************************** 39 * 40 ** DIG_SHUF_config.c 41 **************************************************************************************** 42 */ 43 EXTERN void DIG_CONFIG_SHUF(DRAMC_CTX_T *p,U32 ch_id, U32 group_id); 44 45 46 /* 47 **************************************************************************************** 48 * 49 ** dramc_debug.c 50 **************************************************************************************** 51 */ 52 EXTERN U8 gFinalCBTVrefDQ[CHANNEL_NUM][RANK_MAX]; 53 EXTERN U8 gFinalRXVrefDQ[CHANNEL_NUM][RANK_MAX][2]; 54 EXTERN U8 gFinalTXVrefDQ[CHANNEL_NUM][RANK_MAX]; 55 56 #ifdef FOR_HQA_REPORT_USED 57 EXTERN U8 gHQALog_flag; 58 EXTERN U16 gHQALOG_RX_delay_cell_ps_075V; 59 EXTERN int hqa_vmddr_class; 60 EXTERN void HQA_Log_Message_for_Report(DRAMC_CTX_T *p, U8 u1ChannelIdx, U8 u1RankIdx, U32 who_am_I, U8 *main_str, U8 *main_str2, U8 byte_bit_idx, S32 value1, U8 *ans_str); 61 #endif 62 63 64 // --- Eye scan variables ----- 65 66 EXTERN U8 gCBT_EYE_Scan_flag; 67 EXTERN U8 gRX_EYE_Scan_flag; 68 EXTERN U8 gTX_EYE_Scan_flag; 69 EXTERN U8 gEye_Scan_color_flag; 70 EXTERN U8 gCBT_EYE_Scan_only_higheset_freq_flag; 71 EXTERN U8 gRX_EYE_Scan_only_higheset_freq_flag; 72 EXTERN U8 gTX_EYE_Scan_only_higheset_freq_flag; 73 EXTERN U8 gEye_Scan_unterm_highest_flag; 74 75 #if ENABLE_EYESCAN_GRAPH 76 #define VREF_TOTAL_NUM_WITH_RANGE (((51 + 30) + 1) / (EYESCAN_GRAPH_CATX_VREF_STEP < EYESCAN_GRAPH_RX_VREF_STEP ? EYESCAN_GRAPH_CATX_VREF_STEP : EYESCAN_GRAPH_RX_VREF_STEP)) //range0 0~50 + range1 21~50 77 #define EYESCAN_BROKEN_NUM 3 78 #define EYESCAN_DATA_INVALID 0x7f 79 EXTERN S16 gEyeScan_Min[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH_LP4][EYESCAN_BROKEN_NUM]; 80 EXTERN S16 gEyeScan_Max[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH_LP4][EYESCAN_BROKEN_NUM]; 81 EXTERN S16 gEyeScan_MinMax_store_delay[DQS_NUMBER]; 82 EXTERN U16 gEyeScan_CaliDelay[DQS_NUMBER]; 83 EXTERN U16 gEyeScan_WinSize[VREF_VOLTAGE_TABLE_NUM_LP5][DQ_DATA_WIDTH_LP4]; 84 EXTERN S16 gEyeScan_DelayCellPI[DQ_DATA_WIDTH_LP4]; 85 EXTERN U16 gEyeScan_ContinueVrefHeight[DQ_DATA_WIDTH_LP4]; 86 EXTERN U16 gEyeScan_TotalPassCount[DQ_DATA_WIDTH_LP4]; 87 EXTERN void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p); 88 EXTERN void print_EYESCAN_LOG_message(DRAMC_CTX_T *p, U8 print_type); 89 #endif 90 #if MRW_CHECK_ONLY || MRW_BACKUP 91 EXTERN U8 gFSPWR_Flag[RANK_MAX]; 92 #endif 93 #ifdef FOR_HQA_TEST_USED 94 EXTERN void HQA_measure_message_reset_all_data(DRAMC_CTX_T *p); 95 #endif 96 #if RUNTIME_SHMOO_RELEATED_FUNCTION && SUPPORT_SAVE_TIME_FOR_CALIBRATION 97 void DramcRunTimeShmooRG_BackupRestore(DRAMC_CTX_T *p); 98 #endif 99 100 101 102 /* 103 **************************************************************************************** 104 ** dramc_dvfs.c 105 **************************************************************************************** 106 */ 107 EXTERN U8 get_shuffleIndex_by_Freq(DRAMC_CTX_T *p); 108 EXTERN void vInitMappingFreqArray(DRAMC_CTX_T *p); 109 EXTERN void vSetDFSTable(DRAMC_CTX_T *p, DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable); 110 EXTERN DRAM_DFS_FREQUENCY_TABLE_T* get_FreqTbl_by_shuffleIndex(DRAMC_CTX_T *p, U8 index); 111 EXTERN void vSetDFSFreqSelByTable(DRAMC_CTX_T *p, DRAM_DFS_FREQUENCY_TABLE_T *pFreqTable); 112 EXTERN void DramcDFSDirectJump(DRAMC_CTX_T *p, U8 shu_level); 113 EXTERN void DramcSaveToShuffleSRAM(DRAMC_CTX_T *p, DRAM_DFS_SHUFFLE_TYPE_T srcRG, DRAM_DFS_SHUFFLE_TYPE_T dstRG); 114 EXTERN void LoadShuffleSRAMtoDramc(DRAMC_CTX_T *p, DRAM_DFS_SHUFFLE_TYPE_T srcRG, DRAM_DFS_SHUFFLE_TYPE_T dstRG); 115 EXTERN void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, U8 shu_level); 116 EXTERN void DVFSSettings(DRAMC_CTX_T *p); 117 EXTERN void DPMEnableTracking(DRAMC_CTX_T *p, U32 u4Reg, U32 u4Field, U8 u1ShuIdx, U8 u1Enable); 118 EXTERN void DPMInit(DRAMC_CTX_T *p); 119 EXTERN void TransferPLLToSPMControl(DRAMC_CTX_T *p, U32 MD32Offset); 120 EXTERN void DramcCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr); 121 EXTERN void DdrphyCopyShu0toShu1(DRAMC_CTX_T *p, U32 u4StartAddr, U32 u4EndAddr); 122 EXTERN void EnableDFSHwModeClk(DRAMC_CTX_T *p); 123 EXTERN void DPHYSaveToSRAMShuWA(DRAMC_CTX_T *p, U8 shu_level); 124 EXTERN void DPHYSRAMShuWAToSHU1(DRAMC_CTX_T *p); 125 EXTERN void SRAMShuRestoreToDPHYWA(DRAMC_CTX_T *p, U8 sram_shu_level, U8 pingpong_shu_level); 126 127 128 /* 129 **************************************************************************************** 130 ** dramc_dv_freq_related.c 131 **************************************************************************************** 132 */ 133 EXTERN void sv_algorithm_assistance_LP4_1600(DRAMC_CTX_T *p); 134 EXTERN void sv_algorithm_assistance_LP4_3733(DRAMC_CTX_T *p); 135 EXTERN void sv_algorithm_assistance_LP4_800(DRAMC_CTX_T *p); 136 EXTERN void CInit_golden_mini_freq_related_vseq_LP4_1600(DRAMC_CTX_T *p); 137 EXTERN void CInit_golden_mini_freq_related_vseq_LP4_4266(DRAMC_CTX_T *p); 138 EXTERN void CInit_golden_mini_freq_related_vseq_LP5_3200(DRAMC_CTX_T *p); 139 EXTERN void CInit_golden_mini_freq_related_vseq_LP5_3200_SHU1(DRAMC_CTX_T *p); 140 EXTERN void CInit_golden_mini_freq_related_vseq_LP5_4266(DRAMC_CTX_T *p); 141 EXTERN void CInit_golden_mini_freq_related_vseq_LP5_5500(DRAMC_CTX_T *p); 142 143 144 /* 145 **************************************************************************************** 146 ** dramc_dv_main.c 147 **************************************************************************************** 148 */ 149 #if (FOR_DV_SIMULATION_USED == 1) 150 EXTERN void DPI_DRAMC_init_entry(); 151 EXTERN void DPI_DRAM_INIT(); 152 #endif 153 154 155 /* 156 **************************************************************************************** 157 ** dramc_pi_basic.c 158 **************************************************************************************** 159 */ 160 EXTERN U8 u1PrintModeRegWrite; 161 EXTERN void vApplyConfigBeforeCalibration(DRAMC_CTX_T *p); 162 EXTERN DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p); 163 EXTERN void SetCKE2RankIndependent(DRAMC_CTX_T *p); 164 EXTERN void DramcDQSPrecalculation_TrackingOff(DRAMC_CTX_T *p, U8 shu_level); 165 EXTERN void DramcDQSPrecalculation_TrackingOn(DRAMC_CTX_T *p, U8 shu_level); 166 EXTERN void DramcHWDQSGatingTracking_ModeSetting(DRAMC_CTX_T *p); 167 EXTERN void Set_MRR_Pinmux_Mapping(DRAMC_CTX_T *p); 168 EXTERN void Set_DQO1_Pinmux_Mapping(DRAMC_CTX_T *p); 169 #if CBT_MOVE_CA_INSTEAD_OF_CLK 170 EXTERN void DramcCmdUIDelaySetting(DRAMC_CTX_T *p, U8 value); 171 #endif 172 EXTERN void cbt_switch_freq(DRAMC_CTX_T *p, U8 freq); 173 EXTERN DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p); 174 EXTERN DRAM_STATUS_T DramcModeRegInit_CATerm(DRAMC_CTX_T *p, U8 bWorkAround); 175 EXTERN void DramcPowerOnSequence(DRAMC_CTX_T *p); 176 EXTERN void Global_Option_Init(DRAMC_CTX_T *p); 177 EXTERN U16 u2DFSGetHighestFreq(DRAMC_CTX_T * p); 178 EXTERN void EnableDRAMModeRegWriteDBIAfterCalibration(DRAMC_CTX_T *p); 179 EXTERN void EnableDRAMModeRegReadDBIAfterCalibration(DRAMC_CTX_T *p); 180 EXTERN void ApplyWriteDBIPowerImprove(DRAMC_CTX_T *p, U8 onoff); 181 EXTERN void DramcHMR4_Presetting(DRAMC_CTX_T *p); 182 EXTERN void DramcEnablePerBankRefresh(DRAMC_CTX_T *p, bool en); 183 EXTERN void RXPICGSetting(DRAMC_CTX_T * p); 184 EXTERN void TXPICGNewModeEnable(DRAMC_CTX_T * p); 185 EXTERN unsigned int DDRPhyFreqMeter(void); 186 #ifndef DPM_CONTROL_AFTERK 187 EXTERN void dramc_exit_with_DFS_legacy_mode(DRAMC_CTX_T * p); 188 #endif 189 190 191 192 /* 193 **************************************************************************************** 194 ** dramc_pi_calibration_api.c 195 **************************************************************************************** 196 */ 197 EXTERN U16 gu2MR0_Value[RANK_MAX]; //read only mode register 198 EXTERN U32 gDramcSwImpedanceResult[IMP_VREF_MAX][IMP_DRV_MAX]; //ODT_ON/OFF x DRVP/DRVN/ODTP/ODTN 199 EXTERN U16 u2g_num_dlycell_perT_all[DRAM_DFS_SHUFFLE_MAX][CHANNEL_NUM]; //TODO: to be removed by Francis 200 EXTERN U16 u2gdelay_cell_ps_all[DRAM_DFS_SHUFFLE_MAX][CHANNEL_NUM]; //TODO: to be removed by Francis 201 EXTERN U16 u2gdelay_cell_ps; 202 EXTERN U8 gCBT_VREF_RANGE_SEL; 203 EXTERN U32 u4gVcore[DRAM_DFS_SHUFFLE_MAX]; 204 EXTERN U8 uiLPDDR4_O1_Mapping_POP[CHANNEL_NUM][16]; 205 EXTERN const U8 uiLPDDR4_O1_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][16]; 206 EXTERN U8 uiLPDDR4_CA_Mapping_POP[CHANNEL_NUM][6]; 207 EXTERN const U8 uiLPDDR4_CA_DRAM_Pinmux[PINMUX_MAX][CHANNEL_NUM][6]; 208 209 #if __ETT__ 210 EXTERN U8 gETT_WHILE_1_flag; 211 #endif 212 213 #ifdef FOR_HQA_REPORT_USED 214 extern U8 gHQALog_flag; 215 extern U16 gHQALOG_RX_delay_cell_ps_075V; 216 #endif 217 218 #ifdef FOR_HQA_TEST_USED 219 EXTERN U16 gFinalCBTVrefCA[CHANNEL_NUM][RANK_MAX]; 220 EXTERN U16 gFinalCBTCA[CHANNEL_NUM][RANK_MAX][10]; 221 EXTERN U16 gFinalRXPerbitWin[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; 222 EXTERN U16 gFinalTXPerbitWin[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH]; 223 EXTERN U16 gFinalTXPerbitWin_min_max[CHANNEL_NUM][RANK_MAX]; 224 EXTERN U16 gFinalTXPerbitWin_min_margin[CHANNEL_NUM][RANK_MAX]; 225 EXTERN U16 gFinalTXPerbitWin_min_margin_bit[CHANNEL_NUM][RANK_MAX]; 226 EXTERN S8 gFinalClkDuty[CHANNEL_NUM]; 227 EXTERN U32 gFinalClkDutyMinMax[CHANNEL_NUM][2]; 228 EXTERN S8 gFinalDQSDuty[CHANNEL_NUM][DQS_NUMBER]; 229 EXTERN U32 gFinalDQSDutyMinMax[CHANNEL_NUM][DQS_NUMBER][2]; 230 #endif 231 EXTERN U8 u1MR01Value[FSP_MAX]; 232 EXTERN U8 u1MR02Value[FSP_MAX]; 233 EXTERN U8 u1MR03Value[FSP_MAX]; 234 EXTERN U8 u1MR11Value[FSP_MAX]; 235 EXTERN U8 u1MR18Value[FSP_MAX]; 236 EXTERN U8 u1MR19Value[FSP_MAX]; 237 EXTERN U8 u1MR20Value[FSP_MAX]; 238 EXTERN U8 u1MR21Value[FSP_MAX]; 239 EXTERN U8 u1MR22Value[FSP_MAX]; 240 EXTERN U8 u1MR51Value[FSP_MAX]; 241 EXTERN U8 u1MR04Value[RANK_MAX]; 242 EXTERN U8 u1MR13Value[RANK_MAX]; 243 EXTERN U8 u1MR26Value[RANK_MAX]; 244 EXTERN U8 u1MR30Value[RANK_MAX]; 245 EXTERN U8 u1MR12Value[CHANNEL_NUM][RANK_MAX][FSP_MAX]; 246 EXTERN U8 u1MR14Value[CHANNEL_NUM][RANK_MAX][FSP_MAX]; 247 #if PINMUX_AUTO_TEST_PER_BIT_RX 248 EXTERN U8 gRX_check_per_bit_flag; 249 EXTERN S16 gFinalRXPerbitFirstPass[CHANNEL_NUM][DQ_DATA_WIDTH]; 250 #endif 251 #if PINMUX_AUTO_TEST_PER_BIT_TX 252 EXTERN U8 gTX_check_per_bit_flag; 253 EXTERN S16 gFinalTXPerbitFirstPass[CHANNEL_NUM][DQ_DATA_WIDTH]; 254 #endif 255 EXTERN U8 u1IsLP4Div4DDR800(DRAMC_CTX_T *p); 256 EXTERN DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 u1VrefScanEnable, u8 isAutoK); 257 EXTERN DRAM_STATUS_T DramcZQCalibration(DRAMC_CTX_T *p, U8 rank); 258 EXTERN DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok); 259 EXTERN DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T stDelayBase); 260 EXTERN DRAM_STATUS_T dramc_rx_dqs_gating_cal(DRAMC_CTX_T *p, u8 autok, U8 use_enhanced_rdqs); 261 EXTERN DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p, RX_PATTERN_OPTION_T eRxPattern, 262 U8 *u1AssignedVref, u8 isAutoK); 263 EXTERN DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p); 264 EXTERN DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p); 265 EXTERN DRAM_STATUS_T DramcSwImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_region); 266 EXTERN void DramcSwImpedanceSaveRegister(DRAMC_CTX_T *p, U8 ca_freq_option, U8 dq_freq_option, U8 save_to_where); 267 EXTERN void vBeforeCalibration(DRAMC_CTX_T *p); 268 EXTERN void vAfterCalibration(DRAMC_CTX_T *p); 269 EXTERN void DramcRunTimeConfig(DRAMC_CTX_T *p); 270 EXTERN DRAM_STATUS_T DramcMiockJmeter(DRAMC_CTX_T *p); 271 EXTERN DRAM_STATUS_T DramcDutyCycleMonitor(DRAMC_CTX_T *p); 272 EXTERN void DramcTxOECalibration(DRAMC_CTX_T *p); 273 EXTERN DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p); 274 EXTERN void LP4_ShiftDQS_OENUI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx); 275 EXTERN void ShiftDQ_OENUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx); 276 EXTERN void DramcMiockJmeterHQA(DRAMC_CTX_T *p); 277 EXTERN U8 u1IsPhaseMode(DRAMC_CTX_T *p); 278 EXTERN void RODTSettings(DRAMC_CTX_T *p); 279 EXTERN void DQSSTBSettings(DRAMC_CTX_T *p); 280 EXTERN void DramcWriteShiftMCKForWriteDBI(DRAMC_CTX_T *p, S8 iShiftMCK); 281 EXTERN void DramPhyReset(DRAMC_CTX_T *p); 282 EXTERN U32 DramcRxWinRDDQCInit(DRAMC_CTX_T *p); 283 EXTERN U32 DramcRxWinRDDQCRun(DRAMC_CTX_T *p); 284 EXTERN U32 DramcRxWinRDDQCEnd(DRAMC_CTX_T *p); 285 #if BYPASS_CALIBRATION 286 EXTERN void dle_factor_handler(DRAMC_CTX_T *p, U8 curr_val); 287 EXTERN void ShiftDQSWCK_UI(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx); 288 EXTERN void ShiftDQUI_AllRK(DRAMC_CTX_T *p, S8 iShiftUI, BYTES_T eByteIdx); 289 EXTERN void TXSetDelayReg_DQ(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdqm_ui_large[], U8 ucdqm_oen_ui_large[], U8 ucdqm_ui_small[], U8 ucdqm_oen_ui_small[], U8 ucdqm_pi[]); 290 EXTERN void TXSetDelayReg_DQM(DRAMC_CTX_T *p, U8 u1UpdateRegUI, U8 ucdqm_ui_large[], U8 ucdqm_oen_ui_large[], U8 ucdqm_ui_small[], U8 ucdqm_oen_ui_small[], U8 ucdqm_pi[]); 291 EXTERN void TXUpdateTXTracking(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T calType, U8 ucdq_pi[], U8 ucdqm_pi[]); 292 EXTERN void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p); 293 EXTERN void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p); 294 #endif 295 EXTERN void vInitGlobalVariablesByCondition(DRAMC_CTX_T *p); 296 EXTERN void DramcDramcRxDVSCalPostProcess(DRAMC_CTX_T *p); 297 EXTERN void CBTDelayCACLK(DRAMC_CTX_T *p, S32 iDelay); 298 #if __FLASH_TOOL_DA__ 299 EXTERN void vPrintPinInfoResult(DRAMC_CTX_T *p); 300 EXTERN DEBUG_PIN_INF_FOR_FLASHTOOL_T PINInfo_flashtool; 301 #endif 302 303 304 /* 305 **************************************************************************************** 306 ** dramc_pi_main.c 307 **************************************************************************************** 308 */ 309 EXTERN DRAMC_CTX_T gTimeProfilingDramCtx; 310 EXTERN U8 gHQA_Test_Freq_Vcore_Level; 311 #if (FOR_DV_SIMULATION_USED == 1) 312 EXTERN U8 gu1BroadcastIsLP4; 313 #endif 314 EXTERN bool gAndroid_DVFS_en; 315 EXTERN bool gUpdateHighestFreq; 316 EXTERN DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SHUFFLE_MAX]; 317 EXTERN void dump_dramc_ctx(DRAMC_CTX_T *p); 318 #ifdef ENABLE_MIOCK_JMETER 319 EXTERN void PRE_MIOCK_JMETER_HQA_USED(DRAMC_CTX_T *p); 320 #endif 321 EXTERN void vCalibration_Flow_For_MDL(DRAMC_CTX_T *p); 322 EXTERN void vDramCalibrationAllChannel(DRAMC_CTX_T *p); 323 EXTERN U32 vGetVoltage(DRAMC_CTX_T *p, U32 get_voltage_type); 324 325 326 /* 327 **************************************************************************************** 328 ** dramc_slt.c 329 **************************************************************************************** 330 */ 331 #if ENABLE_EMI_LPBK_TEST 332 EXTERN U8 gEmiLpbkTest; 333 #endif 334 EXTERN void SLT_DramcDFS(DRAMC_CTX_T *p, int iDoDMA); 335 EXTERN void SLT_DFSTestProgram(DRAMC_CTX_T *p, int iDoDMA); 336 EXTERN void SLT_Test_DFS_and_Memory_Test(DRAMC_CTX_T*p); 337 338 339 340 /* 341 **************************************************************************************** 342 ** dramc_temp_function.c 343 **************************************************************************************** 344 */ 345 EXTERN DRAMC_CTX_T DramCtx_LPDDR4; 346 347 348 /* 349 **************************************************************************************** 350 ** dramc_tracking.c 351 **************************************************************************************** 352 */ 353 EXTERN U8 gu1MR23[CHANNEL_NUM][RANK_MAX]; 354 EXTERN void DramcHWGatingInit(DRAMC_CTX_T *p); 355 EXTERN void DramcHWGatingOnOff(DRAMC_CTX_T *p, U8 u1OnOff); 356 EXTERN void DramcHWGatingDebugOnOff(DRAMC_CTX_T *p, U8 u1OnOff); 357 EXTERN void DramcPrintHWGatingStatus(DRAMC_CTX_T *p, U8 u1Channel); 358 #if (ENABLE_TX_TRACKING || TDQSCK_PRECALCULATION_FOR_DVFS) 359 EXTERN void FreqJumpRatioCalculation(DRAMC_CTX_T *p); 360 #endif 361 #if TDQSCK_PRECALCULATION_FOR_DVFS 362 EXTERN void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p); 363 EXTERN void DramcDQSPrecalculation_enable(DRAMC_CTX_T *p); 364 #endif 365 EXTERN void DramcDQSOSCInit(void); 366 EXTERN DRAM_STATUS_T DramcDQSOSCAuto(DRAMC_CTX_T *p); 367 #if ENABLE_TX_TRACKING 368 EXTERN DRAM_STATUS_T DramcDQSOSCMR23(DRAMC_CTX_T *p); 369 EXTERN DRAM_STATUS_T DramcDQSOSCSetMR18MR19(DRAMC_CTX_T *p); 370 EXTERN DRAM_STATUS_T DramcDQSOSCShuSettings(DRAMC_CTX_T *p); 371 EXTERN void DramcHwDQSOSC(DRAMC_CTX_T *p); 372 EXTERN void Enable_TX_Tracking(DRAMC_CTX_T *p, U32 u4DramcShuOffset); 373 #endif 374 375 #if RDSEL_TRACKING_EN 376 EXTERN void Enable_RDSEL_Tracking(DRAMC_CTX_T *p, U32 u4DramcShuOffset); 377 EXTERN void RDSELRunTimeTracking_preset(DRAMC_CTX_T *p); 378 #endif 379 #ifdef HW_GATING 380 EXTERN void Enable_Gating_Tracking(DRAMC_CTX_T *p, U32 u4DramcShuOffset); 381 #endif 382 EXTERN void DramcImpedanceHWSaving(DRAMC_CTX_T *p); 383 EXTERN void DramcImpedanceTrackingEnable(DRAMC_CTX_T *p); 384 EXTERN void DramcRxInputDelayTrackingInit_Common(DRAMC_CTX_T *p); 385 EXTERN void DramcRxInputDelayTrackingHW(DRAMC_CTX_T *p); 386 EXTERN void DramcRxInputDelayTrackingInit_byFreq(DRAMC_CTX_T *p); 387 388 389 /* 390 **************************************************************************************** 391 ** dramc_utility.c 392 **************************************************************************************** 393 */ 394 EXTERN U16 gddrphyfmeter_value; 395 #if FOR_DV_SIMULATION_USED 396 EXTERN U8 u1BroadcastOnOff; 397 #endif 398 #if (fcFOR_CHIP_ID == fcA60868) 399 EXTERN U8 u1EnterRuntime; 400 #endif 401 EXTERN U8 u1MaType; 402 EXTERN void TA2_Test_Run_Time_HW_Set_Column_Num(DRAMC_CTX_T * p); 403 EXTERN void TA2_Test_Run_Time_HW_Presetting(DRAMC_CTX_T * p, U32 len, TA2_RKSEL_TYPE_T rksel_mode); 404 EXTERN void TA2_Test_Run_Time_Pat_Setting(DRAMC_CTX_T *p, U8 PatSwitch); 405 EXTERN void TA2_Test_Run_Time_HW_Write(DRAMC_CTX_T * p, U8 u1Enable); 406 EXTERN U32 TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p); 407 EXTERN void TA2_Test_Run_Time_HW(DRAMC_CTX_T * p); 408 EXTERN void vAutoRefreshSwitch(DRAMC_CTX_T *p, U8 option); 409 EXTERN void vSetRank(DRAMC_CTX_T *p, U8 ucRank); 410 EXTERN void vSetPHY2ChannelMapping(DRAMC_CTX_T *p, U8 u1Channel); 411 EXTERN VREF_CALIBRATION_ENABLE_T Get_Vref_Calibration_OnOff(DRAMC_CTX_T *p); 412 EXTERN u8 lp5heff_save_disable(DRAMC_CTX_T *p); 413 EXTERN void lp5heff_restore(DRAMC_CTX_T *p); 414 EXTERN u8 is_lp5_family(DRAMC_CTX_T *p); 415 EXTERN U32 GetDramcBroadcast(void); 416 EXTERN void CKEFixOnOff(DRAMC_CTX_T *p, U8 u1RankIdx, CKE_FIX_OPTION option, 417 CKE_FIX_CHANNEL WriteChannelNUM); 418 EXTERN void DramcBackupRegisters(DRAMC_CTX_T *p, U32 *backup_addr, U32 backup_num); 419 EXTERN U8 u1GetRank(DRAMC_CTX_T *p); 420 EXTERN void vPrintCalibrationBasicInfo(DRAMC_CTX_T *p); 421 EXTERN void vPrintCalibrationBasicInfo_ForJV(DRAMC_CTX_T *p); 422 EXTERN U32 DramcEngine2Run(DRAMC_CTX_T *p, DRAM_TE_OP_T wr, U8 testaudpat); 423 EXTERN void DramcEngine2End(DRAMC_CTX_T *p); 424 EXTERN DRAM_STATUS_T DramcEngine2Init(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 u1TestPat, U8 u1LoopCnt, U8 u1EnableUiShift); 425 EXTERN void DramcRestoreRegisters(DRAMC_CTX_T *p, U32 *restore_addr, U32 restore_num); 426 EXTERN DDR800_MODE_T vGet_DDR_Loop_Mode(DRAMC_CTX_T *p); 427 EXTERN u8 is_heff_mode(DRAMC_CTX_T *p); 428 EXTERN void DramcEngine2SetPat(DRAMC_CTX_T *p, U8 u1TestPat, U8 u1LoopCnt, U8 u1Len1Flag, U8 u1EnableUiShift); 429 EXTERN void DramcSetRankEngine2(DRAMC_CTX_T *p, U8 u1RankSel); 430 EXTERN U16 GetFreqBySel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel); 431 EXTERN U8 GetEyeScanEnable(DRAMC_CTX_T * p, U8 get_type); 432 EXTERN U8 vGetPHY2ChannelMapping(DRAMC_CTX_T *p); 433 EXTERN DUTY_CALIBRATION_T Get_Duty_Calibration_Mode(DRAMC_CTX_T *p); 434 EXTERN void DDRPhyFreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel); 435 EXTERN DRAM_DFS_SRAM_SHU_T vGet_Current_ShuLevel(DRAMC_CTX_T *p); 436 EXTERN void vSetChannelNumber(DRAMC_CTX_T *p); 437 EXTERN void vSetRankNumber(DRAMC_CTX_T *p); 438 EXTERN void vSetFSPNumber(DRAMC_CTX_T *p); 439 EXTERN void vCKERankCtrl(DRAMC_CTX_T *p, CKE_CTRL_MODE_T CKECtrlMode); 440 EXTERN DRAM_PLL_FREQ_SEL_T vGet_PLL_FreqSel(DRAMC_CTX_T *p); 441 EXTERN void vSet_PLL_FreqSel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel); 442 EXTERN void Temp_TA2_Test_After_K(DRAMC_CTX_T * p); 443 EXTERN void DramcBroadcastOnOff(U32 bOnOff); 444 EXTERN DIV_MODE_T vGet_Div_Mode(DRAMC_CTX_T *p); 445 EXTERN void DramcMRWriteFldMsk(DRAMC_CTX_T *p, U8 mr_idx, U8 listValue, U8 msk, U8 UpdateMode); 446 EXTERN void DramcMRWriteFldAlign(DRAMC_CTX_T *p, U8 mr_idx, U8 value, U32 mr_fld, U8 UpdateMode); 447 EXTERN void DramcModeRegReadByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U16 *u2pValue); 448 EXTERN void DramcModeRegRead(DRAMC_CTX_T *p, U8 u1MRIdx, U16 *u1pValue); 449 EXTERN void DramcModeRegWriteByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value); 450 EXTERN void SetDramModeRegForWriteDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff); 451 EXTERN void SetDramModeRegForReadDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff); 452 #if MRW_CHECK_ONLY 453 EXTERN void vPrintFinalModeRegisterSetting(DRAMC_CTX_T *p); 454 #endif 455 #if MRW_BACKUP 456 EXTERN U8 DramcMRWriteBackup(DRAMC_CTX_T *p, U8 u1MRIdx, U8 u1Rank); 457 #endif 458 #if QT_GUI_Tool 459 EXTERN void TA2_Test_Run_Time_SW_Presetting(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 testaudpat, U8 log2loopcount); 460 EXTERN U32 TestEngineCompare(DRAMC_CTX_T *p); 461 #endif 462 EXTERN void vSet_Div_Mode(DRAMC_CTX_T *p, DIV_MODE_T eMode); 463 EXTERN void vSet_Current_ShuLevel(DRAMC_CTX_T *p, DRAM_DFS_SRAM_SHU_T u1ShuIndex); 464 EXTERN void GetPhyPllFrequency(DRAMC_CTX_T *p); 465 EXTERN void DramcWriteDBIOnOff(DRAMC_CTX_T *p, U8 onoff); 466 EXTERN void DramcReadDBIOnOff(DRAMC_CTX_T *p, U8 onoff); 467 EXTERN void CheckDramcWBR(U32 u4address); 468 EXTERN void DramcModeRegWriteByRank_RTMRW(DRAMC_CTX_T *p, U8 *u1Rank, U8 *u1MRIdx, U8 *u1Value, U8 u1Len); 469 #if PRINT_CALIBRATION_SUMMARY 470 EXTERN void vPrintCalibrationResult(DRAMC_CTX_T *p); 471 #endif 472 EXTERN int dramc_complex_mem_test (unsigned int start, unsigned int len); 473 EXTERN U16 DDRPhyFMeter(void); 474 #ifdef DDR_INIT_TIME_PROFILING 475 void TimeProfileBegin(void); 476 UINT32 TimeProfileEnd(void); 477 #endif 478 479 480 481 /* 482 **************************************************************************************** 483 ** Hal_IO.cpp 484 **************************************************************************************** 485 */ 486 #ifdef DUMP_INIT_RG_LOG_TO_DE 487 EXTERN U8 gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag; 488 #endif 489 490 491 492 /* 493 **************************************************************************************** 494 ** dramc_utility.cpp 495 **************************************************************************************** 496 */ 497 #if (QT_GUI_Tool == 1) 498 EXTERN MCK_TO_UI_SHIFT_T u1Lp5MCK2WCKUI_DivShift(DRAMC_CTX_T *p); 499 #endif 500 501 502 /* 503 **************************************************************************************** 504 ** dramc_debug.cpp 505 **************************************************************************************** 506 */ 507 extern void HQA_Log_Message_for_Report(DRAMC_CTX_T *p, U8 u1ChannelIdx, U8 u1RankIdx, U32 who_am_I, U8 *main_str, U8 *main_str2, U8 byte_bit_idx, S32 value1, U8 *ans_str); 508 509 510 /* 511 **************************************************************************************** 512 ** dramc_utility_QT.cpp 513 **************************************************************************************** 514 */ 515 #if (QT_GUI_Tool == 1) 516 EXTERN void QT_DRAMCTX_INIT(DRAMC_CTX_T *p); 517 EXTERN DRAM_STATUS_T DramcDDRPHYInit_FPGA_A60868(DRAMC_CTX_T *p); 518 EXTERN DRAM_STATUS_T DramcDDRPHYInit_LP5_FPGA_A60868(DRAMC_CTX_T *p); 519 EXTERN void TA2_Stress_Test(DRAMC_CTX_T *p); 520 EXTERN void TA2_Stress_Test_2(DRAMC_CTX_T *p); 521 EXTERN U32 QT_TestEngineCompare(DRAMC_CTX_T *p); 522 EXTERN void Write_Byte_Counter_Begin(DRAMC_CTX_T *p); 523 EXTERN U32 Write_Byte_Counter_End(DRAMC_CTX_T *p); 524 EXTERN void DDRPhyFMeter_Init(DRAMC_CTX_T *p); 525 EXTERN U32 DDRPhyFreqMeter(void); 526 #endif 527 528 529 /* 530 **************************************************************************************** 531 ** fake_engine.c 532 **************************************************************************************** 533 */ 534 535 536 /* 537 **************************************************************************************** 538 ** low_power_test.c 539 **************************************************************************************** 540 */ 541 EXTERN int global_which_test; 542 EXTERN void EnableDramcPhyDCMShuffle(DRAMC_CTX_T *p, bool bEn, U32 u4DramcShuOffset, U32 u4DDRPhyShuOffset); 543 EXTERN void Enter_Precharge_All(DRAMC_CTX_T *p); 544 EXTERN void EnableDramcPhyDCM(DRAMC_CTX_T *p, bool bEn); 545 EXTERN DRAM_STATUS_T CheckGoldenSetting(DRAMC_CTX_T *p); 546 EXTERN void Low_Power_Scenarios_Test(DRAMC_CTX_T *p); 547 #if ENABLE_DDR800_OPEN_LOOP_MODE_OPTION 548 void DDR800semiPowerSavingOn(DRAMC_CTX_T *p, U8 next_shu_level, U8 u1OnOff); 549 #endif 550 551 #define LOW_POWER_SCENARIO_PRECHARGE_ALL 3 //idle(all bank refresh) 552 #define LOW_POWER_SCENARIO_S1 5 553 #define LOW_POWER_SCENARIO_S0 6 554 #define LOW_POWER_SCENARIO_PASR 7 555 #define LOW_POWER_SCENARIO_ALL 8 556 #define LOW_POWER_SCENARIO_FAKE_ENGINE_READ 9 557 #define LOW_POWER_SCENARIO_FAKE_ENGINE_WRITE 10 558 #define LOW_POWER_SCENARIO_ONLY_SELF_REFRESH 12 559 #define LOW_POWER_SCENARIO_HW_AUTO_SAVE_S0 13 560 #define LOW_POWER_SCENARIO_HW_AUTO_SAVE_S0_METHOD_2 14 561 #define LOW_POWER_SCENARIO_PASR_1BANK 15 562 #define LOW_POWER_SCENARIO_PASR_2BANK 16 563 #define LOW_POWER_SCENARIO_PASR_4BANK 17 564 #define LOW_POWER_SCENARIO_PASR_8BANK 18 565 #define LOW_POWER_SCENARIO_FAKE_ENGINE_BW 19 566 #define LOW_POWER_SCENARIO_FAKE_ENGINE_READ_WRITE 21 567 #define AUTO_REFRESH_RESERVE_TEST 22 568 /* 569 **************************************************************************************** 570 ** low_power_test.c 571 **************************************************************************************** 572 */ 573 EXTERN U8 u1StopMiniStress; 574 EXTERN void Ett_Mini_Strss_Test(DRAMC_CTX_T *p); 575 576 577 /* 578 **************************************************************************************** 579 ** LP4_dram_init.c 580 **************************************************************************************** 581 */ 582 EXTERN void CKE_FIX_ON(DRAMC_CTX_T *p, U8 EN, U8 rank); 583 EXTERN void LP4_UpdateInitialSettings(DRAMC_CTX_T *p); 584 EXTERN void LP4_DRAM_INIT(DRAMC_CTX_T *p); 585 586 587 /* 588 **************************************************************************************** 589 ** LP5_dram_init.c 590 **************************************************************************************** 591 */ 592 EXTERN void LP5_UpdateInitialSettings(DRAMC_CTX_T *p); 593 EXTERN void LP5_DRAM_INIT(DRAMC_CTX_T *p); 594 595 596 /* 597 **************************************************************************************** 598 ** system_init.c 599 **************************************************************************************** 600 */ 601 #if (fcFOR_CHIP_ID == fcA60868) 602 EXTERN void syspll_init(DRAMC_CTX_T *p); 603 #endif 604 605 606 /* 607 **************************************************************************************** 608 ** dramc_utility_QT.cpp 609 **************************************************************************************** 610 */ 611 #if (QT_GUI_Tool == 1) 612 EXTERN U8 ucDramRegRead_1(U32 reg_addr, U32 *reg_data); 613 EXTERN U8 ucDramRegWrite_1(U32 reg_addr, U32 reg_data); 614 #endif 615 616 617 /* 618 **************************************************************************************** 619 ** svsim_dummy.c 620 **************************************************************************************** 621 */ 622 #if (FOR_DV_SIMULATION_USED == 0) 623 #define delay_us(x) 624 #define delay_ns(x) 625 #define mysetscope() 626 #define broadcast_on() 627 #define broadcast_off() 628 #define timestamp_show() 629 #define build_api_initial() 630 #define conf_to_sram_sudo(...) 631 #endif 632 633 /* 634 **************************************************************************************** 635 ** RS232.cpp 636 **************************************************************************************** 637 */ 638 #if (QT_GUI_Tool == 1) 639 EXTERN U8 ucDramSetReg_1(U32 address, U32 *data, U16 count); 640 EXTERN U8 ucDramGetReg_1(U32 address, U32 *data, U16 count); 641 #endif 642 643 644 /* 645 **************************************************************************************** 646 ** ett_test.c 647 **************************************************************************************** 648 */ 649 extern int hqa_vmddr_voltage, hqa_vmddr_class; 650 651 652 #endif //_INT_GLOBAL_H 653