1 /**************************************************************************
2 *
3 * Copyright 2008 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include "compiler/nir/nir.h"
29 #include "draw/draw_context.h"
30 #include "nir/nir_to_tgsi.h"
31 #include "util/format/u_format.h"
32 #include "util/format/u_format_s3tc.h"
33 #include "util/os_misc.h"
34 #include "util/u_inlines.h"
35 #include "util/u_memory.h"
36 #include "util/u_screen.h"
37 #include "util/u_string.h"
38
39 #include "i915_context.h"
40 #include "i915_debug.h"
41 #include "i915_fpc.h"
42 #include "i915_public.h"
43 #include "i915_reg.h"
44 #include "i915_resource.h"
45 #include "i915_screen.h"
46 #include "i915_winsys.h"
47
48 /*
49 * Probe functions
50 */
51
52 static const char *
i915_get_vendor(struct pipe_screen * screen)53 i915_get_vendor(struct pipe_screen *screen)
54 {
55 return "Mesa Project";
56 }
57
58 static const char *
i915_get_device_vendor(struct pipe_screen * screen)59 i915_get_device_vendor(struct pipe_screen *screen)
60 {
61 return "Intel";
62 }
63
64 static const char *
i915_get_name(struct pipe_screen * screen)65 i915_get_name(struct pipe_screen *screen)
66 {
67 static char buffer[128];
68 const char *chipset;
69
70 switch (i915_screen(screen)->iws->pci_id) {
71 case PCI_CHIP_I915_G:
72 chipset = "915G";
73 break;
74 case PCI_CHIP_I915_GM:
75 chipset = "915GM";
76 break;
77 case PCI_CHIP_I945_G:
78 chipset = "945G";
79 break;
80 case PCI_CHIP_I945_GM:
81 chipset = "945GM";
82 break;
83 case PCI_CHIP_I945_GME:
84 chipset = "945GME";
85 break;
86 case PCI_CHIP_G33_G:
87 chipset = "G33";
88 break;
89 case PCI_CHIP_Q35_G:
90 chipset = "Q35";
91 break;
92 case PCI_CHIP_Q33_G:
93 chipset = "Q33";
94 break;
95 case PCI_CHIP_PINEVIEW_G:
96 chipset = "Pineview G";
97 break;
98 case PCI_CHIP_PINEVIEW_M:
99 chipset = "Pineview M";
100 break;
101 default:
102 chipset = "unknown";
103 break;
104 }
105
106 snprintf(buffer, sizeof(buffer), "i915 (chipset: %s)", chipset);
107 return buffer;
108 }
109
110 static const nir_shader_compiler_options i915_compiler_options = {
111 .fdot_replicates = true,
112 .fuse_ffma32 = true,
113 .lower_bitops = true, /* required for !CAP_INTEGERS nir_to_tgsi */
114 .lower_extract_byte = true,
115 .lower_extract_word = true,
116 .lower_fdiv = true,
117 .lower_fdph = true,
118 .lower_flrp32 = true,
119 .lower_fmod = true,
120 .lower_sincos = true,
121 .lower_uniforms_to_ubo = true,
122 .lower_vector_cmp = true,
123 .force_indirect_unrolling = nir_var_all,
124 .force_indirect_unrolling_sampler = true,
125 .max_unroll_iterations = 32,
126 .no_integers = true,
127 .has_fused_comp_and_csel = true,
128 };
129
130 static const struct nir_shader_compiler_options gallivm_nir_options = {
131 .fdot_replicates = true,
132 .lower_bitops = true, /* required for !CAP_INTEGERS nir_to_tgsi */
133 .lower_scmp = true,
134 .lower_flrp32 = true,
135 .lower_flrp64 = true,
136 .lower_fsat = true,
137 .lower_bitfield_insert = true,
138 .lower_bitfield_extract = true,
139 .lower_fdph = true,
140 .lower_ffma16 = true,
141 .lower_ffma32 = true,
142 .lower_ffma64 = true,
143 .lower_fmod = true,
144 .lower_hadd = true,
145 .lower_uadd_sat = true,
146 .lower_usub_sat = true,
147 .lower_iadd_sat = true,
148 .lower_ldexp = true,
149 .lower_pack_snorm_2x16 = true,
150 .lower_pack_snorm_4x8 = true,
151 .lower_pack_unorm_2x16 = true,
152 .lower_pack_unorm_4x8 = true,
153 .lower_pack_half_2x16 = true,
154 .lower_pack_split = true,
155 .lower_unpack_snorm_2x16 = true,
156 .lower_unpack_snorm_4x8 = true,
157 .lower_unpack_unorm_2x16 = true,
158 .lower_unpack_unorm_4x8 = true,
159 .lower_unpack_half_2x16 = true,
160 .lower_extract_byte = true,
161 .lower_extract_word = true,
162 .lower_uadd_carry = true,
163 .lower_usub_borrow = true,
164 .lower_mul_2x32_64 = true,
165 .lower_ifind_msb = true,
166 .max_unroll_iterations = 32,
167 .lower_cs_local_index_to_id = true,
168 .lower_uniforms_to_ubo = true,
169 .lower_vector_cmp = true,
170 .lower_device_index_to_zero = true,
171 /* .support_16bit_alu = true, */
172 .support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
173 .support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
174 .has_ddx_intrinsics = true,
175 .no_integers = true,
176 };
177
178 static const void *
i915_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)179 i915_get_compiler_options(struct pipe_screen *pscreen, enum pipe_shader_ir ir,
180 enum pipe_shader_type shader)
181 {
182 assert(ir == PIPE_SHADER_IR_NIR);
183 if (shader == PIPE_SHADER_FRAGMENT)
184 return &i915_compiler_options;
185 else
186 return &gallivm_nir_options;
187 }
188
189 static void
i915_optimize_nir(struct nir_shader * s)190 i915_optimize_nir(struct nir_shader *s)
191 {
192 bool progress;
193
194 do {
195 progress = false;
196
197 NIR_PASS_V(s, nir_lower_vars_to_ssa);
198
199 NIR_PASS(progress, s, nir_copy_prop);
200 NIR_PASS(progress, s, nir_opt_algebraic);
201 NIR_PASS(progress, s, nir_opt_constant_folding);
202 NIR_PASS(progress, s, nir_opt_remove_phis);
203 NIR_PASS(progress, s, nir_opt_conditional_discard);
204 NIR_PASS(progress, s, nir_opt_dce);
205 NIR_PASS(progress, s, nir_opt_dead_cf);
206 NIR_PASS(progress, s, nir_opt_cse);
207 NIR_PASS(progress, s, nir_opt_find_array_copies);
208 NIR_PASS(progress, s, nir_opt_if, nir_opt_if_optimize_phi_true_false);
209 NIR_PASS(progress, s, nir_opt_peephole_select, ~0 /* flatten all IFs. */,
210 true, true);
211 NIR_PASS(progress, s, nir_opt_algebraic);
212 NIR_PASS(progress, s, nir_opt_constant_folding);
213 NIR_PASS(progress, s, nir_opt_shrink_stores, true);
214 NIR_PASS(progress, s, nir_opt_shrink_vectors, false);
215 NIR_PASS(progress, s, nir_opt_loop);
216 NIR_PASS(progress, s, nir_opt_undef);
217 NIR_PASS(progress, s, nir_opt_loop_unroll);
218
219 } while (progress);
220
221 NIR_PASS(progress, s, nir_remove_dead_variables, nir_var_function_temp,
222 NULL);
223
224 /* Group texture loads together to try to avoid hitting the
225 * texture indirection phase limit.
226 */
227 NIR_PASS_V(s, nir_group_loads, nir_group_all, ~0);
228 }
229
230 static char *
i915_check_control_flow(nir_shader * s)231 i915_check_control_flow(nir_shader *s)
232 {
233 if (s->info.stage == MESA_SHADER_FRAGMENT) {
234 nir_function_impl *impl = nir_shader_get_entrypoint(s);
235 nir_block *first = nir_start_block(impl);
236 nir_cf_node *next = nir_cf_node_next(&first->cf_node);
237
238 if (next) {
239 switch (next->type) {
240 case nir_cf_node_if:
241 return "if/then statements not supported by i915 fragment shaders, "
242 "should have been flattened by peephole_select.";
243 case nir_cf_node_loop:
244 return "looping not supported i915 fragment shaders, all loops "
245 "must be statically unrollable.";
246 default:
247 return "Unknown control flow type";
248 }
249 }
250 }
251
252 return NULL;
253 }
254
255 static char *
i915_finalize_nir(struct pipe_screen * pscreen,struct nir_shader * s)256 i915_finalize_nir(struct pipe_screen *pscreen, struct nir_shader *s)
257 {
258 if (s->info.stage == MESA_SHADER_FRAGMENT)
259 i915_optimize_nir(s);
260
261 /* st_program.c's parameter list optimization requires that future nir
262 * variants don't reallocate the uniform storage, so we have to remove
263 * uniforms that occupy storage. But we don't want to remove samplers,
264 * because they're needed for YUV variant lowering.
265 */
266 nir_remove_dead_derefs(s);
267 nir_foreach_uniform_variable_safe (var, s) {
268 if (var->data.mode == nir_var_uniform &&
269 (glsl_type_get_image_count(var->type) ||
270 glsl_type_get_sampler_count(var->type)))
271 continue;
272
273 exec_node_remove(&var->node);
274 }
275 nir_validate_shader(s, "after uniform var removal");
276
277 nir_sweep(s);
278
279 char *msg = i915_check_control_flow(s);
280 if (msg) {
281 if (I915_DBG_ON(DBG_FS) && (!s->info.internal || NIR_DEBUG(PRINT_INTERNAL))) {
282 mesa_logi("failing shader:");
283 nir_log_shaderi(s);
284 }
285 return strdup(msg);
286 }
287
288 if (s->info.stage == MESA_SHADER_FRAGMENT)
289 return i915_test_fragment_shader_compile(pscreen, s);
290 else
291 return NULL;
292 }
293
294 static int
i915_get_shader_param(struct pipe_screen * screen,enum pipe_shader_type shader,enum pipe_shader_cap cap)295 i915_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
296 enum pipe_shader_cap cap)
297 {
298 switch (cap) {
299 case PIPE_SHADER_CAP_SUPPORTED_IRS:
300 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
301
302 case PIPE_SHADER_CAP_INTEGERS:
303 /* mesa/st requires that this cap is the same across stages, and the FS
304 * can't do ints.
305 */
306 return 0;
307
308 /* i915 can't do these, and even if gallivm NIR can we call nir_to_tgsi
309 * manually and TGSI can't.
310 */
311 case PIPE_SHADER_CAP_INT16:
312 case PIPE_SHADER_CAP_FP16:
313 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
314 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
315 return 0;
316
317 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
318 /* While draw could normally handle this for the VS, the NIR lowering
319 * to regs can't handle our non-native-integers, so we have to lower to
320 * if ladders.
321 */
322 return 0;
323
324 default:
325 break;
326 }
327
328 switch (shader) {
329 case PIPE_SHADER_VERTEX:
330 switch (cap) {
331 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
332 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
333 return 0;
334 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
335 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
336 return 0;
337 default:
338 return draw_get_shader_param(shader, cap);
339 }
340 case PIPE_SHADER_FRAGMENT:
341 /* XXX: some of these are just shader model 2.0 values, fix this! */
342 switch (cap) {
343 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
344 return I915_MAX_ALU_INSN + I915_MAX_TEX_INSN;
345 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
346 return I915_MAX_ALU_INSN;
347 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
348 return I915_MAX_TEX_INSN;
349 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
350 return 4;
351 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
352 return 0;
353 case PIPE_SHADER_CAP_MAX_INPUTS:
354 return 10;
355 case PIPE_SHADER_CAP_MAX_OUTPUTS:
356 return 1;
357 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
358 return 32 * sizeof(float[4]);
359 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
360 return 1;
361 case PIPE_SHADER_CAP_MAX_TEMPS:
362 /* 16 inter-phase temps, 3 intra-phase temps. i915c reported 16. too. */
363 return 16;
364 case PIPE_SHADER_CAP_CONT_SUPPORTED:
365 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
366 return 0;
367 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
368 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
369 case PIPE_SHADER_CAP_SUBROUTINES:
370 return 0;
371 case PIPE_SHADER_CAP_INT64_ATOMICS:
372 case PIPE_SHADER_CAP_INT16:
373 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
374 return 0;
375 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
376 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
377 return I915_TEX_UNITS;
378 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
379 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
380 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
381 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
382 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
383 return 0;
384
385 default:
386 debug_printf("%s: Unknown cap %u.\n", __func__, cap);
387 return 0;
388 }
389 break;
390 default:
391 return 0;
392 }
393 }
394
395 static void
i915_init_screen_caps(struct i915_screen * is)396 i915_init_screen_caps(struct i915_screen *is)
397 {
398 struct pipe_caps *caps = (struct pipe_caps *)&is->base.caps;
399
400 u_init_pipe_screen_caps(&is->base, 1);
401
402 /* Supported features (boolean caps). */
403 caps->anisotropic_filter = true;
404 caps->npot_textures = true;
405 caps->mixed_framebuffer_sizes = true;
406 caps->primitive_restart = true; /* draw module */
407 caps->primitive_restart_fixed_index = true;
408 caps->vertex_element_instance_divisor = true;
409 caps->blend_equation_separate = true;
410 caps->vs_instanceid = true;
411 caps->vertex_color_clamped = true;
412 caps->user_vertex_buffers = true;
413 caps->mixed_color_depth_bits = true;
414 caps->tgsi_texcoord = true;
415 caps->call_finalize_nir_in_linker = true;
416
417 caps->texture_transfer_modes =
418 caps->pci_group =
419 caps->pci_bus =
420 caps->pci_device =
421 caps->pci_function = 0;
422
423 caps->allow_mapped_buffers_during_execution = false;
424
425 /* Can't expose shareable shaders because the draw shaders reference the
426 * draw module's state, which is per-context.
427 */
428 caps->shareable_shaders = false;
429
430 caps->max_gs_invocations = 32;
431
432 caps->max_shader_buffer_size = 1 << 27;
433
434 caps->max_viewports = 1;
435
436 caps->min_map_buffer_alignment = 64;
437
438 caps->glsl_feature_level =
439 caps->glsl_feature_level_compatibility = 120;
440
441 caps->constant_buffer_offset_alignment = 16;
442
443 /* Texturing. */
444 caps->max_texture_2d_size = 1 << (I915_MAX_TEXTURE_2D_LEVELS - 1);
445 caps->max_texture_3d_levels = I915_MAX_TEXTURE_3D_LEVELS;
446 caps->max_texture_cube_levels = I915_MAX_TEXTURE_2D_LEVELS;
447
448 /* Render targets. */
449 caps->max_render_targets = 1;
450
451 caps->max_vertex_attrib_stride = 2048;
452
453 /* Fragment coordinate conventions. */
454 caps->fs_coord_origin_upper_left =
455 caps->fs_coord_pixel_center_half_integer = true;
456 caps->endianness = PIPE_ENDIAN_LITTLE;
457 caps->max_varyings = 10;
458
459 caps->nir_images_as_deref = false;
460
461 caps->vendor_id = 0x8086;
462 caps->device_id = is->iws->pci_id;
463
464 /* Once a batch uses more than 75% of the maximum mappable size, we
465 * assume that there's some fragmentation, and we start doing extra
466 * flushing, etc. That's the big cliff apps will care about.
467 */
468 const int gpu_mappable_megabytes = is->iws->aperture_size(is->iws) * 3 / 4;
469 uint64_t system_memory;
470 caps->video_memory =
471 os_get_total_physical_memory(&system_memory) ?
472 MIN2(gpu_mappable_megabytes, (int)(system_memory >> 20)) : 0;
473 caps->uma = true;
474
475 caps->min_line_width =
476 caps->min_line_width_aa =
477 caps->min_point_size =
478 caps->min_point_size_aa = 1;
479
480 caps->point_size_granularity =
481 caps->line_width_granularity = 0.1;
482
483 caps->max_line_width =
484 caps->max_line_width_aa = 7.5;
485
486 caps->max_point_size =
487 caps->max_point_size_aa = 255.0;
488
489 caps->max_texture_anisotropy = 4.0;
490
491 caps->max_texture_lod_bias = 16.0;
492 }
493
494 bool
i915_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned tex_usage)495 i915_is_format_supported(struct pipe_screen *screen, enum pipe_format format,
496 enum pipe_texture_target target, unsigned sample_count,
497 unsigned storage_sample_count, unsigned tex_usage)
498 {
499 static const enum pipe_format tex_supported[] = {
500 PIPE_FORMAT_B8G8R8A8_UNORM, PIPE_FORMAT_B8G8R8A8_SRGB,
501 PIPE_FORMAT_B8G8R8X8_UNORM, PIPE_FORMAT_R8G8B8A8_UNORM,
502 PIPE_FORMAT_R8G8B8X8_UNORM, PIPE_FORMAT_B4G4R4A4_UNORM,
503 PIPE_FORMAT_B5G6R5_UNORM, PIPE_FORMAT_B5G5R5A1_UNORM,
504 PIPE_FORMAT_B10G10R10A2_UNORM, PIPE_FORMAT_L8_UNORM, PIPE_FORMAT_A8_UNORM,
505 PIPE_FORMAT_I8_UNORM, PIPE_FORMAT_L8A8_UNORM, PIPE_FORMAT_UYVY,
506 PIPE_FORMAT_YUYV,
507 /* XXX why not?
508 PIPE_FORMAT_Z16_UNORM, */
509 PIPE_FORMAT_DXT1_RGB, PIPE_FORMAT_DXT1_SRGB, PIPE_FORMAT_DXT1_RGBA,
510 PIPE_FORMAT_DXT1_SRGBA, PIPE_FORMAT_DXT3_RGBA, PIPE_FORMAT_DXT3_SRGBA,
511 PIPE_FORMAT_DXT5_RGBA, PIPE_FORMAT_DXT5_SRGBA, PIPE_FORMAT_Z24X8_UNORM,
512 PIPE_FORMAT_FXT1_RGB, PIPE_FORMAT_FXT1_RGBA,
513 PIPE_FORMAT_Z24_UNORM_S8_UINT, PIPE_FORMAT_NONE /* list terminator */
514 };
515 static const enum pipe_format render_supported[] = {
516 PIPE_FORMAT_B8G8R8A8_UNORM, PIPE_FORMAT_B8G8R8X8_UNORM,
517 PIPE_FORMAT_R8G8B8A8_UNORM, PIPE_FORMAT_R8G8B8X8_UNORM,
518 PIPE_FORMAT_B5G6R5_UNORM, PIPE_FORMAT_B5G5R5A1_UNORM,
519 PIPE_FORMAT_B4G4R4A4_UNORM, PIPE_FORMAT_B10G10R10A2_UNORM,
520 PIPE_FORMAT_L8_UNORM, PIPE_FORMAT_A8_UNORM,
521 PIPE_FORMAT_I8_UNORM, PIPE_FORMAT_NONE /* list terminator */
522 };
523 static const enum pipe_format depth_supported[] = {
524 /* XXX why not?
525 PIPE_FORMAT_Z16_UNORM, */
526 PIPE_FORMAT_Z24X8_UNORM, PIPE_FORMAT_Z24_UNORM_S8_UINT,
527 PIPE_FORMAT_NONE /* list terminator */
528 };
529 const enum pipe_format *list;
530 uint32_t i;
531
532 if (sample_count > 1)
533 return false;
534
535 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
536 return false;
537
538 if (tex_usage & PIPE_BIND_DEPTH_STENCIL)
539 list = depth_supported;
540 else if (tex_usage & PIPE_BIND_RENDER_TARGET)
541 list = render_supported;
542 else if (tex_usage & PIPE_BIND_SAMPLER_VIEW)
543 list = tex_supported;
544 else
545 return true; /* PIPE_BIND_{VERTEX,INDEX}_BUFFER */
546
547 for (i = 0; list[i] != PIPE_FORMAT_NONE; i++) {
548 if (list[i] == format)
549 return true;
550 }
551
552 return false;
553 }
554
555 /*
556 * Fence functions
557 */
558
559 static void
i915_fence_reference(struct pipe_screen * screen,struct pipe_fence_handle ** ptr,struct pipe_fence_handle * fence)560 i915_fence_reference(struct pipe_screen *screen, struct pipe_fence_handle **ptr,
561 struct pipe_fence_handle *fence)
562 {
563 struct i915_screen *is = i915_screen(screen);
564
565 is->iws->fence_reference(is->iws, ptr, fence);
566 }
567
568 static bool
i915_fence_finish(struct pipe_screen * screen,struct pipe_context * ctx,struct pipe_fence_handle * fence,uint64_t timeout)569 i915_fence_finish(struct pipe_screen *screen, struct pipe_context *ctx,
570 struct pipe_fence_handle *fence, uint64_t timeout)
571 {
572 struct i915_screen *is = i915_screen(screen);
573
574 if (!timeout)
575 return is->iws->fence_signalled(is->iws, fence) == 1;
576
577 return is->iws->fence_finish(is->iws, fence) == 1;
578 }
579
580 /*
581 * Generic functions
582 */
583
584 static void
i915_destroy_screen(struct pipe_screen * screen)585 i915_destroy_screen(struct pipe_screen *screen)
586 {
587 struct i915_screen *is = i915_screen(screen);
588
589 if (is->iws)
590 is->iws->destroy(is->iws);
591
592 FREE(is);
593 }
594
595 static int
i915_screen_get_fd(struct pipe_screen * screen)596 i915_screen_get_fd(struct pipe_screen *screen)
597 {
598 struct i915_screen *is = i915_screen(screen);
599
600 return is->iws->get_fd(is->iws);
601 }
602
603 /**
604 * Create a new i915_screen object
605 */
606 struct pipe_screen *
i915_screen_create(struct i915_winsys * iws)607 i915_screen_create(struct i915_winsys *iws)
608 {
609 struct i915_screen *is = CALLOC_STRUCT(i915_screen);
610
611 if (!is)
612 return NULL;
613
614 switch (iws->pci_id) {
615 case PCI_CHIP_I915_G:
616 case PCI_CHIP_I915_GM:
617 is->is_i945 = false;
618 break;
619
620 case PCI_CHIP_I945_G:
621 case PCI_CHIP_I945_GM:
622 case PCI_CHIP_I945_GME:
623 case PCI_CHIP_G33_G:
624 case PCI_CHIP_Q33_G:
625 case PCI_CHIP_Q35_G:
626 case PCI_CHIP_PINEVIEW_G:
627 case PCI_CHIP_PINEVIEW_M:
628 is->is_i945 = true;
629 break;
630
631 default:
632 debug_printf("%s: unknown pci id 0x%x, cannot create screen\n", __func__,
633 iws->pci_id);
634 FREE(is);
635 return NULL;
636 }
637
638 is->iws = iws;
639
640 is->base.destroy = i915_destroy_screen;
641
642 is->base.get_name = i915_get_name;
643 is->base.get_vendor = i915_get_vendor;
644 is->base.get_device_vendor = i915_get_device_vendor;
645 is->base.get_screen_fd = i915_screen_get_fd;
646 is->base.get_shader_param = i915_get_shader_param;
647 is->base.get_compiler_options = i915_get_compiler_options;
648 is->base.finalize_nir = i915_finalize_nir;
649 is->base.is_format_supported = i915_is_format_supported;
650
651 is->base.context_create = i915_create_context;
652
653 is->base.fence_reference = i915_fence_reference;
654 is->base.fence_finish = i915_fence_finish;
655
656 i915_init_screen_resource_functions(is);
657
658 i915_init_screen_caps(is);
659
660 i915_debug_init(is);
661
662 return &is->base;
663 }
664