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Searched defs:instr (Results 1 – 25 of 48) sorted by relevance

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/art/compiler/optimizing/
Dscheduler_arm64.cc135 void SchedulingLatencyVisitorARM64::VisitBinaryOperation(HBinaryOperation* instr) { in VisitBinaryOperation()
159 [[maybe_unused]] HIntermediateAddressIndex* instr) { in VisitIntermediateAddressIndex()
191 void SchedulingLatencyVisitorARM64::VisitDiv(HDiv* instr) { in VisitDiv()
244 void SchedulingLatencyVisitorARM64::VisitMul(HMul* instr) { in VisitMul()
305 void SchedulingLatencyVisitorARM64::VisitTypeConversion(HTypeConversion* instr) { in VisitTypeConversion()
314 void SchedulingLatencyVisitorARM64::HandleSimpleArithmeticSIMD(HVecOperation *instr) { in HandleSimpleArithmeticSIMD()
323 [[maybe_unused]] HVecReplicateScalar* instr) { in VisitVecReplicateScalar()
327 void SchedulingLatencyVisitorARM64::VisitVecExtractScalar(HVecExtractScalar* instr) { in VisitVecExtractScalar()
331 void SchedulingLatencyVisitorARM64::VisitVecReduce(HVecReduce* instr) { in VisitVecReduce()
335 void SchedulingLatencyVisitorARM64::VisitVecCnv([[maybe_unused]] HVecCnv* instr) { in VisitVecCnv()
[all …]
Dcommon_arm.h89 inline vixl::aarch32::SRegister OutputSRegister(HInstruction* instr) { in OutputSRegister()
95 inline vixl::aarch32::DRegister OutputDRegister(HInstruction* instr) { in OutputDRegister()
101 inline vixl::aarch32::VRegister OutputVRegister(HInstruction* instr) { in OutputVRegister()
110 inline vixl::aarch32::SRegister InputSRegisterAt(HInstruction* instr, int input_index) { in InputSRegisterAt()
116 inline vixl::aarch32::DRegister InputDRegisterAt(HInstruction* instr, int input_index) { in InputDRegisterAt()
122 inline vixl::aarch32::VRegister InputVRegisterAt(HInstruction* instr, int input_index) { in InputVRegisterAt()
132 inline vixl::aarch32::VRegister InputVRegister(HInstruction* instr) { in InputVRegister()
137 inline vixl::aarch32::Register OutputRegister(HInstruction* instr) { in OutputRegister()
141 inline vixl::aarch32::Register InputRegisterAt(HInstruction* instr, int input_index) { in InputRegisterAt()
146 inline vixl::aarch32::Register InputRegister(HInstruction* instr) { in InputRegister()
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Dreference_type_propagation.cc485 void ReferenceTypePropagation::RTPVisitor::SetClassAsTypeInfo(HInstruction* instr, in SetClassAsTypeInfo()
521 void ReferenceTypePropagation::RTPVisitor::VisitDeoptimize(HDeoptimize* instr) { in VisitDeoptimize()
525 void ReferenceTypePropagation::RTPVisitor::UpdateReferenceTypeInfo(HInstruction* instr, in UpdateReferenceTypeInfo()
543 void ReferenceTypePropagation::RTPVisitor::VisitNewInstance(HNewInstance* instr) { in VisitNewInstance()
548 void ReferenceTypePropagation::RTPVisitor::VisitNewArray(HNewArray* instr) { in VisitNewArray()
553 void ReferenceTypePropagation::RTPVisitor::VisitParameterValue(HParameterValue* instr) { in VisitParameterValue()
563 void ReferenceTypePropagation::RTPVisitor::UpdateFieldAccessTypeInfo(HInstruction* instr, in UpdateFieldAccessTypeInfo()
580 void ReferenceTypePropagation::RTPVisitor::VisitInstanceFieldGet(HInstanceFieldGet* instr) { in VisitInstanceFieldGet()
584 void ReferenceTypePropagation::RTPVisitor::VisitStaticFieldGet(HStaticFieldGet* instr) { in VisitStaticFieldGet()
589 HUnresolvedInstanceFieldGet* instr) { in VisitUnresolvedInstanceFieldGet()
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Dcommon_arm64.h83 inline vixl::aarch64::Register OutputRegister(HInstruction* instr) { in OutputRegister()
87 inline vixl::aarch64::Register InputRegisterAt(HInstruction* instr, int input_index) { in InputRegisterAt()
127 inline vixl::aarch64::VRegister OutputFPRegister(HInstruction* instr) { in OutputFPRegister()
131 inline vixl::aarch64::VRegister InputFPRegisterAt(HInstruction* instr, int input_index) { in InputFPRegisterAt()
142 inline vixl::aarch64::CPURegister OutputCPURegister(HInstruction* instr) { in OutputCPURegister()
148 inline vixl::aarch64::CPURegister InputCPURegisterAt(HInstruction* instr, int index) { in InputCPURegisterAt()
154 inline vixl::aarch64::CPURegister InputCPURegisterOrZeroRegAt(HInstruction* instr, in InputCPURegisterOrZeroRegAt()
178 inline vixl::aarch64::Operand InputOperandAt(HInstruction* instr, int input_index) { in InputOperandAt()
256 inline bool Arm64CanEncodeConstantAsImmediate(HConstant* constant, HInstruction* instr) { in Arm64CanEncodeConstantAsImmediate()
315 inline Location ARM64EncodableConstantOrRegister(HInstruction* constant, HInstruction* instr) { in ARM64EncodableConstantOrRegister()
Dscheduler_arm.cc143 void SchedulingLatencyVisitorARM::HandleBinaryOperationLantencies(HBinaryOperation* instr) { in HandleBinaryOperationLantencies()
162 void SchedulingLatencyVisitorARM::VisitAdd(HAdd* instr) { in VisitAdd()
166 void SchedulingLatencyVisitorARM::VisitSub(HSub* instr) { in VisitSub()
170 void SchedulingLatencyVisitorARM::VisitMul(HMul* instr) { in VisitMul()
186 void SchedulingLatencyVisitorARM::HandleBitwiseOperationLantencies(HBinaryOperation* instr) { in HandleBitwiseOperationLantencies()
202 void SchedulingLatencyVisitorARM::VisitAnd(HAnd* instr) { in VisitAnd()
206 void SchedulingLatencyVisitorARM::VisitOr(HOr* instr) { in VisitOr()
210 void SchedulingLatencyVisitorARM::VisitXor(HXor* instr) { in VisitXor()
214 void SchedulingLatencyVisitorARM::VisitRor(HRor* instr) { in VisitRor()
243 void SchedulingLatencyVisitorARM::HandleShiftLatencies(HBinaryOperation* instr) { in HandleShiftLatencies()
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Dcontrol_flow_simplifier_test.cc30 HPhi* ConstructBasicGraphForSelect(HBasicBlock* return_block, HInstruction* instr) { in ConstructBasicGraphForSelect()
55 HDivZeroCheck* instr = new (GetAllocator()) HDivZeroCheck(param, 0); in TEST_F() local
68 HAdd* instr = new (GetAllocator()) HAdd(DataType::Type::kInt32, param, param, /*dex_pc=*/ 0); in TEST_F() local
Dscheduler_arm64.h40 bool IsSchedulingBarrier(const HInstruction* instr) const override { in IsSchedulingBarrier()
Dcode_generator_utils.cc243 bool HasNonNegativeInputAt(HInstruction* instr, size_t i) { in HasNonNegativeInputAt()
248 bool HasNonNegativeOrMinIntInputAt(HInstruction* instr, size_t i) { in HasNonNegativeOrMinIntInputAt()
Dinstruction_simplifier_shared.h44 inline bool HasShifterOperand(HInstruction* instr, InstructionSet isa) { in HasShifterOperand()
Dcontrol_flow_simplifier.cc117 HInstruction* instr = true_block->GetFirstInstruction(); in TryGenerateSelectSimpleDiamondPattern() local
122 HInstruction* instr = false_block->GetFirstInstruction(); in TryGenerateSelectSimpleDiamondPattern() local
Dgraph_visualizer.h69 void AddInstructionInterval(HInstruction* instr, size_t start, size_t end) { in AddInstructionInterval()
Dscheduler.h160 SchedulingNode(HInstruction* instr, ScopedArenaAllocator* allocator, bool is_scheduling_barrier) in SchedulingNode()
341 SchedulingNode* GetNode(const HInstruction* instr) const { in GetNode()
Dcode_generator_arm64.h579 vixl::aarch64::PRegister GetVecGoverningPReg(HVecOperation* instr) { in GetVecGoverningPReg()
590 static vixl::aarch64::PRegister GetVecPredSetFixedOutPReg(HVecPredSetOperation* instr) { in GetVecPredSetFixedOutPReg()
1100 void MaybeRecordImplicitNullCheck(HInstruction* instr) final { in MaybeRecordImplicitNullCheck()
Dsuperblock_cloner.cc42 static bool IsUsedOutsideRegion(const HInstruction* instr, const HBasicBlockSet& bb_set) { in IsUsedOutsideRegion()
532 HInstruction* instr = it.Current(); in CollectLiveOutsAndCheckClonable() local
541 HInstruction* instr = it.Current(); in CollectLiveOutsAndCheckClonable() local
Dgraph_test.cc40 HInstruction* instr = graph->GetIntConstant(4); in CreateIfBlock() local
/art/disassembler/
Ddisassembler_arm64.cc46 void CustomDisassembler::AppendRegisterNameToOutput(const Instruction* instr, in AppendRegisterNameToOutput()
63 void CustomDisassembler::AppendCodeRelativeAddressToOutput(const Instruction* instr, in AppendCodeRelativeAddressToOutput()
74 void CustomDisassembler::Visit(vixl::aarch64::Metadata* metadata, const Instruction* instr) { in Visit()
101 void CustomDisassembler::VisitLoadLiteralInstr(const Instruction* instr) { in VisitLoadLiteralInstr()
139 void CustomDisassembler::VisitLoadStoreUnsignedOffsetInstr(const Instruction* instr) { in VisitLoadStoreUnsignedOffsetInstr()
145 void CustomDisassembler::VisitUnconditionalBranchInstr(const Instruction* instr) { in VisitUnconditionalBranchInstr()
161 void CustomDisassembler::AppendThreadOfsetName(const vixl::aarch64::Instruction* instr) { in AppendThreadOfsetName()
169 const Instruction* instr = reinterpret_cast<const Instruction*>(begin); in Dump() local
Ddisassembler_x86.cc174 RegFile dst_reg_file, const uint8_t** instr, in DumpAddress()
257 size_t DisassemblerX86::DumpNops(std::ostream& os, const uint8_t* instr) { in DumpNops()
283 size_t DisassemblerX86::DumpInstruction(std::ostream& os, const uint8_t* instr) { in DumpInstruction()
/art/runtime/
Dinstrumentation_test.cc192 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in CheckConfigureStubs() local
219 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in TestEvent() local
346 static bool HasEventListener(const instrumentation::Instrumentation* instr, uint32_t event_type) in HasEventListener()
375 static void ReportEvent(const instrumentation::Instrumentation* instr, in ReportEvent()
468 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in TEST_F() local
615 instrumentation::Instrumentation* instr = runtime->GetInstrumentation(); in TEST_F() local
646 instrumentation::Instrumentation* instr = runtime->GetInstrumentation(); in TEST_F() local
665 instrumentation::Instrumentation* instr = runtime->GetInstrumentation(); in TEST_F() local
713 instrumentation::Instrumentation* instr = runtime->GetInstrumentation(); in TEST_F() local
732 instrumentation::Instrumentation* instr = runtime->GetInstrumentation(); in TEST_F() local
Dcommon_throws.cc483 static bool IsValidImplicitCheck(uintptr_t addr, const Instruction& instr) in IsValidImplicitCheck()
571 const Instruction& instr = accessor.InstructionAt(throw_dex_pc); in ThrowNullPointerExceptionFromDexPC() local
/art/runtime/entrypoints/quick/
Dquick_thread_entrypoints.cc29 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in artDeoptimizeIfNeeded() local
Dquick_trampoline_entrypoints.cc819 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in artQuickToInterpreterBridge() local
948 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in artQuickProxyInvokeHandler() local
1230 const Instruction& instr = accessor.InstructionAt(dex_pc); in artQuickResolutionTrampoline() local
2095 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in artQuickGenericJniTrampoline() local
2194 const Instruction& instr = accessor.InstructionAt(dex_pc); in artInvokeCommon() local
2305 const Instruction& instr = caller_method->DexInstructions().InstructionAt(dex_pc); in artInvokeInterfaceTrampoline() local
2692 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in artJniMethodEntryHook() local
2700 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in artMethodEntryHook() local
2736 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in artMethodExitHook() local
/art/runtime/arch/arm/
Dfault_handler_arm.cc42 uint16_t instr = pc[0] | pc[1] << 8; in GetInstructionSize() local
/art/runtime/interpreter/
Dinterpreter.cc443 static int16_t GetReceiverRegisterForStringInit(const Instruction* instr) { in GetReceiverRegisterForStringInit()
484 const Instruction* instr = &accessor.InstructionAt(dex_pc); in EnterInterpreterFromDeoptimize() local
/art/compiler/
Dcommon_compiler_test.cc309 instrumentation::Instrumentation* instr = GetRuntime()->GetInstrumentation(); in CompileMethod() local
/art/dex2oat/driver/
Dcompiler_driver_test.cc97 instrumentation::Instrumentation* instr = runtime_->GetInstrumentation(); in MakeExecutable() local

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