1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * SPDX-License-Identifier: MIT
9 */
10
11 #ifndef RADV_SHADER_H
12 #define RADV_SHADER_H
13
14 #include "util/mesa-blake3.h"
15 #include "util/u_math.h"
16 #include "vulkan/vulkan.h"
17 #include "ac_binary.h"
18 #include "ac_shader_util.h"
19 #include "amd_family.h"
20 #include "radv_constants.h"
21 #include "radv_shader_args.h"
22 #include "radv_shader_info.h"
23 #include "vk_pipeline_cache.h"
24
25 #include "aco_shader_info.h"
26
27 struct radv_physical_device;
28 struct radv_device;
29 struct radv_pipeline;
30 struct radv_ray_tracing_pipeline;
31 struct radv_shader_args;
32 struct radv_vertex_input_state;
33 struct radv_shader_args;
34 struct radv_serialized_shader_arena_block;
35 struct vk_pipeline_robustness_state;
36
37 enum {
38 RADV_GRAPHICS_STAGE_BITS =
39 (VK_SHADER_STAGE_ALL_GRAPHICS | VK_SHADER_STAGE_MESH_BIT_EXT | VK_SHADER_STAGE_TASK_BIT_EXT),
40 RADV_RT_STAGE_BITS =
41 (VK_SHADER_STAGE_RAYGEN_BIT_KHR | VK_SHADER_STAGE_ANY_HIT_BIT_KHR | VK_SHADER_STAGE_CLOSEST_HIT_BIT_KHR |
42 VK_SHADER_STAGE_MISS_BIT_KHR | VK_SHADER_STAGE_INTERSECTION_BIT_KHR | VK_SHADER_STAGE_CALLABLE_BIT_KHR)
43 };
44
45 #define RADV_STAGE_MASK ((1 << MESA_VULKAN_SHADER_STAGES) - 1)
46
47 #define radv_foreach_stage(stage, stage_bits) \
48 for (gl_shader_stage stage, __tmp = (gl_shader_stage)((stage_bits)&RADV_STAGE_MASK); stage = ffs(__tmp) - 1, __tmp; \
49 __tmp &= ~(1 << (stage)))
50
51 enum radv_nggc_settings {
52 radv_nggc_none = 0,
53 radv_nggc_front_face = 1 << 0,
54 radv_nggc_back_face = 1 << 1,
55 radv_nggc_face_is_ccw = 1 << 2,
56 radv_nggc_small_primitives = 1 << 3,
57 };
58
59 enum radv_shader_query_state {
60 radv_shader_query_none = 0,
61 radv_shader_query_pipeline_stat = 1 << 0,
62 radv_shader_query_prim_gen = 1 << 1,
63 radv_shader_query_prim_xfb = 1 << 2,
64 };
65
66 enum radv_required_subgroup_size {
67 RADV_REQUIRED_NONE = 0,
68 RADV_REQUIRED_WAVE32 = 1,
69 RADV_REQUIRED_WAVE64 = 2,
70 };
71
72 struct radv_shader_stage_key {
73 uint8_t subgroup_required_size : 2; /* radv_required_subgroup_size */
74 uint8_t subgroup_require_full : 1; /* whether full subgroups are required */
75
76 uint8_t storage_robustness2 : 1;
77 uint8_t uniform_robustness2 : 1;
78 uint8_t vertex_robustness1 : 1;
79
80 uint8_t optimisations_disabled : 1;
81 uint8_t keep_statistic_info : 1;
82 uint8_t view_index_from_device_index : 1;
83
84 /* Shader version (up to 8) to force re-compilation when RADV_BUILD_ID_OVERRIDE is enabled. */
85 uint8_t version : 3;
86
87 /* Whether the mesh shader is used with a task shader. */
88 uint8_t has_task_shader : 1;
89
90 /* Whether the shader is used with indirect pipeline binds. */
91 uint8_t indirect_bindable : 1;
92 };
93
94 struct radv_ps_epilog_key {
95 uint32_t spi_shader_col_format;
96 uint32_t spi_shader_z_format;
97
98 /* Bitmasks, each bit represents one of the 8 MRTs. */
99 uint8_t color_is_int8;
100 uint8_t color_is_int10;
101 uint8_t enable_mrt_output_nan_fixup;
102
103 uint32_t colors_written;
104 uint8_t color_map[MAX_RTS];
105 bool mrt0_is_dual_src;
106 bool export_depth;
107 bool export_stencil;
108 bool export_sample_mask;
109 bool alpha_to_coverage_via_mrtz;
110 bool alpha_to_one;
111 };
112
113 struct radv_spirv_to_nir_options {
114 uint32_t lower_view_index_to_zero : 1;
115 uint32_t lower_view_index_to_device_index : 1;
116 };
117
118 struct radv_graphics_state_key {
119 uint32_t lib_flags : 4; /* VkGraphicsPipelineLibraryFlagBitsEXT */
120
121 uint32_t has_multiview_view_index : 1;
122 uint32_t adjust_frag_coord_z : 1;
123 uint32_t dynamic_rasterization_samples : 1;
124 uint32_t dynamic_provoking_vtx_mode : 1;
125 uint32_t dynamic_line_rast_mode : 1;
126 uint32_t enable_remove_point_size : 1;
127 uint32_t unknown_rast_prim : 1;
128
129 struct {
130 uint8_t topology;
131 } ia;
132
133 struct {
134 uint32_t instance_rate_inputs;
135 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
136 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
137 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
138 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
139 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
140 uint8_t vertex_binding_align[MAX_VBS];
141 } vi;
142
143 struct {
144 unsigned patch_control_points;
145 } ts;
146
147 struct {
148 uint32_t provoking_vtx_last : 1;
149 } rs;
150
151 struct {
152 bool sample_shading_enable;
153 bool alpha_to_coverage_via_mrtz; /* GFX11+ */
154 uint8_t rasterization_samples;
155 } ms;
156
157 struct vs {
158 bool has_prolog;
159 } vs;
160
161 struct {
162 struct radv_ps_epilog_key epilog;
163 bool force_vrs_enabled;
164 bool exports_mrtz_via_epilog;
165 bool has_epilog;
166 } ps;
167 };
168
169 struct radv_graphics_pipeline_key {
170 struct radv_graphics_state_key gfx_state;
171
172 struct radv_shader_stage_key stage_info[MESA_VULKAN_SHADER_STAGES];
173 };
174
175 struct radv_nir_compiler_options {
176 bool robust_buffer_access_llvm;
177 bool dump_shader;
178 bool dump_ir;
179 bool dump_preoptir;
180 bool record_asm;
181 bool record_ir;
182 bool record_stats;
183 bool check_ir;
184 uint8_t enable_mrt_output_nan_fixup;
185 bool wgp_mode;
186 const struct radeon_info *info;
187
188 struct {
189 void (*func)(void *private_data, enum aco_compiler_debug_level level, const char *message);
190 void *private_data;
191 } debug;
192 };
193
194 #define SET_SGPR_FIELD(field, value) (((unsigned)(value)&field##__MASK) << field##__SHIFT)
195
196 #define TCS_OFFCHIP_LAYOUT_NUM_PATCHES__SHIFT 0
197 #define TCS_OFFCHIP_LAYOUT_NUM_PATCHES__MASK 0x7f
198 #define TCS_OFFCHIP_LAYOUT_PATCH_CONTROL_POINTS__SHIFT 12
199 #define TCS_OFFCHIP_LAYOUT_PATCH_CONTROL_POINTS__MASK 0x1f
200 #define TCS_OFFCHIP_LAYOUT_OUT_PATCH_CP__SHIFT 7
201 #define TCS_OFFCHIP_LAYOUT_OUT_PATCH_CP__MASK 0x1f
202 #define TCS_OFFCHIP_LAYOUT_NUM_LS_OUTPUTS__SHIFT 17
203 #define TCS_OFFCHIP_LAYOUT_NUM_LS_OUTPUTS__MASK 0x3f
204 #define TCS_OFFCHIP_LAYOUT_NUM_HS_OUTPUTS__SHIFT 23
205 #define TCS_OFFCHIP_LAYOUT_NUM_HS_OUTPUTS__MASK 0x3f
206 #define TCS_OFFCHIP_LAYOUT_PRIMITIVE_MODE__SHIFT 29
207 #define TCS_OFFCHIP_LAYOUT_PRIMITIVE_MODE__MASK 0x03
208 #define TCS_OFFCHIP_LAYOUT_TES_READS_TF__SHIFT 31
209 #define TCS_OFFCHIP_LAYOUT_TES_READS_TF__MASK 0x01
210
211 #define TES_STATE_NUM_PATCHES__SHIFT 0
212 #define TES_STATE_NUM_PATCHES__MASK 0xff
213 #define TES_STATE_TCS_VERTICES_OUT__SHIFT 8
214 #define TES_STATE_TCS_VERTICES_OUT__MASK 0xff
215 #define TES_STATE_NUM_TCS_OUTPUTS__SHIFT 16
216 #define TES_STATE_NUM_TCS_OUTPUTS__MASK 0xff
217
218 #define NGG_LDS_LAYOUT_GS_OUT_VERTEX_BASE__SHIFT 0
219 #define NGG_LDS_LAYOUT_GS_OUT_VERTEX_BASE__MASK 0xffff
220 #define NGG_LDS_LAYOUT_SCRATCH_BASE__SHIFT 16
221 #define NGG_LDS_LAYOUT_SCRATCH_BASE__MASK 0xffff
222
223 #define NGG_STATE_NUM_VERTS_PER_PRIM__SHIFT 0
224 #define NGG_STATE_NUM_VERTS_PER_PRIM__MASK 0x7
225 #define NGG_STATE_PROVOKING_VTX__SHIFT 3
226 #define NGG_STATE_PROVOKING_VTX__MASK 0x7
227 #define NGG_STATE_QUERY__SHIFT 6
228 #define NGG_STATE_QUERY__MASK 0x7
229
230 #define PS_STATE_NUM_SAMPLES__SHIFT 0
231 #define PS_STATE_NUM_SAMPLES__MASK 0xf
232 #define PS_STATE_LINE_RAST_MODE__SHIFT 4
233 #define PS_STATE_LINE_RAST_MODE__MASK 0x3
234 #define PS_STATE_PS_ITER_MASK__SHIFT 6
235 #define PS_STATE_PS_ITER_MASK__MASK 0xffff
236 #define PS_STATE_RAST_PRIM__SHIFT 22
237 #define PS_STATE_RAST_PRIM__MASK 0x3
238
239 struct radv_shader_layout {
240 uint32_t num_sets;
241
242 struct {
243 struct radv_descriptor_set_layout *layout;
244 uint32_t dynamic_offset_start;
245 } set[MAX_SETS];
246
247 uint32_t push_constant_size;
248 uint32_t dynamic_offset_count;
249 bool use_dynamic_descriptors;
250 };
251
252 struct radv_shader_stage {
253 gl_shader_stage stage;
254 gl_shader_stage next_stage;
255
256 struct {
257 const struct vk_object_base *object;
258 const char *data;
259 uint32_t size;
260 } spirv;
261
262 const char *entrypoint;
263 const VkSpecializationInfo *spec_info;
264
265 unsigned char shader_sha1[20];
266
267 nir_shader *nir;
268 nir_shader *internal_nir; /* meta shaders */
269
270 struct radv_shader_info info;
271 struct radv_shader_args args;
272 struct radv_shader_stage_key key;
273
274 VkPipelineCreationFeedback feedback;
275
276 struct radv_shader_layout layout;
277 };
278
279 static inline bool
radv_is_last_vgt_stage(const struct radv_shader_stage * stage)280 radv_is_last_vgt_stage(const struct radv_shader_stage *stage)
281 {
282 return (stage->info.stage == MESA_SHADER_VERTEX || stage->info.stage == MESA_SHADER_TESS_EVAL ||
283 stage->info.stage == MESA_SHADER_GEOMETRY || stage->info.stage == MESA_SHADER_MESH) &&
284 (stage->info.next_stage == MESA_SHADER_FRAGMENT || stage->info.next_stage == MESA_SHADER_NONE);
285 }
286
287 struct radv_vertex_input_state {
288 uint32_t attribute_mask;
289
290 uint32_t instance_rate_inputs;
291 uint32_t nontrivial_divisors;
292 uint32_t zero_divisors;
293 uint32_t post_shuffle;
294 /* Having two separate fields instead of a single uint64_t makes it easier to remove attributes
295 * using bitwise arithmetic.
296 */
297 uint32_t alpha_adjust_lo;
298 uint32_t alpha_adjust_hi;
299 uint32_t nontrivial_formats;
300
301 uint8_t bindings[MAX_VERTEX_ATTRIBS];
302 uint32_t divisors[MAX_VERTEX_ATTRIBS];
303 uint32_t offsets[MAX_VERTEX_ATTRIBS];
304 uint8_t formats[MAX_VERTEX_ATTRIBS];
305 uint8_t format_align_req_minus_1[MAX_VERTEX_ATTRIBS];
306 uint8_t component_align_req_minus_1[MAX_VERTEX_ATTRIBS];
307 uint8_t format_sizes[MAX_VERTEX_ATTRIBS];
308 uint32_t attrib_index_offset[MAX_VERTEX_ATTRIBS]; /* Only used with static strides. */
309
310 bool bindings_match_attrib;
311 };
312
313 struct radv_vs_prolog_key {
314 /* All the fields are pre-masked with BITFIELD_MASK(num_attributes).
315 * Some of the fields are pre-masked by other conditions. See lookup_vs_prolog.
316 */
317 uint32_t instance_rate_inputs;
318 uint32_t nontrivial_divisors;
319 uint32_t zero_divisors;
320 uint32_t post_shuffle;
321 /* Having two separate fields instead of a single uint64_t makes it easier to remove attributes
322 * using bitwise arithmetic.
323 */
324 uint32_t alpha_adjust_lo;
325 uint32_t alpha_adjust_hi;
326 uint8_t formats[MAX_VERTEX_ATTRIBS];
327 unsigned num_attributes;
328 uint32_t misaligned_mask;
329 uint32_t unaligned_mask;
330 bool as_ls;
331 bool is_ngg;
332 bool wave32;
333 gl_shader_stage next_stage;
334 };
335
336 enum radv_shader_binary_type { RADV_BINARY_TYPE_LEGACY, RADV_BINARY_TYPE_RTLD };
337
338 struct radv_shader_binary {
339 uint32_t type; /* enum radv_shader_binary_type */
340
341 struct ac_shader_config config;
342 struct radv_shader_info info;
343
344 /* Self-referential size so we avoid consistency issues. */
345 uint32_t total_size;
346 };
347
348 struct radv_shader_binary_legacy {
349 struct radv_shader_binary base;
350 uint32_t code_size;
351 uint32_t exec_size;
352 uint32_t ir_size;
353 uint32_t disasm_size;
354 uint32_t stats_size;
355 uint32_t debug_info_size;
356
357 /* data has size of stats_size + code_size + ir_size + disasm_size + 2,
358 * where the +2 is for 0 of the ir strings. */
359 uint8_t data[0];
360 };
361 static_assert(sizeof(struct radv_shader_binary_legacy) == offsetof(struct radv_shader_binary_legacy, data),
362 "Unexpected padding");
363
364 struct radv_shader_binary_rtld {
365 struct radv_shader_binary base;
366 unsigned elf_size;
367 unsigned llvm_ir_size;
368 uint8_t data[0];
369 };
370
371 struct radv_shader_part_binary {
372 struct {
373 uint32_t spi_shader_col_format;
374 uint32_t cb_shader_mask;
375 uint32_t spi_shader_z_format;
376 } info;
377
378 uint8_t num_sgprs;
379 uint8_t num_vgprs;
380 unsigned code_size;
381 unsigned disasm_size;
382
383 /* Self-referential size so we avoid consistency issues. */
384 uint32_t total_size;
385
386 uint8_t data[0];
387 };
388
389 enum radv_shader_arena_type { RADV_SHADER_ARENA_DEFAULT, RADV_SHADER_ARENA_REPLAYABLE, RADV_SHADER_ARENA_REPLAYED };
390
391 struct radv_shader_arena {
392 struct list_head list;
393 struct list_head entries;
394 uint32_t size;
395 struct radeon_winsys_bo *bo;
396 char *ptr;
397 enum radv_shader_arena_type type;
398 };
399
400 union radv_shader_arena_block {
401 struct list_head pool;
402 struct {
403 /* List of blocks in the arena, sorted by address. */
404 struct list_head list;
405 /* For holes, a list_head for the free-list. For allocations, freelist.prev=NULL and
406 * freelist.next is a pointer associated with the allocation.
407 */
408 struct list_head freelist;
409 struct radv_shader_arena *arena;
410 uint32_t offset;
411 uint32_t size;
412 };
413 };
414
415 struct radv_shader_free_list {
416 uint8_t size_mask;
417 struct list_head free_lists[RADV_SHADER_ALLOC_NUM_FREE_LISTS];
418 };
419
420 struct radv_serialized_shader_arena_block {
421 uint32_t offset;
422 uint32_t size;
423 uint64_t arena_va;
424 uint32_t arena_size;
425 };
426
427 struct radv_shader {
428 struct vk_pipeline_cache_object base;
429
430 simple_mtx_t replay_mtx;
431 bool has_replay_alloc;
432
433 struct radeon_winsys_bo *bo;
434 union radv_shader_arena_block *alloc;
435 uint64_t va;
436
437 uint64_t upload_seq;
438
439 struct ac_shader_config config;
440 uint32_t code_size;
441 uint32_t exec_size;
442 struct radv_shader_info info;
443 uint32_t max_waves;
444
445 blake3_hash hash;
446 void *code;
447
448 /* debug only */
449 char *spirv;
450 uint32_t spirv_size;
451 char *nir_string;
452 char *disasm_string;
453 char *ir_string;
454 uint32_t *statistics;
455 struct ac_shader_debug_info *debug_info;
456 uint32_t debug_info_count;
457 };
458
459 struct radv_shader_part {
460 uint32_t ref_count;
461
462 union {
463 struct radv_vs_prolog_key vs;
464 struct radv_ps_epilog_key ps;
465 } key;
466
467 uint64_t va;
468
469 struct radeon_winsys_bo *bo;
470 union radv_shader_arena_block *alloc;
471 uint32_t code_size;
472 uint32_t rsrc1;
473 bool nontrivial_divisors;
474 uint32_t spi_shader_col_format;
475 uint32_t cb_shader_mask;
476 uint32_t spi_shader_z_format;
477 uint64_t upload_seq;
478
479 /* debug only */
480 char *disasm_string;
481 };
482
483 struct radv_shader_part_cache_ops {
484 uint32_t (*hash)(const void *key);
485 bool (*equals)(const void *a, const void *b);
486 struct radv_shader_part *(*create)(struct radv_device *device, const void *key);
487 };
488
489 struct radv_shader_part_cache {
490 simple_mtx_t lock;
491 struct radv_shader_part_cache_ops *ops;
492 struct set entries;
493 };
494
495 struct radv_shader_dma_submission {
496 struct list_head list;
497
498 struct radeon_cmdbuf *cs;
499 struct radeon_winsys_bo *bo;
500 uint64_t bo_size;
501 char *ptr;
502
503 /* The semaphore value to wait for before reusing this submission. */
504 uint64_t seq;
505 };
506
507 struct radv_pipeline_layout;
508 struct radv_shader_stage;
509
510 void radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively);
511 void radv_optimize_nir_algebraic(nir_shader *shader, bool opt_offsets, bool opt_mqsad);
512
513 void radv_nir_lower_rt_io(nir_shader *shader, bool monolithic, uint32_t payload_offset);
514
515 struct radv_ray_tracing_stage_info;
516
517 void radv_nir_lower_rt_abi(nir_shader *shader, const VkRayTracingPipelineCreateInfoKHR *pCreateInfo,
518 const struct radv_shader_args *args, const struct radv_shader_info *info,
519 uint32_t *stack_size, bool resume_shader, struct radv_device *device,
520 struct radv_ray_tracing_pipeline *pipeline, bool monolithic,
521 const struct radv_ray_tracing_stage_info *traversal_info);
522
523 void radv_gather_unused_args(struct radv_ray_tracing_stage_info *info, nir_shader *nir);
524
525 struct radv_shader_stage;
526
527 nir_shader *radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_stage *stage,
528 const struct radv_spirv_to_nir_options *options, bool is_internal);
529
530 void radv_init_shader_arenas(struct radv_device *device);
531 void radv_destroy_shader_arenas(struct radv_device *device);
532 VkResult radv_init_shader_upload_queue(struct radv_device *device);
533 void radv_destroy_shader_upload_queue(struct radv_device *device);
534
535 struct radv_shader_args;
536
537 VkResult radv_shader_create_uncached(struct radv_device *device, const struct radv_shader_binary *binary,
538 bool replayable, struct radv_serialized_shader_arena_block *replay_block,
539 struct radv_shader **out_shader);
540
541 struct radv_shader_binary *radv_shader_nir_to_asm(struct radv_device *device, struct radv_shader_stage *pl_stage,
542 struct nir_shader *const *shaders, int shader_count,
543 const struct radv_graphics_state_key *gfx_state,
544 bool keep_shader_info, bool keep_statistic_info);
545
546 void radv_shader_dump_debug_info(struct radv_device *device, bool dump_shader, struct radv_shader_binary *binary,
547 struct radv_shader *shader, struct nir_shader *const *shaders, int shader_count,
548 struct radv_shader_info *info);
549
550 struct radv_instance;
551 char *radv_dump_nir_shaders(const struct radv_instance *instance, struct nir_shader *const *shaders, int shader_count);
552
553 VkResult radv_shader_wait_for_upload(struct radv_device *device, uint64_t seq);
554
555 struct radv_shader_dma_submission *radv_shader_dma_pop_submission(struct radv_device *device);
556
557 void radv_shader_dma_push_submission(struct radv_device *device, struct radv_shader_dma_submission *submission,
558 uint64_t seq);
559
560 struct radv_shader_dma_submission *
561 radv_shader_dma_get_submission(struct radv_device *device, struct radeon_winsys_bo *bo, uint64_t va, uint64_t size);
562
563 bool radv_shader_dma_submit(struct radv_device *device, struct radv_shader_dma_submission *submission,
564 uint64_t *upload_seq_out);
565
566 union radv_shader_arena_block *radv_alloc_shader_memory(struct radv_device *device, uint32_t size, bool replayable,
567 void *ptr);
568
569 union radv_shader_arena_block *radv_replay_shader_arena_block(struct radv_device *device,
570 const struct radv_serialized_shader_arena_block *src,
571 void *ptr);
572
573 void radv_free_shader_memory(struct radv_device *device, union radv_shader_arena_block *alloc);
574
575 struct radv_shader *radv_create_trap_handler_shader(struct radv_device *device);
576
577 struct radv_shader *radv_create_rt_prolog(struct radv_device *device);
578
579 struct radv_shader_part *radv_shader_part_create(struct radv_device *device, struct radv_shader_part_binary *binary,
580 unsigned wave_size);
581
582 struct radv_shader_part *radv_create_vs_prolog(struct radv_device *device, const struct radv_vs_prolog_key *key);
583
584 struct radv_shader_part *radv_create_ps_epilog(struct radv_device *device, const struct radv_ps_epilog_key *key,
585 struct radv_shader_part_binary **binary_out);
586
587 void radv_shader_part_destroy(struct radv_device *device, struct radv_shader_part *shader_part);
588
589 bool radv_shader_part_cache_init(struct radv_shader_part_cache *cache, struct radv_shader_part_cache_ops *ops);
590 void radv_shader_part_cache_finish(struct radv_device *device, struct radv_shader_part_cache *cache);
591 struct radv_shader_part *radv_shader_part_cache_get(struct radv_device *device, struct radv_shader_part_cache *cache,
592 struct set *local_entries, const void *key);
593
594 uint64_t radv_shader_get_va(const struct radv_shader *shader);
595 struct radv_shader *radv_find_shader(struct radv_device *device, uint64_t pc);
596
597 unsigned radv_get_max_waves(const struct radv_device *device, const struct ac_shader_config *conf,
598 const struct radv_shader_info *info);
599
600 unsigned radv_get_max_scratch_waves(const struct radv_device *device, struct radv_shader *shader);
601
602 const char *radv_get_shader_name(const struct radv_shader_info *info, gl_shader_stage stage);
603
604 unsigned radv_compute_spi_ps_input(const struct radv_physical_device *pdev,
605 const struct radv_graphics_state_key *gfx_state,
606 const struct radv_shader_info *info);
607
608 bool radv_can_dump_shader(struct radv_device *device, nir_shader *nir);
609
610 bool radv_can_dump_shader_stats(struct radv_device *device, nir_shader *nir);
611
612 VkResult radv_dump_shader_stats(struct radv_device *device, struct radv_pipeline *pipeline, struct radv_shader *shader,
613 gl_shader_stage stage, FILE *output);
614
615 /* Returns true on success and false on failure */
616 bool radv_shader_reupload(struct radv_device *device, struct radv_shader *shader);
617
618 extern const struct vk_pipeline_cache_object_ops radv_shader_ops;
619
620 static inline struct radv_shader *
radv_shader_ref(struct radv_shader * shader)621 radv_shader_ref(struct radv_shader *shader)
622 {
623 vk_pipeline_cache_object_ref(&shader->base);
624 return shader;
625 }
626
627 static inline void
radv_shader_unref(struct radv_device * device,struct radv_shader * shader)628 radv_shader_unref(struct radv_device *device, struct radv_shader *shader)
629 {
630 vk_pipeline_cache_object_unref((struct vk_device *)device, &shader->base);
631 }
632
633 static inline struct radv_shader_part *
radv_shader_part_ref(struct radv_shader_part * shader_part)634 radv_shader_part_ref(struct radv_shader_part *shader_part)
635 {
636 assert(shader_part && shader_part->ref_count >= 1);
637 p_atomic_inc(&shader_part->ref_count);
638 return shader_part;
639 }
640
641 static inline void
radv_shader_part_unref(struct radv_device * device,struct radv_shader_part * shader_part)642 radv_shader_part_unref(struct radv_device *device, struct radv_shader_part *shader_part)
643 {
644 assert(shader_part && shader_part->ref_count >= 1);
645 if (p_atomic_dec_zero(&shader_part->ref_count))
646 radv_shader_part_destroy(device, shader_part);
647 }
648
649 static inline struct radv_shader_part *
radv_shader_part_from_cache_entry(const void * key)650 radv_shader_part_from_cache_entry(const void *key)
651 {
652 return container_of(key, struct radv_shader_part, key);
653 }
654
655 static inline unsigned
get_tcs_input_vertex_stride(unsigned tcs_num_inputs)656 get_tcs_input_vertex_stride(unsigned tcs_num_inputs)
657 {
658 unsigned stride = tcs_num_inputs * 16;
659
660 /* Add 1 dword to reduce LDS bank conflicts. */
661 if (stride)
662 stride += 4;
663
664 return stride;
665 }
666
667 void radv_get_tess_wg_info(const struct radv_physical_device *pdev, const struct shader_info *tcs_info,
668 unsigned tcs_num_input_vertices, unsigned tcs_num_lds_inputs, unsigned tcs_num_vram_outputs,
669 unsigned tcs_num_vram_patch_outputs, bool all_invocations_define_tess_levels,
670 unsigned *num_patches_per_wg, unsigned *hw_lds_size);
671
672 void radv_lower_ngg(struct radv_device *device, struct radv_shader_stage *ngg_stage,
673 const struct radv_graphics_state_key *gfx_state);
674
675 bool radv_consider_culling(const struct radv_physical_device *pdev, struct nir_shader *nir, uint64_t ps_inputs_read,
676 unsigned num_vertices_per_primitive, const struct radv_shader_info *info);
677
678 void radv_get_nir_options(struct radv_physical_device *pdev);
679
680 struct radv_ray_tracing_stage_info;
681
682 nir_shader *radv_build_traversal_shader(struct radv_device *device, struct radv_ray_tracing_pipeline *pipeline,
683 const VkRayTracingPipelineCreateInfoKHR *pCreateInfo,
684 struct radv_ray_tracing_stage_info *info);
685
686 enum radv_rt_priority {
687 radv_rt_priority_raygen = 0,
688 radv_rt_priority_traversal = 1,
689 radv_rt_priority_hit_miss = 2,
690 radv_rt_priority_callable = 3,
691 radv_rt_priority_mask = 0x3,
692 };
693
694 static inline enum radv_rt_priority
radv_get_rt_priority(gl_shader_stage stage)695 radv_get_rt_priority(gl_shader_stage stage)
696 {
697 switch (stage) {
698 case MESA_SHADER_RAYGEN:
699 return radv_rt_priority_raygen;
700 case MESA_SHADER_INTERSECTION:
701 case MESA_SHADER_ANY_HIT:
702 return radv_rt_priority_traversal;
703 case MESA_SHADER_CLOSEST_HIT:
704 case MESA_SHADER_MISS:
705 return radv_rt_priority_hit_miss;
706 case MESA_SHADER_CALLABLE:
707 return radv_rt_priority_callable;
708 default:
709 unreachable("Unimplemented RT shader stage.");
710 }
711 }
712
713 struct radv_shader_layout;
714 enum radv_pipeline_type;
715
716 void radv_shader_combine_cfg_vs_tcs(const struct radv_shader *vs, const struct radv_shader *tcs, uint32_t *rsrc1_out,
717 uint32_t *rsrc2_out);
718
719 void radv_shader_combine_cfg_vs_gs(const struct radv_shader *vs, const struct radv_shader *gs, uint32_t *rsrc1_out,
720 uint32_t *rsrc2_out);
721
722 void radv_shader_combine_cfg_tes_gs(const struct radv_shader *tes, const struct radv_shader *gs, uint32_t *rsrc1_out,
723 uint32_t *rsrc2_out);
724
725 const struct radv_userdata_info *radv_get_user_sgpr_info(const struct radv_shader *shader, int idx);
726
727 uint32_t radv_get_user_sgpr_loc(const struct radv_shader *shader, int idx);
728
729 uint32_t radv_get_user_sgpr(const struct radv_shader *shader, int idx);
730
731 void radv_precompute_registers_hw_ngg(struct radv_device *device, const struct ac_shader_config *config,
732 struct radv_shader_info *info);
733
734 void radv_set_stage_key_robustness(const struct vk_pipeline_robustness_state *rs, gl_shader_stage stage,
735 struct radv_shader_stage_key *key);
736
737 #endif /* RADV_SHADER_H */
738