1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 /**
24 * @file iris_screen.c
25 *
26 * Screen related driver hooks and capability lists.
27 *
28 * A program may use multiple rendering contexts (iris_context), but
29 * they all share a common screen (iris_screen). Global driver state
30 * can be stored in the screen; it may be accessed by multiple threads.
31 */
32
33 #include <stdio.h>
34 #include <errno.h>
35 #include <sys/ioctl.h>
36 #include "pipe/p_defines.h"
37 #include "pipe/p_state.h"
38 #include "pipe/p_context.h"
39 #include "pipe/p_screen.h"
40 #include "util/u_debug.h"
41 #include "util/os_file.h"
42 #include "util/u_cpu_detect.h"
43 #include "util/u_inlines.h"
44 #include "util/format/u_format.h"
45 #include "util/u_transfer_helper.h"
46 #include "util/u_upload_mgr.h"
47 #include "util/ralloc.h"
48 #include "util/xmlconfig.h"
49 #include "iris_context.h"
50 #include "iris_defines.h"
51 #include "iris_fence.h"
52 #include "iris_perf.h"
53 #include "iris_pipe.h"
54 #include "iris_resource.h"
55 #include "iris_screen.h"
56 #include "compiler/glsl_types.h"
57 #include "intel/common/intel_debug_identifier.h"
58 #include "intel/common/intel_gem.h"
59 #include "intel/common/intel_l3_config.h"
60 #include "intel/common/intel_uuid.h"
61 #include "iris_monitor.h"
62
63 #define genX_call(devinfo, func, ...) \
64 switch ((devinfo)->verx10) { \
65 case 300: \
66 gfx30_##func(__VA_ARGS__); \
67 break; \
68 case 200: \
69 gfx20_##func(__VA_ARGS__); \
70 break; \
71 case 125: \
72 gfx125_##func(__VA_ARGS__); \
73 break; \
74 case 120: \
75 gfx12_##func(__VA_ARGS__); \
76 break; \
77 case 110: \
78 gfx11_##func(__VA_ARGS__); \
79 break; \
80 case 90: \
81 gfx9_##func(__VA_ARGS__); \
82 break; \
83 case 80: \
84 gfx8_##func(__VA_ARGS__); \
85 break; \
86 default: \
87 unreachable("Unknown hardware generation"); \
88 }
89
90 static const char *
iris_get_vendor(struct pipe_screen * pscreen)91 iris_get_vendor(struct pipe_screen *pscreen)
92 {
93 return "Intel";
94 }
95
96 static const char *
iris_get_device_vendor(struct pipe_screen * pscreen)97 iris_get_device_vendor(struct pipe_screen *pscreen)
98 {
99 return "Intel";
100 }
101
102 static void
iris_get_device_uuid(struct pipe_screen * pscreen,char * uuid)103 iris_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
104 {
105 struct iris_screen *screen = (struct iris_screen *)pscreen;
106
107 intel_uuid_compute_device_id((uint8_t *)uuid, screen->devinfo, PIPE_UUID_SIZE);
108 }
109
110 static void
iris_get_driver_uuid(struct pipe_screen * pscreen,char * uuid)111 iris_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
112 {
113 struct iris_screen *screen = (struct iris_screen *)pscreen;
114 const struct intel_device_info *devinfo = screen->devinfo;
115
116 intel_uuid_compute_driver_id((uint8_t *)uuid, devinfo, PIPE_UUID_SIZE);
117 }
118
119 static void
iris_warn_cl()120 iris_warn_cl()
121 {
122 static bool warned = false;
123 if (warned || INTEL_DEBUG(DEBUG_CL_QUIET))
124 return;
125
126 warned = true;
127 fprintf(stderr, "WARNING: OpenCL support via iris driver is incomplete.\n"
128 "For a complete and conformant OpenCL implementation, use\n"
129 "https://github.com/intel/compute-runtime instead\n");
130 }
131
132 static const char *
iris_get_name(struct pipe_screen * pscreen)133 iris_get_name(struct pipe_screen *pscreen)
134 {
135 struct iris_screen *screen = (struct iris_screen *)pscreen;
136 const struct intel_device_info *devinfo = screen->devinfo;
137 static char buf[128];
138
139 snprintf(buf, sizeof(buf), "Mesa %s", devinfo->name);
140 return buf;
141 }
142
143 static const char *
iris_get_cl_cts_version(struct pipe_screen * pscreen)144 iris_get_cl_cts_version(struct pipe_screen *pscreen)
145 {
146 struct iris_screen *screen = (struct iris_screen *)pscreen;
147 const struct intel_device_info *devinfo = screen->devinfo;
148
149 /* https://www.khronos.org/conformance/adopters/conformant-products/opencl#submission_405 */
150 if (devinfo->verx10 == 120)
151 return "v2022-04-22-00";
152
153 return NULL;
154 }
155
156 static int
iris_get_video_memory(struct iris_screen * screen)157 iris_get_video_memory(struct iris_screen *screen)
158 {
159 uint64_t vram = iris_bufmgr_vram_size(screen->bufmgr);
160 uint64_t sram = iris_bufmgr_sram_size(screen->bufmgr);
161 if (vram) {
162 return vram / (1024 * 1024);
163 } else if (sram) {
164 return sram / (1024 * 1024);
165 } else {
166 /* This is the old code path, it get the GGTT size from the kernel
167 * (which should always be 4Gb on Gfx8+).
168 *
169 * We should probably never end up here. This is just a fallback to get
170 * some kind of value in case os_get_available_system_memory fails.
171 */
172 const struct intel_device_info *devinfo = screen->devinfo;
173 /* Once a batch uses more than 75% of the maximum mappable size, we
174 * assume that there's some fragmentation, and we start doing extra
175 * flushing, etc. That's the big cliff apps will care about.
176 */
177 const unsigned gpu_mappable_megabytes =
178 (devinfo->aperture_bytes * 3 / 4) / (1024 * 1024);
179
180 const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
181 const long system_page_size = sysconf(_SC_PAGE_SIZE);
182
183 if (system_memory_pages <= 0 || system_page_size <= 0)
184 return -1;
185
186 const uint64_t system_memory_bytes =
187 (uint64_t) system_memory_pages * (uint64_t) system_page_size;
188
189 const unsigned system_memory_megabytes =
190 (unsigned) (system_memory_bytes / (1024 * 1024));
191
192 return MIN2(system_memory_megabytes, gpu_mappable_megabytes);
193 }
194 }
195
196 static int
iris_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type p_stage,enum pipe_shader_cap param)197 iris_get_shader_param(struct pipe_screen *pscreen,
198 enum pipe_shader_type p_stage,
199 enum pipe_shader_cap param)
200 {
201 gl_shader_stage stage = stage_from_pipe(p_stage);
202
203 if (p_stage == PIPE_SHADER_MESH ||
204 p_stage == PIPE_SHADER_TASK)
205 return 0;
206
207 /* this is probably not totally correct.. but it's a start: */
208 switch (param) {
209 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
210 return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
211 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
212 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
213 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
214 return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
215
216 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
217 return UINT_MAX;
218
219 case PIPE_SHADER_CAP_MAX_INPUTS:
220 return stage == MESA_SHADER_VERTEX ? 16 : 32;
221 case PIPE_SHADER_CAP_MAX_OUTPUTS:
222 return 32;
223 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
224 return 16 * 1024 * sizeof(float);
225 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
226 return 16;
227 case PIPE_SHADER_CAP_MAX_TEMPS:
228 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
229 case PIPE_SHADER_CAP_CONT_SUPPORTED:
230 return 0;
231 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
232 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
233 /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
234 * which we don't want. Our compiler backend will check brw_compiler's
235 * options and call nir_lower_indirect_derefs appropriately anyway.
236 */
237 return true;
238 case PIPE_SHADER_CAP_SUBROUTINES:
239 return 0;
240 case PIPE_SHADER_CAP_INTEGERS:
241 return 1;
242 case PIPE_SHADER_CAP_INT64_ATOMICS:
243 case PIPE_SHADER_CAP_FP16:
244 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
245 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
246 case PIPE_SHADER_CAP_INT16:
247 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
248 return 0;
249 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
250 return IRIS_MAX_SAMPLERS;
251 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
252 return IRIS_MAX_TEXTURES;
253 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
254 return IRIS_MAX_IMAGES;
255 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
256 return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
257 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
258 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
259 return 0;
260 case PIPE_SHADER_CAP_SUPPORTED_IRS:
261 return 1 << PIPE_SHADER_IR_NIR;
262 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
263 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
264 return 0;
265 default:
266 unreachable("unknown shader param");
267 }
268 }
269
270 static int
iris_get_compute_param(struct pipe_screen * pscreen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * ret)271 iris_get_compute_param(struct pipe_screen *pscreen,
272 enum pipe_shader_ir ir_type,
273 enum pipe_compute_cap param,
274 void *ret)
275 {
276 struct iris_screen *screen = (struct iris_screen *)pscreen;
277 const struct intel_device_info *devinfo = screen->devinfo;
278
279 const uint32_t max_invocations =
280 MIN2(1024, 32 * devinfo->max_cs_workgroup_threads);
281
282 #define RET(x) do { \
283 if (ret) \
284 memcpy(ret, x, sizeof(x)); \
285 return sizeof(x); \
286 } while (0)
287
288 switch (param) {
289 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
290 /* This gets queried on OpenCL device init and is never queried by the
291 * OpenGL state tracker.
292 */
293 iris_warn_cl();
294 RET((uint32_t []){ 64 });
295
296 case PIPE_COMPUTE_CAP_IR_TARGET:
297 if (ret)
298 strcpy(ret, "gen");
299 return 4;
300
301 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
302 RET((uint64_t []) { 3 });
303
304 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
305 RET(((uint64_t []) { UINT32_MAX, UINT32_MAX, UINT32_MAX }));
306
307 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
308 /* MaxComputeWorkGroupSize[0..2] */
309 RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
310
311 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
312 /* MaxComputeWorkGroupInvocations */
313 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
314 /* MaxComputeVariableGroupInvocations */
315 RET((uint64_t []) { max_invocations });
316
317 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
318 /* MaxComputeSharedMemorySize */
319 RET((uint64_t []) { 64 * 1024 });
320
321 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
322 RET((uint32_t []) { 1 });
323
324 case PIPE_COMPUTE_CAP_SUBGROUP_SIZES:
325 RET((uint32_t []) { 32 | 16 | 8 });
326
327 case PIPE_COMPUTE_CAP_MAX_SUBGROUPS:
328 RET((uint32_t []) { devinfo->max_cs_workgroup_threads });
329
330 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
331 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
332 RET((uint64_t []) { 1 << 30 }); /* TODO */
333
334 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
335 RET((uint32_t []) { 400 }); /* TODO */
336
337 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS: {
338 RET((uint32_t []) { intel_device_info_subslice_total(devinfo) });
339 }
340
341 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
342 /* MaxComputeSharedMemorySize */
343 RET((uint64_t []) { 64 * 1024 });
344
345 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
346 /* We could probably allow more; this is the OpenCL minimum */
347 RET((uint64_t []) { 1024 });
348
349 default:
350 unreachable("unknown compute param");
351 }
352 }
353
354 static void
iris_init_screen_caps(struct iris_screen * screen)355 iris_init_screen_caps(struct iris_screen *screen)
356 {
357 struct pipe_caps *caps = (struct pipe_caps *)&screen->base.caps;
358
359 u_init_pipe_screen_caps(&screen->base, 1);
360
361 const struct intel_device_info *devinfo = screen->devinfo;
362
363 caps->npot_textures = true;
364 caps->anisotropic_filter = true;
365 caps->occlusion_query = true;
366 caps->query_time_elapsed = true;
367 caps->texture_swizzle = true;
368 caps->texture_mirror_clamp_to_edge = true;
369 caps->blend_equation_separate = true;
370 caps->fragment_shader_texture_lod = true;
371 caps->fragment_shader_derivatives = true;
372 caps->primitive_restart = true;
373 caps->primitive_restart_fixed_index = true;
374 caps->indep_blend_enable = true;
375 caps->indep_blend_func = true;
376 caps->fs_coord_origin_upper_left = true;
377 caps->fs_coord_pixel_center_integer = true;
378 caps->depth_clip_disable = true;
379 caps->vs_instanceid = true;
380 caps->vertex_element_instance_divisor = true;
381 caps->seamless_cube_map = true;
382 caps->seamless_cube_map_per_texture = true;
383 caps->conditional_render = true;
384 caps->texture_barrier = true;
385 caps->stream_output_pause_resume = true;
386 caps->vertex_color_unclamped = true;
387 caps->compute = true;
388 caps->start_instance = true;
389 caps->query_timestamp = true;
390 caps->texture_multisample = true;
391 caps->cube_map_array = true;
392 caps->texture_buffer_objects = true;
393 caps->query_pipeline_statistics_single = true;
394 caps->texture_query_lod = true;
395 caps->sample_shading = true;
396 caps->force_persample_interp = true;
397 caps->draw_indirect = true;
398 caps->multi_draw_indirect = true;
399 caps->multi_draw_indirect_params = true;
400 caps->mixed_framebuffer_sizes = true;
401 caps->vs_layer_viewport = true;
402 caps->tes_layer_viewport = true;
403 caps->fs_fine_derivative = true;
404 caps->shader_pack_half_float = true;
405 caps->conditional_render_inverted = true;
406 caps->clip_halfz = true;
407 caps->tgsi_texcoord = true;
408 caps->stream_output_interleave_buffers = true;
409 caps->doubles = true;
410 caps->int64 = true;
411 caps->sampler_view_target = true;
412 caps->robust_buffer_access_behavior = true;
413 caps->device_reset_status_query = true;
414 caps->copy_between_compressed_and_plain_formats = true;
415 caps->framebuffer_no_attachment = true;
416 caps->cull_distance = true;
417 caps->packed_uniforms = true;
418 caps->signed_vertex_buffer_offset = true;
419 caps->texture_float_linear = true;
420 caps->texture_half_float_linear = true;
421 caps->polygon_offset_clamp = true;
422 caps->query_so_overflow = true;
423 caps->query_buffer_object = true;
424 caps->tgsi_tex_txf_lz = true;
425 caps->texture_query_samples = true;
426 caps->shader_clock = true;
427 caps->shader_ballot = true;
428 caps->multisample_z_resolve = true;
429 caps->clear_scissored = true;
430 caps->shader_group_vote = true;
431 caps->vs_window_space_position = true;
432 caps->texture_gather_sm5 = true;
433 caps->shader_array_components = true;
434 caps->glsl_tess_levels_as_inputs = true;
435 caps->load_constbuf = true;
436 caps->draw_parameters = true;
437 caps->fs_position_is_sysval = true;
438 caps->fs_face_is_integer_sysval = true;
439 caps->compute_shader_derivatives = true;
440 caps->invalidate_buffer = true;
441 caps->surface_reinterpret_blocks = true;
442 caps->texture_shadow_lod = true;
443 caps->shader_samples_identical = true;
444 caps->gl_spirv = true;
445 caps->gl_spirv_variable_pointers = true;
446 caps->demote_to_helper_invocation = true;
447 caps->native_fence_fd = true;
448 caps->memobj = true;
449 caps->mixed_color_depth_bits = true;
450 caps->fence_signal = true;
451 caps->image_store_formatted = true;
452 caps->legacy_math_rules = true;
453 caps->alpha_to_coverage_dither_control = true;
454 caps->map_unsynchronized_thread_safe = true;
455 caps->has_const_bw = true;
456 caps->cl_gl_sharing = true;
457 caps->uma = iris_bufmgr_vram_size(screen->bufmgr) == 0;
458 caps->query_memory_info = iris_bufmgr_vram_size(screen->bufmgr) != 0;
459 caps->prefer_back_buffer_reuse = false;
460 caps->fbfetch = IRIS_MAX_DRAW_BUFFERS;
461 caps->fbfetch_coherent = devinfo->ver >= 9 && devinfo->ver < 20;
462 caps->conservative_raster_inner_coverage =
463 caps->post_depth_coverage =
464 caps->shader_stencil_export =
465 caps->depth_clip_disable_separate =
466 caps->fragment_shader_interlock =
467 caps->atomic_float_minmax = devinfo->ver >= 9;
468 caps->depth_bounds_test = devinfo->ver >= 12;
469 caps->max_dual_source_render_targets = 1;
470 caps->max_render_targets = IRIS_MAX_DRAW_BUFFERS;
471 caps->max_texture_2d_size = 16384;
472 caps->max_texture_cube_levels = IRIS_MAX_MIPLEVELS; /* 16384x16384 */
473 caps->max_texture_3d_levels = 12; /* 2048x2048 */
474 caps->max_stream_output_buffers = 4;
475 caps->max_texture_array_layers = 2048;
476 caps->max_stream_output_separate_components =
477 IRIS_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
478 caps->max_stream_output_interleaved_components = IRIS_MAX_SOL_BINDINGS;
479 caps->glsl_feature_level =
480 caps->glsl_feature_level_compatibility = 460;
481 /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
482 caps->constant_buffer_offset_alignment = 32;
483 caps->min_map_buffer_alignment = IRIS_MAP_BUFFER_ALIGNMENT;
484 caps->shader_buffer_offset_alignment = 4;
485 caps->max_shader_buffer_size = 1 << 27;
486 caps->texture_buffer_offset_alignment = 16; // XXX: u_screen says 256 is the minimum value...
487 caps->linear_image_pitch_alignment = 1;
488 caps->linear_image_base_address_alignment = 1;
489 caps->texture_transfer_modes = PIPE_TEXTURE_TRANSFER_BLIT;
490 caps->max_texel_buffer_elements = IRIS_MAX_TEXTURE_BUFFER_SIZE;
491 caps->max_viewports = 16;
492 caps->max_geometry_output_vertices = 256;
493 caps->max_geometry_total_output_components = 1024;
494 caps->max_gs_invocations = 32;
495 caps->max_texture_gather_components = 4;
496 caps->min_texture_gather_offset = -32;
497 caps->max_texture_gather_offset = 31;
498 caps->max_vertex_streams = 4;
499 caps->vendor_id = 0x8086;
500 caps->device_id = screen->devinfo->pci_device_id;
501 caps->video_memory = iris_get_video_memory(screen);
502 caps->max_shader_patch_varyings =
503 caps->max_varyings = 32;
504 /* We want immediate arrays to go get uploaded as nir->constant_data by
505 * nir_opt_large_constants() instead.
506 */
507 caps->prefer_imm_arrays_as_constbuf = false;
508 /* AMD_pinned_memory assumes the flexibility of using client memory
509 * for any buffer (incl. vertex buffers) which rules out the prospect
510 * of using snooped buffers, as using snooped buffers without
511 * cogniscience is likely to be detrimental to performance and require
512 * extensive checking in the driver for correctness, e.g. to prevent
513 * illegal snoop <-> snoop transfers.
514 */
515 caps->resource_from_user_memory = devinfo->has_llc;
516 caps->throttle = !screen->driconf.disable_throttling;
517
518 caps->context_priority_mask =
519 PIPE_CONTEXT_PRIORITY_LOW |
520 PIPE_CONTEXT_PRIORITY_MEDIUM |
521 PIPE_CONTEXT_PRIORITY_HIGH;
522
523 caps->frontend_noop = true;
524
525 // XXX: don't hardcode 00:00:02.0 PCI here
526 caps->pci_group = 0;
527 caps->pci_bus = 0;
528 caps->pci_device = 2;
529 caps->pci_function = 0;
530
531 caps->opencl_integer_functions =
532 caps->integer_multiply_32x16 = true;
533
534 /* Internal details of VF cache make this optimization harmful on GFX
535 * version 8 and 9, because generated VERTEX_BUFFER_STATEs are cached
536 * separately.
537 */
538 caps->allow_dynamic_vao_fastpath = devinfo->ver >= 11;
539
540 caps->timer_resolution = DIV_ROUND_UP(1000000000ull, devinfo->timestamp_frequency);
541
542 caps->device_protected_context =
543 screen->kernel_features & KERNEL_HAS_PROTECTED_CONTEXT;
544
545 caps->astc_void_extents_need_denorm_flush =
546 devinfo->ver == 9 && !intel_device_info_is_9lp(devinfo);
547
548 caps->min_line_width =
549 caps->min_line_width_aa =
550 caps->min_point_size =
551 caps->min_point_size_aa = 1;
552
553 caps->point_size_granularity =
554 caps->line_width_granularity = 0.1;
555
556 caps->max_line_width =
557 caps->max_line_width_aa = 7.375f;
558
559 caps->max_point_size =
560 caps->max_point_size_aa = 255.0f;
561
562 caps->max_texture_anisotropy = 16.0f;
563 caps->max_texture_lod_bias = 15.0f;
564 }
565
566 static uint64_t
iris_get_timestamp(struct pipe_screen * pscreen)567 iris_get_timestamp(struct pipe_screen *pscreen)
568 {
569 struct iris_screen *screen = (struct iris_screen *) pscreen;
570 uint64_t result;
571
572 if (!intel_gem_read_render_timestamp(iris_bufmgr_get_fd(screen->bufmgr),
573 screen->devinfo->kmd_type, &result))
574 return 0;
575
576 result = intel_device_info_timebase_scale(screen->devinfo, result);
577
578 return result;
579 }
580
581 void
iris_screen_destroy(struct iris_screen * screen)582 iris_screen_destroy(struct iris_screen *screen)
583 {
584 intel_perf_free(screen->perf_cfg);
585 iris_destroy_screen_measure(screen);
586 util_queue_destroy(&screen->shader_compiler_queue);
587 glsl_type_singleton_decref();
588 iris_bo_unreference(screen->workaround_bo);
589 iris_bo_unreference(screen->breakpoint_bo);
590 u_transfer_helper_destroy(screen->base.transfer_helper);
591 iris_bufmgr_unref(screen->bufmgr);
592 disk_cache_destroy(screen->disk_cache);
593 close(screen->winsys_fd);
594 ralloc_free(screen);
595 }
596
597 static void
iris_screen_unref(struct pipe_screen * pscreen)598 iris_screen_unref(struct pipe_screen *pscreen)
599 {
600 iris_pscreen_unref(pscreen);
601 }
602
603 static void
iris_query_memory_info(struct pipe_screen * pscreen,struct pipe_memory_info * info)604 iris_query_memory_info(struct pipe_screen *pscreen,
605 struct pipe_memory_info *info)
606 {
607 struct iris_screen *screen = (struct iris_screen *)pscreen;
608 struct intel_device_info di;
609 memcpy(&di, screen->devinfo, sizeof(di));
610
611 if (!intel_device_info_update_memory_info(&di, screen->fd))
612 return;
613
614 info->total_device_memory =
615 (di.mem.vram.mappable.size + di.mem.vram.unmappable.size) / 1024;
616 info->avail_device_memory =
617 (di.mem.vram.mappable.free + di.mem.vram.unmappable.free) / 1024;
618 info->total_staging_memory = di.mem.sram.mappable.size / 1024;
619 info->avail_staging_memory = di.mem.sram.mappable.free / 1024;
620
621 /* Neither kernel gives us any way to calculate this information */
622 info->device_memory_evicted = 0;
623 info->nr_device_memory_evictions = 0;
624 }
625
626 static struct disk_cache *
iris_get_disk_shader_cache(struct pipe_screen * pscreen)627 iris_get_disk_shader_cache(struct pipe_screen *pscreen)
628 {
629 struct iris_screen *screen = (struct iris_screen *) pscreen;
630 return screen->disk_cache;
631 }
632
633 static const struct intel_l3_config *
iris_get_default_l3_config(const struct intel_device_info * devinfo,bool compute)634 iris_get_default_l3_config(const struct intel_device_info *devinfo,
635 bool compute)
636 {
637 bool wants_dc_cache = true;
638 bool has_slm = compute;
639 const struct intel_l3_weights w =
640 intel_get_default_l3_weights(devinfo, wants_dc_cache, has_slm);
641 return intel_get_l3_config(devinfo, w);
642 }
643
644 static void
iris_detect_kernel_features(struct iris_screen * screen)645 iris_detect_kernel_features(struct iris_screen *screen)
646 {
647 const struct intel_device_info *devinfo = screen->devinfo;
648 /* Kernel 5.2+ */
649 if (intel_gem_supports_syncobj_wait(screen->fd))
650 screen->kernel_features |= KERNEL_HAS_WAIT_FOR_SUBMIT;
651 if (intel_gem_supports_protected_context(screen->fd, devinfo->kmd_type))
652 screen->kernel_features |= KERNEL_HAS_PROTECTED_CONTEXT;
653 }
654
655 static bool
iris_init_identifier_bo(struct iris_screen * screen)656 iris_init_identifier_bo(struct iris_screen *screen)
657 {
658 void *bo_map;
659
660 bo_map = iris_bo_map(NULL, screen->workaround_bo, MAP_READ | MAP_WRITE);
661 if (!bo_map)
662 return false;
663
664 assert(iris_bo_is_real(screen->workaround_bo));
665
666 screen->workaround_address = (struct iris_address) {
667 .bo = screen->workaround_bo,
668 .offset = ALIGN(
669 intel_debug_write_identifiers(bo_map, 4096, "Iris"), 32),
670 };
671
672 iris_bo_unmap(screen->workaround_bo);
673
674 return true;
675 }
676
677 static int
iris_screen_get_fd(struct pipe_screen * pscreen)678 iris_screen_get_fd(struct pipe_screen *pscreen)
679 {
680 struct iris_screen *screen = (struct iris_screen *) pscreen;
681
682 return screen->winsys_fd;
683 }
684
685 static void
iris_set_damage_region(struct pipe_screen * pscreen,struct pipe_resource * pres,unsigned int nrects,const struct pipe_box * rects)686 iris_set_damage_region(struct pipe_screen *pscreen, struct pipe_resource *pres,
687 unsigned int nrects, const struct pipe_box *rects)
688 {
689 struct iris_resource *res = (struct iris_resource *)pres;
690
691 res->use_damage = nrects > 0;
692 if (!res->use_damage)
693 return;
694
695 res->damage.x = INT32_MAX;
696 res->damage.y = INT32_MAX;
697 res->damage.width = 0;
698 res->damage.height = 0;
699
700 for (unsigned i = 0; i < nrects; i++) {
701 res->damage.x = MIN2(res->damage.x, rects[i].x);
702 res->damage.y = MIN2(res->damage.y, rects[i].y);
703 res->damage.width = MAX2(res->damage.width, rects[i].width + rects[i].x);
704 res->damage.height = MAX2(res->damage.height, rects[i].height + rects[i].y);
705
706 if (unlikely(res->damage.x == 0 &&
707 res->damage.y == 0 &&
708 res->damage.width == res->base.b.width0 &&
709 res->damage.height == res->base.b.height0))
710 break;
711 }
712
713 res->damage.x = MAX2(res->damage.x, 0);
714 res->damage.y = MAX2(res->damage.y, 0);
715 res->damage.width = MIN2(res->damage.width, res->base.b.width0);
716 res->damage.height = MIN2(res->damage.height, res->base.b.height0);
717 }
718
719 struct pipe_screen *
iris_screen_create(int fd,const struct pipe_screen_config * config)720 iris_screen_create(int fd, const struct pipe_screen_config *config)
721 {
722 struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
723 if (!screen)
724 return NULL;
725
726 driParseConfigFiles(config->options, config->options_info, 0, "iris",
727 NULL, NULL, NULL, 0, NULL, 0);
728
729 bool bo_reuse = false;
730 int bo_reuse_mode = driQueryOptioni(config->options, "bo_reuse");
731 switch (bo_reuse_mode) {
732 case DRI_CONF_BO_REUSE_DISABLED:
733 break;
734 case DRI_CONF_BO_REUSE_ALL:
735 bo_reuse = true;
736 break;
737 }
738
739 process_intel_debug_variable();
740
741 screen->bufmgr = iris_bufmgr_get_for_fd(fd, bo_reuse);
742 if (!screen->bufmgr)
743 return NULL;
744
745 screen->devinfo = iris_bufmgr_get_device_info(screen->bufmgr);
746 p_atomic_set(&screen->refcount, 1);
747
748 /* Here are the i915 features we need for Iris (in chronological order) :
749 * - I915_PARAM_HAS_EXEC_NO_RELOC (3.10)
750 * - I915_PARAM_HAS_EXEC_HANDLE_LUT (3.10)
751 * - I915_PARAM_HAS_EXEC_BATCH_FIRST (4.13)
752 * - I915_PARAM_HAS_EXEC_FENCE_ARRAY (4.14)
753 * - I915_PARAM_HAS_CONTEXT_ISOLATION (4.16)
754 *
755 * Checking the last feature availability will include all previous ones.
756 */
757 if (!screen->devinfo->has_context_isolation) {
758 debug_error("Kernel is too old (4.16+ required) or unusable for Iris.\n"
759 "Check your dmesg logs for loading failures.\n");
760 return NULL;
761 }
762
763 screen->fd = iris_bufmgr_get_fd(screen->bufmgr);
764 screen->winsys_fd = os_dupfd_cloexec(fd);
765
766 screen->id = iris_bufmgr_create_screen_id(screen->bufmgr);
767
768 screen->workaround_bo =
769 iris_bo_alloc(screen->bufmgr, "workaround", 4096, 4096,
770 IRIS_MEMZONE_OTHER, BO_ALLOC_NO_SUBALLOC | BO_ALLOC_CAPTURE);
771 if (!screen->workaround_bo)
772 return NULL;
773
774 screen->breakpoint_bo = iris_bo_alloc(screen->bufmgr, "breakpoint", 4, 4,
775 IRIS_MEMZONE_OTHER, BO_ALLOC_ZEROED);
776 if (!screen->breakpoint_bo)
777 return NULL;
778
779 if (!iris_init_identifier_bo(screen))
780 return NULL;
781
782 screen->driconf.dual_color_blend_by_location =
783 driQueryOptionb(config->options, "dual_color_blend_by_location");
784 screen->driconf.disable_throttling =
785 driQueryOptionb(config->options, "disable_throttling");
786 screen->driconf.always_flush_cache = INTEL_DEBUG(DEBUG_STALL) ||
787 driQueryOptionb(config->options, "always_flush_cache");
788 screen->driconf.sync_compile =
789 driQueryOptionb(config->options, "sync_compile");
790 screen->driconf.limit_trig_input_range =
791 driQueryOptionb(config->options, "limit_trig_input_range");
792 screen->driconf.lower_depth_range_rate =
793 driQueryOptionf(config->options, "lower_depth_range_rate");
794 screen->driconf.intel_enable_wa_14018912822 =
795 driQueryOptionb(config->options, "intel_enable_wa_14018912822");
796 screen->driconf.enable_tbimr =
797 driQueryOptionb(config->options, "intel_tbimr");
798 screen->driconf.generated_indirect_threshold =
799 driQueryOptioni(config->options, "generated_indirect_threshold");
800
801 screen->precompile = debug_get_bool_option("shader_precompile", true);
802
803 isl_device_init(&screen->isl_dev, screen->devinfo);
804 screen->isl_dev.dummy_aux_address = iris_bufmgr_get_dummy_aux_address(screen->bufmgr);
805
806 screen->isl_dev.sampler_route_to_lsc =
807 driQueryOptionb(config->options, "intel_sampler_route_to_lsc");
808
809 iris_compiler_init(screen);
810
811 screen->l3_config_3d = iris_get_default_l3_config(screen->devinfo, false);
812 screen->l3_config_cs = iris_get_default_l3_config(screen->devinfo, true);
813
814 iris_disk_cache_init(screen);
815
816 slab_create_parent(&screen->transfer_pool,
817 sizeof(struct iris_transfer), 64);
818
819 iris_detect_kernel_features(screen);
820
821 struct pipe_screen *pscreen = &screen->base;
822
823 iris_init_screen_fence_functions(pscreen);
824 iris_init_screen_resource_functions(pscreen);
825 iris_init_screen_measure(screen);
826
827 pscreen->destroy = iris_screen_unref;
828 pscreen->get_name = iris_get_name;
829 pscreen->get_vendor = iris_get_vendor;
830 pscreen->get_device_vendor = iris_get_device_vendor;
831 pscreen->get_cl_cts_version = iris_get_cl_cts_version;
832 pscreen->get_screen_fd = iris_screen_get_fd;
833 pscreen->get_shader_param = iris_get_shader_param;
834 pscreen->get_compute_param = iris_get_compute_param;
835 pscreen->get_compiler_options = iris_get_compiler_options;
836 pscreen->get_device_uuid = iris_get_device_uuid;
837 pscreen->get_driver_uuid = iris_get_driver_uuid;
838 pscreen->get_disk_shader_cache = iris_get_disk_shader_cache;
839 pscreen->is_format_supported = iris_is_format_supported;
840 pscreen->context_create = iris_create_context;
841 pscreen->get_timestamp = iris_get_timestamp;
842 pscreen->query_memory_info = iris_query_memory_info;
843 pscreen->get_driver_query_group_info = iris_get_monitor_group_info;
844 pscreen->get_driver_query_info = iris_get_monitor_info;
845 pscreen->set_damage_region = iris_set_damage_region;
846 iris_init_screen_program_functions(pscreen);
847
848 iris_init_screen_caps(screen);
849
850 genX_call(screen->devinfo, init_screen_state, screen);
851 genX_call(screen->devinfo, init_screen_gen_state, screen);
852
853 glsl_type_singleton_init_or_ref();
854
855 intel_driver_ds_init();
856
857 /* FINISHME: Big core vs little core (for CPUs that have both kinds of
858 * cores) and, possibly, thread vs core should be considered here too.
859 */
860 unsigned compiler_threads = 1;
861 const struct util_cpu_caps_t *caps = util_get_cpu_caps();
862 unsigned hw_threads = caps->nr_cpus;
863
864 if (hw_threads >= 12) {
865 compiler_threads = hw_threads * 3 / 4;
866 } else if (hw_threads >= 6) {
867 compiler_threads = hw_threads - 2;
868 } else if (hw_threads >= 2) {
869 compiler_threads = hw_threads - 1;
870 }
871
872 if (!util_queue_init(&screen->shader_compiler_queue,
873 "sh", 64, compiler_threads,
874 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
875 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY,
876 NULL)) {
877 iris_screen_destroy(screen);
878 return NULL;
879 }
880
881 return pscreen;
882 }
883