1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <arch/io.h>
4 #include <cf9_reset.h>
5 #include <reset.h>
6 #include <soc/northbridge.h>
7 #include <soc/pci_devs.h>
8 #include <device/pci_ops.h>
9 #include <soc/southbridge.h>
10 #include <amdblocks/acpimmio.h>
11 #include <amdblocks/reset.h>
12
set_warm_reset_flag(void)13 void set_warm_reset_flag(void)
14 {
15 u32 htic;
16 htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);
17 htic |= HTIC_COLD_RST_DET;
18 pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic);
19 }
20
is_warm_reset(void)21 int is_warm_reset(void)
22 {
23 u32 htic;
24 htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);
25 return !!(htic & HTIC_COLD_RST_DET);
26 }
27
28 /* Clear bits 5, 9 & 10, used to signal the reset type */
clear_bios_reset(void)29 static void clear_bios_reset(void)
30 {
31 u32 htic;
32 htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);
33 htic &= ~HTIC_BIOSR_DETECT;
34 pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic);
35 }
36
do_cold_reset(void)37 void do_cold_reset(void)
38 {
39 clear_bios_reset();
40
41 /* De-assert and then assert all PwrGood signals on CF9 reset. */
42 pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
43 TOGGLE_ALL_PWR_GOOD);
44 outb(RST_CPU | SYS_RST, RST_CNT);
45 }
46
do_warm_reset(void)47 void do_warm_reset(void)
48 {
49 set_warm_reset_flag();
50 clear_bios_reset();
51
52 /* Assert reset signals only. */
53 outb(RST_CPU | SYS_RST, RST_CNT);
54 }
55
do_board_reset(void)56 void do_board_reset(void)
57 {
58 /* TODO: Would a warm_reset() suffice? */
59 do_cold_reset();
60 }
61