1 // Copyright 2019 The Pigweed Authors 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); you may not 4 // use this file except in compliance with the License. You may obtain a copy of 5 // the License at 6 // 7 // https://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 11 // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 12 // License for the specific language governing permissions and limitations under 13 // the License. 14 #pragma once 15 16 #ifdef __cplusplus 17 18 #include <cstdint> 19 20 #include "pw_preprocessor/arch.h" 21 #include "pw_preprocessor/compiler.h" 22 23 namespace pw::cpu_exception::cortex_m { 24 25 // The PC, LR, and PSR registers are not captured when the program stack 26 // pointer is in an MPU-protected or otherwise invalid memory region. In 27 // these situations, the registers are set to 0xFFFF'FFFF to indicate they 28 // are invalid. 29 // 30 // 0xFFFFFFFF is an illegal LR value, which is why it was selected for 31 // this purpose. PC and PSR values of 0xFFFFFFFF are dubious too, so this 32 // constant is clear enough at suggesting that the registers weren't 33 // properly captured. 34 inline constexpr uintptr_t kUndefinedPcLrOrPsrRegValue = 0xFFFF'FFFF; 35 36 // This is dictated by ARMv7-M architecture. Do not change. 37 struct ExceptionRegisters { 38 uint32_t r0; 39 uint32_t r1; 40 uint32_t r2; 41 uint32_t r3; 42 uint32_t r12; 43 uint32_t lr; // Link register, note this may be invalid. 44 uint32_t pc; // Program counter, note this may be invalid. 45 uint32_t psr; // Program status register, note this may be invalid. 46 }; 47 static_assert(sizeof(ExceptionRegisters) == (sizeof(uint32_t) * 8), 48 "There's unexpected padding."); 49 50 // This is dictated by ARMv7-M architecture. Do not change. 51 struct ExceptionRegistersFpu { 52 uint32_t s0; 53 uint32_t s1; 54 uint32_t s2; 55 uint32_t s3; 56 uint32_t s4; 57 uint32_t s5; 58 uint32_t s6; 59 uint32_t s7; 60 uint32_t s8; 61 uint32_t s9; 62 uint32_t s10; 63 uint32_t s11; 64 uint32_t s12; 65 uint32_t s13; 66 uint32_t s14; 67 uint32_t s15; 68 uint32_t fpscr; 69 uint32_t reserved; 70 }; 71 static_assert(sizeof(ExceptionRegistersFpu) == (sizeof(uint32_t) * 18), 72 "There's unexpected padding."); 73 74 // Bit in the PSR that indicates CPU added an extra word on the stack to 75 // align it during context save for an exception. 76 inline constexpr uint32_t kPsrExtraStackAlignBit = (1 << 9); 77 78 // This is dictated by this module, and shouldn't change often. 79 // Note that the order of entries in this struct is very important (as the 80 // values are populated in assembly). 81 // 82 // NOTE: Memory mapped registers are NOT restored upon fault return! 83 struct ExtraRegisters { 84 // Memory mapped registers. 85 #if !_PW_ARCH_ARM_V6M 86 uint32_t cfsr; 87 uint32_t mmfar; 88 uint32_t bfar; 89 #endif // !_PW_ARCH_ARM_V6M 90 uint32_t icsr; 91 #if !_PW_ARCH_ARM_V6M 92 uint32_t hfsr; 93 #endif // !_PW_ARCH_ARM_V6M 94 uint32_t shcsr; 95 // Special registers. 96 uint32_t exc_return; 97 uint32_t msp; 98 uint32_t psp; 99 uint32_t control; 100 #if _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE 101 uint32_t msplim; 102 uint32_t psplim; 103 #endif // _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE 104 // General purpose registers. 105 uint32_t r4; 106 uint32_t r5; 107 uint32_t r6; 108 uint32_t r7; 109 uint32_t r8; 110 uint32_t r9; 111 uint32_t r10; 112 uint32_t r11; 113 }; 114 static_assert(sizeof(ExtraRegisters) == 115 #if _PW_ARCH_ARM_V6M 116 (sizeof(uint32_t) * 14), 117 #elif _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE 118 (sizeof(uint32_t) * 20), 119 #else // !_PW_ARCH_ARM_V8M_MAINLINE && ! _PW_ARCH_ARM_V8_1M_MAINLINE 120 (sizeof(uint32_t) * 18), 121 #endif // _PW_ARCH_ARM_V8M_MAINLINE || _PW_ARCH_ARM_V8_1M_MAINLINE 122 "There's unexpected padding."); 123 124 } // namespace pw::cpu_exception::cortex_m 125 126 struct pw_cpu_exception_State { 127 pw::cpu_exception::cortex_m::ExtraRegisters extended; 128 pw::cpu_exception::cortex_m::ExceptionRegisters base; 129 // TODO(amontanez): FPU registers may or may not be here as well. Make the 130 // availability of the FPU registers a compile-time configuration when FPU 131 // register support is added. 132 }; 133 134 #else // !__cplusplus 135 136 typedef struct pw_cpu_exception_State pw_cpu_exception_State; 137 138 #endif // __cplusplus 139