1 /*
2 * Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <common/fdt_wrappers.h>
10 #include <common/runtime_svc.h>
11 #include <libfdt.h>
12 #include <smccc_helpers.h>
13
14 /* default platform version is 0.0 */
15 static int platform_version_major;
16 static int platform_version_minor;
17
18 #define SMC_FASTCALL 0x80000000
19 #define SMC64_FUNCTION (SMC_FASTCALL | 0x40000000)
20 #define SIP_FUNCTION (SMC64_FUNCTION | 0x02000000)
21 #define SIP_FUNCTION_ID(n) (SIP_FUNCTION | (n))
22
23 /*
24 * We do not use SMCCC_ARCH_SOC_ID here because qemu_sbsa is virtual platform
25 * which uses SoC present in QEMU. And they can change on their own while we
26 * need version of whole 'virtual hardware platform'.
27 */
28 #define SIP_SVC_VERSION SIP_FUNCTION_ID(1)
29 #define SIP_SVC_GET_GIC SIP_FUNCTION_ID(100)
30 #define SIP_SVC_GET_GIC_ITS SIP_FUNCTION_ID(101)
31 #define SIP_SVC_GET_CPU_COUNT SIP_FUNCTION_ID(200)
32 #define SIP_SVC_GET_CPU_NODE SIP_FUNCTION_ID(201)
33 #define SIP_SVC_GET_CPU_TOPOLOGY SIP_FUNCTION_ID(202)
34 #define SIP_SVC_GET_MEMORY_NODE_COUNT SIP_FUNCTION_ID(300)
35 #define SIP_SVC_GET_MEMORY_NODE SIP_FUNCTION_ID(301)
36
37 static uint64_t gic_its_addr;
38
39 typedef struct {
40 uint32_t nodeid;
41 uint32_t mpidr;
42 } cpu_data;
43
44 typedef struct{
45 uint32_t nodeid;
46 uint64_t addr_base;
47 uint64_t addr_size;
48 } memory_data;
49
50 /*
51 * sockets: the number of sockets on sbsa-ref platform.
52 * clusters: the number of clusters in one socket.
53 * cores: the number of cores in one cluster.
54 * threads: the number of threads in one core.
55 */
56 typedef struct {
57 uint32_t sockets;
58 uint32_t clusters;
59 uint32_t cores;
60 uint32_t threads;
61 } cpu_topology;
62
63 static struct {
64 uint32_t num_cpus;
65 uint32_t num_memnodes;
66 cpu_data cpu[PLATFORM_CORE_COUNT];
67 cpu_topology cpu_topo;
68 memory_data memory[PLAT_MAX_MEM_NODES];
69 } dynamic_platform_info;
70
71 void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base);
72 uintptr_t sbsa_get_gicd(void);
73 uintptr_t sbsa_get_gicr(void);
74
75 /*
76 * QEMU provides us with minimal information about hardware platform using
77 * minimalistic DeviceTree. This is not a Linux DeviceTree. It is not even
78 * a firmware DeviceTree.
79 *
80 * It is information passed from QEMU to describe the information a hardware
81 * platform would have other mechanisms to discover at runtime, that are
82 * affected by the QEMU command line.
83 *
84 * Ultimately this device tree will be replaced by IPC calls to an emulated SCP.
85 * And when we do that, we won't then have to rewrite Normal world firmware to
86 * cope.
87 */
88
read_cpu_topology_from_dt(void * dtb)89 static void read_cpu_topology_from_dt(void *dtb)
90 {
91 int node;
92
93 /*
94 * QEMU gives us this DeviceTree node when we config:
95 * -smp 16,sockets=2,clusters=2,cores=2,threads=2
96 *
97 * topology {
98 * threads = <0x02>;
99 * cores = <0x02>;
100 * clusters = <0x02>;
101 * sockets = <0x02>;
102 * };
103 */
104
105 node = fdt_path_offset(dtb, "/cpus/topology");
106 if (node > 0) {
107 dynamic_platform_info.cpu_topo.sockets =
108 fdt_read_uint32_default(dtb, node, "sockets", 0);
109 dynamic_platform_info.cpu_topo.clusters =
110 fdt_read_uint32_default(dtb, node, "clusters", 0);
111 dynamic_platform_info.cpu_topo.cores =
112 fdt_read_uint32_default(dtb, node, "cores", 0);
113 dynamic_platform_info.cpu_topo.threads =
114 fdt_read_uint32_default(dtb, node, "threads", 0);
115 }
116
117 INFO("Cpu topology: sockets: %d, clusters: %d, cores: %d, threads: %d\n",
118 dynamic_platform_info.cpu_topo.sockets,
119 dynamic_platform_info.cpu_topo.clusters,
120 dynamic_platform_info.cpu_topo.cores,
121 dynamic_platform_info.cpu_topo.threads);
122 }
123
read_cpuinfo_from_dt(void * dtb)124 void read_cpuinfo_from_dt(void *dtb)
125 {
126 int node;
127 int prev;
128 int cpu = 0;
129 uintptr_t mpidr;
130
131 /*
132 * QEMU gives us this DeviceTree node:
133 * numa-node-id entries are only when NUMA config is used
134 *
135 * cpus {
136 * #size-cells = <0x00>;
137 * #address-cells = <0x02>;
138 *
139 * cpu@0 {
140 * numa-node-id = <0x00>;
141 * reg = <0x00 0x00>;
142 * };
143 *
144 * cpu@1 {
145 * numa-node-id = <0x03>;
146 * reg = <0x00 0x01>;
147 * };
148 * };
149 */
150 node = fdt_path_offset(dtb, "/cpus");
151 if (node < 0) {
152 ERROR("No information about cpus in DeviceTree.\n");
153 panic();
154 }
155
156 /*
157 * QEMU numbers cpus from 0 and there can be /cpus/cpu-map present so we
158 * cannot use fdt_first_subnode() here
159 */
160 node = fdt_path_offset(dtb, "/cpus/cpu@0");
161
162 while (node > 0) {
163 if (fdt_getprop(dtb, node, "reg", NULL)) {
164 fdt_get_reg_props_by_index(dtb, node, 0, &mpidr, NULL);
165 } else {
166 ERROR("Incomplete information for cpu %d in DeviceTree.\n", cpu);
167 panic();
168 }
169
170 dynamic_platform_info.cpu[cpu].mpidr = mpidr;
171 dynamic_platform_info.cpu[cpu].nodeid =
172 fdt_read_uint32_default(dtb, node, "numa-node-id", 0);
173
174 INFO("CPU %d: node-id: %d, mpidr: %ld\n", cpu,
175 dynamic_platform_info.cpu[cpu].nodeid, mpidr);
176
177 cpu++;
178
179 prev = node;
180 node = fdt_next_subnode(dtb, prev);
181 }
182
183 dynamic_platform_info.num_cpus = cpu;
184 INFO("Found %d cpus\n", dynamic_platform_info.num_cpus);
185
186 read_cpu_topology_from_dt(dtb);
187 }
188
read_meminfo_from_dt(void * dtb)189 void read_meminfo_from_dt(void *dtb)
190 {
191 const fdt32_t *prop;
192 const char *type;
193 int prev, node;
194 int len;
195 uint32_t memnode = 0;
196 uint32_t higher_value, lower_value;
197 uint64_t cur_base, cur_size;
198
199 /*
200 * QEMU gives us this DeviceTree node:
201 *
202 * memory@100c0000000 {
203 * numa-node-id = <0x01>;
204 * reg = <0x100 0xc0000000 0x00 0x40000000>;
205 * device_type = "memory";
206 * };
207 *
208 * memory@10000000000 {
209 * numa-node-id = <0x00>;
210 * reg = <0x100 0x00 0x00 0xc0000000>;
211 * device_type = "memory";
212 * }
213 */
214
215 for (prev = 0;; prev = node) {
216 node = fdt_next_node(dtb, prev, NULL);
217 if (node < 0) {
218 break;
219 }
220
221 type = fdt_getprop(dtb, node, "device_type", &len);
222 if (type && strncmp(type, "memory", len) == 0) {
223 dynamic_platform_info.memory[memnode].nodeid =
224 fdt_read_uint32_default(dtb, node, "numa-node-id", 0);
225
226 /*
227 * Get the 'reg' property of this node and
228 * assume two 8 bytes for base and size.
229 */
230 prop = fdt_getprop(dtb, node, "reg", &len);
231 if (prop != 0 && len == (2 * sizeof(int64_t))) {
232 higher_value = fdt32_to_cpu(*prop);
233 lower_value = fdt32_to_cpu(*(prop + 1));
234 cur_base = (uint64_t)(lower_value | ((uint64_t)higher_value) << 32);
235
236 higher_value = fdt32_to_cpu(*(prop + 2));
237 lower_value = fdt32_to_cpu(*(prop + 3));
238 cur_size = (uint64_t)(lower_value | ((uint64_t)higher_value) << 32);
239
240 dynamic_platform_info.memory[memnode].addr_base = cur_base;
241 dynamic_platform_info.memory[memnode].addr_size = cur_size;
242
243 INFO("RAM %d: node-id: %d, address: 0x%lx - 0x%lx\n",
244 memnode,
245 dynamic_platform_info.memory[memnode].nodeid,
246 dynamic_platform_info.memory[memnode].addr_base,
247 dynamic_platform_info.memory[memnode].addr_base +
248 dynamic_platform_info.memory[memnode].addr_size - 1);
249 }
250
251 memnode++;
252 }
253 }
254
255 dynamic_platform_info.num_memnodes = memnode;
256 }
257
read_platform_config_from_dt(void * dtb)258 void read_platform_config_from_dt(void *dtb)
259 {
260 int node;
261 const fdt64_t *data;
262 int err;
263 uintptr_t gicd_base;
264 uintptr_t gicr_base;
265
266 /*
267 * QEMU gives us this DeviceTree node:
268 *
269 * intc {
270 * reg = < 0x00 0x40060000 0x00 0x10000
271 * 0x00 0x40080000 0x00 0x4000000>;
272 * its {
273 * reg = <0x00 0x44081000 0x00 0x20000>;
274 * };
275 * };
276 */
277 node = fdt_path_offset(dtb, "/intc");
278 if (node < 0) {
279 return;
280 }
281
282 data = fdt_getprop(dtb, node, "reg", NULL);
283 if (data == NULL) {
284 return;
285 }
286
287 err = fdt_get_reg_props_by_index(dtb, node, 0, &gicd_base, NULL);
288 if (err < 0) {
289 ERROR("Failed to read GICD reg property of GIC node\n");
290 return;
291 }
292 INFO("GICD base = 0x%lx\n", gicd_base);
293
294 err = fdt_get_reg_props_by_index(dtb, node, 1, &gicr_base, NULL);
295 if (err < 0) {
296 ERROR("Failed to read GICR reg property of GIC node\n");
297 return;
298 }
299 INFO("GICR base = 0x%lx\n", gicr_base);
300
301 sbsa_set_gic_bases(gicd_base, gicr_base);
302
303 node = fdt_path_offset(dtb, "/intc/its");
304 if (node < 0) {
305 return;
306 }
307
308 err = fdt_get_reg_props_by_index(dtb, node, 0, &gic_its_addr, NULL);
309 if (err < 0) {
310 ERROR("Failed to read GICI reg property of GIC node\n");
311 return;
312 }
313 INFO("GICI base = 0x%lx\n", gic_its_addr);
314 }
315
read_platform_version(void * dtb)316 void read_platform_version(void *dtb)
317 {
318 int node;
319
320 node = fdt_path_offset(dtb, "/");
321 if (node >= 0) {
322 platform_version_major =
323 fdt_read_uint32_default(dtb, node, "machine-version-major", 0);
324 platform_version_minor =
325 fdt_read_uint32_default(dtb, node, "machine-version-minor", 0);
326 }
327 }
328
sip_svc_init(void)329 void sip_svc_init(void)
330 {
331 /* Read DeviceTree data before MMU is enabled */
332
333 void *dtb = (void *)(uintptr_t)ARM_PRELOADED_DTB_BASE;
334 int err;
335
336 err = fdt_open_into(dtb, dtb, PLAT_QEMU_DT_MAX_SIZE);
337 if (err < 0) {
338 ERROR("Invalid Device Tree at %p: error %d\n", dtb, err);
339 return;
340 }
341
342 err = fdt_check_header(dtb);
343 if (err < 0) {
344 ERROR("Invalid DTB file passed\n");
345 return;
346 }
347
348 read_platform_version(dtb);
349 INFO("Platform version: %d.%d\n", platform_version_major, platform_version_minor);
350
351 read_platform_config_from_dt(dtb);
352 read_cpuinfo_from_dt(dtb);
353 read_meminfo_from_dt(dtb);
354 }
355
356 /*
357 * This function is responsible for handling all SiP calls from the NS world
358 */
sbsa_sip_smc_handler(uint32_t smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4,void * cookie,void * handle,u_register_t flags)359 uintptr_t sbsa_sip_smc_handler(uint32_t smc_fid,
360 u_register_t x1,
361 u_register_t x2,
362 u_register_t x3,
363 u_register_t x4,
364 void *cookie,
365 void *handle,
366 u_register_t flags)
367 {
368 uint32_t ns;
369 uint64_t index;
370
371 /* Determine which security state this SMC originated from */
372 ns = is_caller_non_secure(flags);
373 if (!ns) {
374 ERROR("%s: wrong world SMC (0x%x)\n", __func__, smc_fid);
375 SMC_RET1(handle, SMC_UNK);
376 }
377
378 switch (smc_fid) {
379 case SIP_SVC_VERSION:
380 INFO("Platform version requested\n");
381 SMC_RET3(handle, NULL, platform_version_major, platform_version_minor);
382
383 case SIP_SVC_GET_GIC:
384 SMC_RET3(handle, NULL, sbsa_get_gicd(), sbsa_get_gicr());
385
386 case SIP_SVC_GET_GIC_ITS:
387 SMC_RET2(handle, NULL, gic_its_addr);
388
389 case SIP_SVC_GET_CPU_COUNT:
390 SMC_RET2(handle, NULL, dynamic_platform_info.num_cpus);
391
392 case SIP_SVC_GET_CPU_NODE:
393 index = x1;
394 if (index < PLATFORM_CORE_COUNT) {
395 SMC_RET3(handle, NULL,
396 dynamic_platform_info.cpu[index].nodeid,
397 dynamic_platform_info.cpu[index].mpidr);
398 } else {
399 SMC_RET1(handle, SMC_ARCH_CALL_INVAL_PARAM);
400 }
401
402 case SIP_SVC_GET_CPU_TOPOLOGY:
403 if (dynamic_platform_info.cpu_topo.cores > 0) {
404 SMC_RET5(handle, NULL,
405 dynamic_platform_info.cpu_topo.sockets,
406 dynamic_platform_info.cpu_topo.clusters,
407 dynamic_platform_info.cpu_topo.cores,
408 dynamic_platform_info.cpu_topo.threads);
409 } else {
410 /* we do not know topology so we report SMC as unknown */
411 SMC_RET1(handle, SMC_UNK);
412 }
413
414 case SIP_SVC_GET_MEMORY_NODE_COUNT:
415 SMC_RET2(handle, NULL, dynamic_platform_info.num_memnodes);
416
417 case SIP_SVC_GET_MEMORY_NODE:
418 index = x1;
419 if (index < PLAT_MAX_MEM_NODES) {
420 SMC_RET4(handle, NULL,
421 dynamic_platform_info.memory[index].nodeid,
422 dynamic_platform_info.memory[index].addr_base,
423 dynamic_platform_info.memory[index].addr_size);
424 } else {
425 SMC_RET1(handle, SMC_ARCH_CALL_INVAL_PARAM);
426 }
427
428 default:
429 ERROR("%s: unhandled SMC (0x%x) (function id: %d)\n", __func__, smc_fid,
430 smc_fid - SIP_FUNCTION);
431 SMC_RET1(handle, SMC_UNK);
432 }
433 }
434
sbsa_sip_smc_setup(void)435 int sbsa_sip_smc_setup(void)
436 {
437 return 0;
438 }
439
440 /* Define a runtime service descriptor for fast SMC calls */
441 DECLARE_RT_SVC(
442 sbsa_sip_svc,
443 OEN_SIP_START,
444 OEN_SIP_END,
445 SMC_TYPE_FAST,
446 sbsa_sip_smc_setup,
447 sbsa_sip_smc_handler
448 );
449