| /external/vixl/test/aarch64/ |
| D | test-api-movprfx-aarch64.cc | 157 __ lsl(z4.VnS(), p1.Merging(), z4.VnS(), z4.VnS()); in TEST() local
160 __ lsl(z4.VnB(), p5.Merging(), z4.VnB(), z4.VnD()); in TEST() local
163 __ lsl(z11.VnD(), p4.Merging(), z11.VnD(), z11.VnD()); in TEST() local
734 __ lsl(z7.VnD(), p7.Merging(), z7.VnD(), 3); in TEST() local
737 __ lsl(z11.VnB(), p3.Merging(), z11.VnB(), z21.VnB()); in TEST() local
740 __ lsl(z31.VnH(), p7.Merging(), z31.VnH(), z21.VnD()); in TEST() local
743 __ lsl(z26.VnD(), p0.Merging(), z26.VnD(), z24.VnD()); in TEST() local
1449 __ lsl(z30.VnD(), p0.Merging(), z30.VnD(), 3); in TEST() local
1452 __ lsl(z28.VnS(), p2.Merging(), z28.VnS(), z6.VnS()); in TEST() local
1455 __ lsl(z15.VnH(), p6.Merging(), z15.VnH(), z3.VnD()); in TEST() local
[all …]
|
| D | test-trace-aarch64.cc | 230 __ lsl(w5, w6, 2); in GenerateTestSequenceBase() local
231 __ lsl(x7, x8, 3); in GenerateTestSequenceBase() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 30 lsl, enumerator
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 30 lsl, enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 30 lsl, enumerator
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 829 void lsl(const Register& rd, const Register& rn, unsigned shift) { in lsl() function
|
| D | assembler-sve-aarch64.cc | 252 void Assembler::lsl(const ZRegister& zd, in lsl() function in vixl::aarch64::Assembler
270 void Assembler::lsl(const ZRegister& zd, in lsl() function in vixl::aarch64::Assembler
407 void Assembler::lsl(const ZRegister& zd, const ZRegister& zn, int shift) { in lsl() function in vixl::aarch64::Assembler
414 void Assembler::lsl(const ZRegister& zd, in lsl() function in vixl::aarch64::Assembler
|
| /external/vixl/benchmarks/aarch32/ |
| D | asm-disasm-speed-test.cc | 475 __ lsl(r2, r8, r5); in Generate_3() local
483 __ lsl(r8, r8, r0); in Generate_3() local
2842 __ lsl(r1, r8, lr); in Generate_22() local
2850 __ lsl(r8, r8, r0); in Generate_22() local
4894 __ lsl(r9, r3, 5U); in Generate_37() local
5422 __ lsl(r4, sl, 5U); in Generate_41() local
5502 __ lsl(sl, r6, 5U); in Generate_42() local
5538 __ lsl(lr, r4, 5U); in Generate_42() local
5562 __ lsl(r7, fp, 5U); in Generate_42() local
8905 __ lsl(r0, r2, r1); in Generate_67() local
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2551 void lsl(Register rd, Register rm, const Operand& operand) { in lsl() function
2554 void lsl(Condition cond, Register rd, Register rm, const Operand& operand) { in lsl() function
2557 void lsl(EncodingSize size, in lsl() function
|
| D | assembler-aarch32.cc | 6717 void Assembler::lsl(Condition cond, in lsl() function in vixl::aarch32::Assembler
|
| D | disasm-aarch32.cc | 1842 void Disassembler::lsl(Condition cond, in lsl() function in vixl::aarch32::Disassembler
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 1736 void AssemblerARM32::lsl(const Operand *OpRd, const Operand *OpRm, in lsl() function in Ice::ARM32::AssemblerARM32
|