1 /*
2 * Copyright (c) 2009-2024 Broadcom. All Rights Reserved.
3 * The term “Broadcom” refers to Broadcom Inc.
4 * and/or its subsidiaries.
5 * SPDX-License-Identifier: MIT
6 */
7
8 /**
9 * @file
10 * Common definitions for the VMware SVGA winsys.
11 *
12 * @author Jose Fonseca <jfonseca@vmware.com>
13 */
14
15
16 #ifndef VMW_SCREEN_H_
17 #define VMW_SCREEN_H_
18
19
20 #include "util/compiler.h"
21 #include "pipe/p_state.h"
22
23 #include "svga_winsys.h"
24 #include "svga_surface.h"
25 #include "pipebuffer/pb_buffer_fenced.h"
26 #include "util/u_thread.h"
27 #include <sys/types.h>
28
29 #define VMW_GMR_POOL_SIZE (16*1024*1024)
30 #define VMW_QUERY_POOL_SIZE (8192)
31 #define VMW_DEBUG_FLUSH_STACK 10
32
33 /*
34 * Something big, but arbitrary. The kernel reports an error if it can't
35 * handle this, and the svga driver will resort to multiple partial
36 * uploads.
37 */
38 #define VMW_MAX_BUFFER_SIZE (512*1024*1024)
39
40 struct pb_manager;
41 struct vmw_region;
42
43 struct vmw_cap_3d {
44 bool has_cap;
45 SVGA3dDevCapResult result;
46 };
47
48 struct vmw_winsys_screen
49 {
50 struct svga_winsys_screen base;
51
52 struct {
53 int drm_fd;
54 uint32_t hwversion;
55 uint32_t num_cap_3d;
56 struct vmw_cap_3d *cap_3d;
57 uint64_t max_mob_memory;
58 uint64_t max_surface_memory;
59 uint64_t max_texture_size;
60 bool have_drm_2_6;
61 bool have_drm_2_9;
62 uint32_t drm_execbuf_version;
63 bool have_drm_2_15;
64 bool have_drm_2_16;
65 bool have_drm_2_17;
66 bool have_drm_2_18;
67 bool have_drm_2_19;
68 bool have_drm_2_20;
69 } ioctl;
70
71 struct {
72 struct pb_manager *dma_base;
73 struct pb_manager *dma_mm;
74 struct pb_manager *query_mm;
75 struct pb_manager *query_fenced;
76 struct pb_manager *dma_fenced;
77 struct pb_manager *dma_cache;
78 struct pb_manager *dma_slab;
79 struct pb_manager *dma_slab_fenced;
80 } pools;
81
82 struct pb_fence_ops *fence_ops;
83
84 struct svga_winsys_context *swc;
85
86 #ifdef VMX86_STATS
87 /*
88 * mksGuestStats TLS array; length must be power of two
89 */
90 struct {
91 void * stat_pages;
92 uint64_t stat_id;
93 uint32_t pid;
94 } mksstat_tls[64];
95
96 #endif
97 /*
98 * Screen instances
99 */
100 dev_t device;
101 int open_count;
102
103 cnd_t cs_cond;
104 mtx_t cs_mutex;
105
106 bool force_coherent;
107 bool cache_maps;
108 bool userspace_surface;
109 };
110
111
112 static inline struct vmw_winsys_screen *
vmw_winsys_screen(struct svga_winsys_screen * base)113 vmw_winsys_screen(struct svga_winsys_screen *base)
114 {
115 return (struct vmw_winsys_screen *)base;
116 }
117
118 static inline bool
vmw_has_userspace_surface(struct vmw_winsys_screen * vws)119 vmw_has_userspace_surface(struct vmw_winsys_screen *vws)
120 {
121 if (!vws->base.have_gb_objects || !vws->base.have_vgpu10)
122 return false;
123 return vws->userspace_surface;
124 }
125
126 /* */
127 uint32_t
128 vmw_region_size(struct vmw_region *region);
129
130 uint32
131 vmw_ioctl_context_create(struct vmw_winsys_screen *vws);
132
133 uint32
134 vmw_ioctl_extended_context_create(struct vmw_winsys_screen *vws,
135 bool vgpu10);
136
137 void
138 vmw_ioctl_context_destroy(struct vmw_winsys_screen *vws,
139 uint32 cid);
140
141 uint32
142 vmw_ioctl_surface_create(struct vmw_winsys_screen *vws,
143 SVGA3dSurface1Flags flags,
144 SVGA3dSurfaceFormat format,
145 unsigned usage,
146 SVGA3dSize size,
147 uint32 numFaces,
148 uint32 numMipLevels,
149 unsigned sampleCount);
150 uint32
151 vmw_ioctl_gb_surface_create(struct vmw_winsys_screen *vws,
152 SVGA3dSurfaceAllFlags flags,
153 SVGA3dSurfaceFormat format,
154 unsigned usage,
155 SVGA3dSize size,
156 uint32 numFaces,
157 uint32 numMipLevels,
158 unsigned sampleCount,
159 uint32 buffer_handle,
160 SVGA3dMSPattern multisamplePattern,
161 SVGA3dMSQualityLevel qualityLevel,
162 struct vmw_region **p_region);
163
164 int
165 vmw_ioctl_gb_surface_ref(struct vmw_winsys_screen *vws,
166 const struct winsys_handle *whandle,
167 SVGA3dSurfaceAllFlags *flags,
168 SVGA3dSurfaceFormat *format,
169 uint32_t *numMipLevels,
170 uint32_t *handle,
171 struct vmw_region **p_region);
172
173 void
174 vmw_ioctl_surface_destroy(struct vmw_winsys_screen *vws,
175 uint32 sid);
176
177 void
178 vmw_ioctl_command(struct vmw_winsys_screen *vws,
179 int32_t cid,
180 uint32_t throttle_us,
181 void *commands,
182 uint32_t size,
183 struct pipe_fence_handle **fence,
184 int32_t imported_fence_fd,
185 uint32_t flags);
186
187 struct vmw_region *
188 vmw_ioctl_region_create(struct vmw_winsys_screen *vws, uint32_t size);
189
190 void
191 vmw_ioctl_region_destroy(struct vmw_region *region);
192
193 struct SVGAGuestPtr
194 vmw_ioctl_region_ptr(struct vmw_region *region);
195
196 void *
197 vmw_ioctl_region_map(struct vmw_region *region);
198 void
199 vmw_ioctl_region_unmap(struct vmw_region *region);
200
201
202 int
203 vmw_ioctl_fence_finish(struct vmw_winsys_screen *vws,
204 uint32_t handle, uint32_t flags);
205
206 int
207 vmw_ioctl_fence_signalled(struct vmw_winsys_screen *vws,
208 uint32_t handle, uint32_t flags);
209
210 void
211 vmw_ioctl_fence_unref(struct vmw_winsys_screen *vws,
212 uint32_t handle);
213
214 uint32
215 vmw_ioctl_shader_create(struct vmw_winsys_screen *vws,
216 SVGA3dShaderType type,
217 uint32 code_len);
218 void
219 vmw_ioctl_shader_destroy(struct vmw_winsys_screen *vws, uint32 shid);
220
221 int
222 vmw_ioctl_syncforcpu(struct vmw_region *region,
223 bool dont_block,
224 bool readonly,
225 bool allow_cs);
226 void
227 vmw_ioctl_releasefromcpu(struct vmw_region *region,
228 bool readonly,
229 bool allow_cs);
230 /* Initialize parts of vmw_winsys_screen at startup:
231 */
232 bool vmw_ioctl_init(struct vmw_winsys_screen *vws);
233 bool vmw_pools_init(struct vmw_winsys_screen *vws);
234 bool vmw_query_pools_init(struct vmw_winsys_screen *vws);
235 bool vmw_winsys_screen_init_svga(struct vmw_winsys_screen *vws);
236
237 void vmw_ioctl_cleanup(struct vmw_winsys_screen *vws);
238 void vmw_pools_cleanup(struct vmw_winsys_screen *vws);
239
240 struct vmw_winsys_screen *vmw_winsys_create(int fd);
241 void vmw_winsys_destroy(struct vmw_winsys_screen *sws);
242 void vmw_winsys_screen_set_throttling(struct pipe_screen *screen,
243 uint32_t throttle_us);
244
245 struct pb_manager *
246 simple_fenced_bufmgr_create(struct pb_manager *provider,
247 struct pb_fence_ops *ops);
248 void
249 vmw_fences_signal(struct pb_fence_ops *fence_ops,
250 uint32_t signaled,
251 uint32_t emitted,
252 bool has_emitted);
253
254 struct svga_winsys_gb_shader *
255 vmw_svga_winsys_shader_create(struct svga_winsys_screen *sws,
256 SVGA3dShaderType type,
257 const uint32 *bytecode,
258 uint32 bytecodeLen);
259 void
260 vmw_svga_winsys_shader_destroy(struct svga_winsys_screen *sws,
261 struct svga_winsys_gb_shader *shader);
262
263 size_t
264 vmw_svga_winsys_stats_len(void);
265
266 #endif /* VMW_SCREEN_H_ */
267