1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <mainboard/google/auron/variant.h>
4 #include <soc/pei_wrapper.h>
5 #include <southbridge/intel/lynxpoint/lp_gpio.h>
6
7 /* Samus board memory configuration GPIOs */
8 #define SPD_GPIO_BIT0 69
9 #define SPD_GPIO_BIT1 68
10 #define SPD_GPIO_BIT2 67
11 #define SPD_GPIO_BIT3 65
12
variant_get_spd_index(void)13 unsigned int variant_get_spd_index(void)
14 {
15 const int gpio_vector[] = {
16 SPD_GPIO_BIT0,
17 SPD_GPIO_BIT1,
18 SPD_GPIO_BIT2,
19 SPD_GPIO_BIT3,
20 -1,
21 };
22 return get_gpios(gpio_vector);
23 }
24
variant_is_dual_channel(const unsigned int spd_index)25 bool variant_is_dual_channel(const unsigned int spd_index)
26 {
27 /* Assume same memory in both channels */
28 return true;
29 }
30
mb_get_lpddr3_dq_dqs_map(void)31 const struct lpddr3_dq_dqs_map *mb_get_lpddr3_dq_dqs_map(void)
32 {
33 static const struct lpddr3_dq_dqs_map lpddr3_map = {
34 .dq = {
35 { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
36 { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
37 { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
38 { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
39 },
40 .dqs = {
41 { 2, 0, 1, 3, 6, 4, 7, 5 },
42 { 2, 1, 0, 3, 6, 5, 4, 7 },
43 },
44 };
45 return &lpddr3_map;
46 }
47