1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_MT8173_PERICFG_H__ 4 #define __SOC_MEDIATEK_MT8173_PERICFG_H__ 5 6 #include <soc/addressmap.h> 7 #include <types.h> 8 9 struct mt8173_pericfg_regs { 10 u32 rst0; 11 u32 rst1; 12 u32 pdn0_set; 13 u32 pdn1_set; 14 u32 pdn0_clr; 15 u32 pdn1_clr; 16 u32 pdn0_sta; 17 u32 pdn1_sta; 18 u32 pdn_md1_set; 19 u32 pdn_md2_set; 20 u32 pdn_md1_clr; 21 u32 pdn_md2_clr; 22 u32 pdn_md1_sta; 23 u32 pdn_md2_sta; 24 u32 pdn_md_mask; 25 u32 reserved0[5]; 26 u32 dcmctl; 27 u32 dcmdbc; 28 u32 dcmfsel; 29 u32 cksel; 30 u32 reserved1[104]; 31 u32 axi_bus_ctl1; 32 u32 axi_bus_ctl2; 33 u32 axi_bus_ctl3; 34 u32 axi_si0_ctl; 35 u32 axi_si1_ctl; 36 u32 axi_mi_sta; 37 u32 reserved2[58]; 38 u32 axi_ahb_lmt_con1; 39 u32 axi_ahb_lmt_con2; 40 u32 axi_ahb_lmt_con3; 41 u32 axi_ahb_lmt_con4; 42 u32 axi_ahb_lmt_con5; 43 u32 axi_ahb_lmt_con6; 44 u32 reserved3[2]; 45 u32 axi_axi_lmt_con1; 46 u32 axi_axi_lmt_con2; 47 u32 axi_axi_lmt_con3; 48 u32 axi_axi_lmt_con4; 49 u32 axi_axi_lmt_con5; 50 u32 axi_axi_lmt_con6; 51 u32 axi_axi_lmt_con7; 52 u32 axi_axi_lmt_con8; 53 u32 axi_axi_lmt_con9; 54 u32 reserved4[47]; 55 u32 usb_wakeup_dec_con0; 56 u32 usb_wakeup_dec_con1; 57 u32 usb_wakeup_dec_con2; 58 u32 uart_ck_source_sel; 59 u32 reserved5[1]; 60 u32 usb_wakeup_dec_con3a; 61 u32 reserved6[58]; 62 u32 ssusb_rst; 63 u32 ssusb_pdn_set; 64 u32 ssusb_pdn_clr; 65 u32 ssusb_pdn_sta; 66 }; 67 68 static struct mt8173_pericfg_regs *const mt8173_pericfg = 69 (void *)PERI_CON_BASE; 70 71 /* 72 * UART power down control 73 */ 74 75 enum { 76 PERICFG_UART0_PDN = 1 << 19 77 }; 78 79 /* 80 * PERI 4GB control 81 */ 82 83 enum { 84 PERISYS_4G_SUPPORT = 1 << 15 85 }; 86 87 #endif /* __SOC_MEDIATEK_MT8173_PERICFG_H__ */ 88