1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2 3 /* 4 * This file is created based on MT8188 Functional Specification 5 * Chapter number: 5.2 6 */ 7 8 #ifndef __SOC_MEDIATEK_MT8188_IOCFG_H__ 9 #define __SOC_MEDIATEK_MT8188_IOCFG_H__ 10 11 #include <soc/addressmap.h> 12 #include <types.h> 13 14 struct mt8188_iocfg_lt_regs { 15 u32 reserved1[4]; 16 u32 drv_cfg1; 17 u32 drv_cfg1_set; 18 u32 drv_cfg1_clr; 19 u32 reserved2; 20 u32 drv_cfg2; 21 u32 drv_cfg2_set; 22 u32 drv_cfg2_clr; 23 u32 reserved3; 24 u32 drv_cfg3; 25 u32 drv_cfg3_set; 26 u32 drv_cfg3_clr; 27 u32 reserved4[5]; 28 u32 eh_cfg; 29 u32 eh_cfg_set; 30 u32 eh_cfg_clr; 31 u32 reserved5[9]; 32 u32 ies_cfg1; 33 u32 ies_cfg1_set; 34 u32 ies_cfg1_clr; 35 u32 reserved6[9]; 36 u32 pd_cfg1; 37 u32 pd_cfg1_set; 38 u32 pd_cfg1_clr; 39 u32 reserved7[9]; 40 u32 pu_cfg1; 41 u32 pu_cfg1_set; 42 u32 pu_cfg1_clr; 43 u32 reserved8[21]; 44 u32 rdsel_cfg3; 45 u32 rdsel_cfg3_set; 46 u32 rdsel_cfg3_clr; 47 u32 reserved9[5]; 48 u32 smt_cfg0; 49 u32 smt_cfg0_set; 50 u32 smt_cfg0_clr; 51 u32 reserved10[17]; 52 u32 tdsel_cfg3; 53 u32 tdsel_cfg3_set; 54 u32 tdsel_cfg3_clr; 55 }; 56 check_member(mt8188_iocfg_lt_regs, drv_cfg1, 0x10); 57 check_member(mt8188_iocfg_lt_regs, drv_cfg2, 0x20); 58 check_member(mt8188_iocfg_lt_regs, drv_cfg3, 0x30); 59 check_member(mt8188_iocfg_lt_regs, eh_cfg, 0x50); 60 check_member(mt8188_iocfg_lt_regs, ies_cfg1, 0x80); 61 check_member(mt8188_iocfg_lt_regs, pd_cfg1, 0xB0); 62 check_member(mt8188_iocfg_lt_regs, pu_cfg1, 0xE0); 63 check_member(mt8188_iocfg_lt_regs, rdsel_cfg3, 0x140); 64 check_member(mt8188_iocfg_lt_regs, smt_cfg0, 0x160); 65 check_member(mt8188_iocfg_lt_regs, tdsel_cfg3, 0x1B0); 66 67 #define mtk_iocfg_lt ((struct mt8188_iocfg_lt_regs *)IOCFG_LT_BASE) 68 69 enum { 70 IO_4_MA = 0x1, 71 IO_6_MA = 0x2, 72 }; 73 74 #endif /* __SOC_MEDIATEK_MT8188_IOCFG_H__ */ 75