1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 /* 4 * This file is created based on MT8186 Functional Specification 5 * Chapter number: 3.7 6 */ 7 8 #ifndef __SOC_MEDIATEK_MT8186_PMIF_H__ 9 #define __SOC_MEDIATEK_MT8186_PMIF_H__ 10 11 #include <device/mmio.h> 12 #include <soc/addressmap.h> 13 #include <soc/pmif_common.h> 14 #include <types.h> 15 16 /* indicate which number SW channel start, by project */ 17 #define PMIF_SPMI_SW_CHAN 0xFFFFFFFF 18 #define PMIF_SPMI_INF 0xFFFFFFFF 19 20 struct mtk_pmif_regs { 21 u32 init_done; 22 u32 reserved1[5]; 23 u32 inf_busy_sta; 24 u32 other_busy_sta_0; 25 u32 other_busy_sta_1; 26 u32 inf_en; 27 u32 other_inf_en; 28 u32 inf_cmd_per_0; 29 u32 inf_cmd_per_1; 30 u32 inf_cmd_per_2; 31 u32 inf_cmd_per_3; 32 u32 inf_max_bytecnt_per_0; 33 u32 inf_max_bytecnt_per_1; 34 u32 inf_max_bytecnt_per_2; 35 u32 inf_max_bytecnt_per_3; 36 u32 staupd_ctrl; 37 u32 reserved2[48]; 38 u32 int_gps_auxadc_cmd_addr; 39 u32 int_gps_auxadc_cmd; 40 u32 int_gps_auxadc_rdata_addr; 41 u32 reserved3[13]; 42 u32 arb_en; 43 u32 reserved4[34]; 44 u32 lat_cnter_ctrl; 45 u32 lat_cnter_en; 46 u32 lat_limit_loading; 47 u32 lat_limit_0; 48 u32 lat_limit_1; 49 u32 lat_limit_2; 50 u32 lat_limit_3; 51 u32 lat_limit_4; 52 u32 lat_limit_5; 53 u32 lat_limit_6; 54 u32 lat_limit_7; 55 u32 lat_limit_8; 56 u32 lat_limit_9; 57 u32 reserved5[99]; 58 u32 crc_ctrl; 59 u32 crc_sta; 60 u32 sig_mode; 61 u32 pmic_sig_addr; 62 u32 pmic_sig_val; 63 u32 reserved6[2]; 64 u32 cmdissue_en; 65 u32 reserved7[10]; 66 u32 timer_ctrl; 67 u32 timer_sta; 68 u32 sleep_protection_ctrl; 69 u32 reserved8[6]; 70 u32 spi_mode_ctrl; 71 u32 reserved9[2]; 72 u32 pmic_eint_sta_addr; 73 u32 reserved10[2]; 74 u32 irq_event_en_0; 75 u32 irq_flag_raw_0; 76 u32 irq_flag_0; 77 u32 irq_clr_0; 78 u32 reserved11[244]; 79 u32 swinf_0_acc; 80 u32 swinf_0_wdata_31_0; 81 u32 swinf_0_wdata_63_32; 82 u32 reserved12[2]; 83 u32 swinf_0_rdata_31_0; 84 u32 swinf_0_rdata_63_32; 85 u32 reserved13[2]; 86 u32 swinf_0_vld_clr; 87 u32 swinf_0_sta; 88 u32 reserved14[5]; 89 u32 swinf_1_acc; 90 u32 swinf_1_wdata_31_0; 91 u32 swinf_1_wdata_63_32; 92 u32 reserved15[2]; 93 u32 swinf_1_rdata_31_0; 94 u32 swinf_1_rdata_63_32; 95 u32 reserved16[2]; 96 u32 swinf_1_vld_clr; 97 u32 swinf_1_sta; 98 u32 reserved17[5]; 99 u32 swinf_2_acc; 100 u32 swinf_2_wdata_31_0; 101 u32 swinf_2_wdata_63_32; 102 u32 reserved18[2]; 103 u32 swinf_2_rdata_31_0; 104 u32 swinf_2_rdata_63_32; 105 u32 reserved19[2]; 106 u32 swinf_2_vld_clr; 107 u32 swinf_2_sta; 108 u32 reserved20[5]; 109 u32 swinf_3_acc; 110 u32 swinf_3_wdata_31_0; 111 u32 swinf_3_wdata_63_32; 112 u32 reserved21[2]; 113 u32 swinf_3_rdata_31_0; 114 u32 swinf_3_rdata_63_32; 115 u32 reserved22[2]; 116 u32 swinf_3_vld_clr; 117 u32 swinf_3_sta; 118 u32 reserved23[133]; 119 }; 120 check_member(mtk_pmif_regs, inf_busy_sta, 0x18); 121 check_member(mtk_pmif_regs, int_gps_auxadc_cmd_addr, 0x110); 122 check_member(mtk_pmif_regs, arb_en, 0x0150); 123 check_member(mtk_pmif_regs, lat_cnter_en, 0x1E0); 124 check_member(mtk_pmif_regs, crc_ctrl, 0x39C); 125 check_member(mtk_pmif_regs, cmdissue_en, 0x3B8); 126 check_member(mtk_pmif_regs, timer_ctrl, 0x3E4); 127 check_member(mtk_pmif_regs, spi_mode_ctrl, 0x408); 128 check_member(mtk_pmif_regs, pmic_eint_sta_addr, 0x414); 129 check_member(mtk_pmif_regs, irq_event_en_0, 0x420); 130 check_member(mtk_pmif_regs, swinf_0_acc, 0x800); 131 132 #define PMIF_SPMI_AP_CHAN (PMIF_SPMI_BASE + 0x880) 133 #define PMIF_SPI_AP_CHAN (PMIF_SPI_BASE + 0xC20) 134 135 enum { 136 FREQ_250MHZ = 250, 137 }; 138 139 struct mtk_scp_clk_regs { 140 u32 reserved0; 141 u32 scp_clk_en; 142 }; 143 check_member(mtk_scp_clk_regs, scp_clk_en, 0x4); 144 145 #define mtk_scp_clk ((struct mtk_scp_clk_regs *)SCP_CLK_BASE) 146 147 void pmif_spmi_set_lp_mode(void); 148 149 #endif /*__SOC_MEDIATEK_MT8186_PMIF_H__*/ 150