1 /* 2 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 3 * Copyright (c) 2024, Altera Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 #ifndef NCORE_CCU_H 8 #define NCORE_CCU_H 9 10 #include <stdbool.h> 11 #include <stdint.h> 12 13 #include "socfpga_plat_def.h" 14 15 #ifndef CCU_ACTIVATE_COH_FPGA 16 #define CCU_ACTIVATE_COH_FPGA 0 17 #endif 18 19 /* Macros */ 20 #define CCU_OFFSET_VAL_MASK 3U 21 #define CCU_WORD_BYTE 4U 22 23 // Address Map for CCU Init 24 #define addr_CAIUIDR1 SOCFPGA_CCU_NOC_REG_BASE + 0x00000 25 #define addr_GRBUNRRUCR SOCFPGA_CCU_NOC_REG_BASE + 0xFFFF8 26 #define base_addr_NRS_CAIU0 SOCFPGA_CCU_NOC_REG_BASE + 0x00000 27 #define base_addr_NRS_NCAIU0 SOCFPGA_CCU_NOC_REG_BASE + 0x01000 28 #define base_addr_NRS_NCAIU1 SOCFPGA_CCU_NOC_REG_BASE + 0x02000 29 #define base_addr_NRS_NCAIU2 SOCFPGA_CCU_NOC_REG_BASE + 0x03000 30 #define base_addr_NRS_NCAIU3 SOCFPGA_CCU_NOC_REG_BASE + 0x04000 31 #define base_addr_NRS_DCE0 SOCFPGA_CCU_NOC_REG_BASE + 0x05000 32 #define base_addr_NRS_DCE1 SOCFPGA_CCU_NOC_REG_BASE + 0x06000 33 //#define base_addr_NRS_DMI0 SOCFPGA_CCU_NOC_REG_BASE + 0x07000 34 //#define base_addr_NRS_DMI1 SOCFPGA_CCU_NOC_REG_BASE + 0x08000 35 36 /* DMI */ 37 #define ALT_CCU_CCU_DMI0_DMIUSMCTCR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x7300 38 #define ALT_CCU_CCU_DMI1_DMIUSMCTCR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x8300 39 40 /* DSU */ 41 #define ALT_CCU_DSU_CAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3C0 42 #define ALT_CCU_DSU_CAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3C4 43 #define ALT_CCU_DSU_CAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x414 44 #define ALT_CCU_DSU_CAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x418 45 #define ALT_CCU_DSU_CAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x410 46 #define ALT_CCU_DSU_CAIUGPRBLR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x424 47 #define ALT_CCU_DSU_CAIUGPRBHR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x428 48 #define ALT_CCU_DSU_CAIUGPRAR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x420 49 #define ALT_CCU_DSU_CAIUGPRBLR4_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x444 50 #define ALT_CCU_DSU_CAIUGPRBHR4_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x448 51 #define ALT_CCU_DSU_CAIUGPRAR4_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x440 52 #define ALT_CCU_DSU_CAIUGPRBLR5_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x454 53 #define ALT_CCU_DSU_CAIUGPRBHR5_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x458 54 #define ALT_CCU_DSU_CAIUGPRAR5_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x450 55 #define ALT_CCU_DSU_CAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x464 56 #define ALT_CCU_DSU_CAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x468 57 #define ALT_CCU_DSU_CAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x460 58 #define ALT_CCU_DSU_CAIUGPRBLR7_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x474 59 #define ALT_CCU_DSU_CAIUGPRBHR7_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x478 60 #define ALT_CCU_DSU_CAIUGPRAR7_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x470 61 #define ALT_CCU_DSU_CAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x484 62 #define ALT_CCU_DSU_CAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x488 63 #define ALT_CCU_DSU_CAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x480 64 #define ALT_CCU_DSU_CAIUGPRBLR9_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x494 65 #define ALT_CCU_DSU_CAIUGPRBHR9_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x498 66 #define ALT_CCU_DSU_CAIUGPRAR9_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x490 67 #define ALT_CCU_DSU_CAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x4A4 68 #define ALT_CCU_DSU_CAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x4A8 69 #define ALT_CCU_DSU_CAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x4A0 70 71 /* GIC */ 72 #define ALT_CCU_GIC_M_XAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x23C0 73 #define ALT_CCU_GIC_M_XAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x23C4 74 #define ALT_CCU_GIC_M_XAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2414 75 #define ALT_CCU_GIC_M_XAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2418 76 #define ALT_CCU_GIC_M_XAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2410 77 #define ALT_CCU_GIC_M_XAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2464 78 #define ALT_CCU_GIC_M_XAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2468 79 #define ALT_CCU_GIC_M_XAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2460 80 #define ALT_CCU_GIC_M_XAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2484 81 #define ALT_CCU_GIC_M_XAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2488 82 #define ALT_CCU_GIC_M_XAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x2480 83 #define ALT_CCU_GIC_M_XAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x24A4 84 #define ALT_CCU_GIC_M_XAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x24A8 85 #define ALT_CCU_GIC_M_XAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x24A0 86 87 /* FPGA2SOC */ 88 #define ALT_CCU_FPGA2SOC_BASE SOCFPGA_CCU_NOC_REG_BASE + 0x1000 89 #define ALT_CCU_FPGA2SOC_XAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x13C0 90 #define ALT_CCU_FPGA2SOC_XAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x13C4 91 #define ALT_CCU_FPGA2SOC_XAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1414 92 #define ALT_CCU_FPGA2SOC_XAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1418 93 #define ALT_CCU_FPGA2SOC_XAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1410 94 #define ALT_CCU_FPGA2SOC_XAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1464 95 #define ALT_CCU_FPGA2SOC_XAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1468 96 #define ALT_CCU_FPGA2SOC_XAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1460 97 #define ALT_CCU_FPGA2SOC_XAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1484 98 #define ALT_CCU_FPGA2SOC_XAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1488 99 #define ALT_CCU_FPGA2SOC_XAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1480 100 #define ALT_CCU_FPGA2SOC_XAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A4 101 #define ALT_CCU_FPGA2SOC_XAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A8 102 #define ALT_CCU_FPGA2SOC_XAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A0 103 104 /* TCU */ 105 #define ALT_CCU_TCU_XAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x33C0 106 #define ALT_CCU_TCU_XAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x33C4 107 #define ALT_CCU_TCU_XAIUGPRBLR0_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3404 108 #define ALT_CCU_TCU_XAIUGPRBHR0_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3408 109 #define ALT_CCU_TCU_XAIUGPRAR0_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3400 110 #define ALT_CCU_TCU_XAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3414 111 #define ALT_CCU_TCU_XAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3418 112 #define ALT_CCU_TCU_XAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3410 113 #define ALT_CCU_TCU_XAIUGPRBLR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3424 114 #define ALT_CCU_TCU_XAIUGPRBHR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3428 115 #define ALT_CCU_TCU_XAIUGPRAR2_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3420 116 #define ALT_CCU_TCU_XAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3464 117 #define ALT_CCU_TCU_XAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3468 118 #define ALT_CCU_TCU_XAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3460 119 #define ALT_CCU_TCU_XAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3484 120 #define ALT_CCU_TCU_XAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3488 121 #define ALT_CCU_TCU_XAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x3480 122 #define ALT_CCU_TCU_XAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x34A4 123 #define ALT_CCU_TCU_XAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x34A8 124 #define ALT_CCU_TCU_XAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x34A0 125 126 /* IOM */ 127 #define ALT_CCU_CCU_IOM_XAIUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x43C0 128 #define ALT_CCU_CCU_IOM_XAIUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x13C4 129 #define ALT_CCU_IOM_XAIUGPRBLR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1414 130 #define ALT_CCU_IOM_XAIUGPRBHR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1418 131 #define ALT_CCU_IOM_XAIUGPRAR1_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1410 132 #define ALT_CCU_CCU_IOM_XAIUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1464 133 #define ALT_CCU_CCU_IOM_XAIUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1468 134 #define ALT_CCU_CCU_IOM_XAIUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1460 135 #define ALT_CCU_CCU_IOM_XAIUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1484 136 #define ALT_CCU_CCU_IOM_XAIUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1488 137 #define ALT_CCU_CCU_IOM_XAIUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x1480 138 #define ALT_CCU_CCU_IOM_XAIUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A4 139 #define ALT_CCU_CCU_IOM_XAIUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A8 140 #define ALT_CCU_CCU_IOM_XAIUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x14A0 141 142 /* DCE */ 143 #define ALT_CCU_DCE0_DCEUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x53C0 144 #define ALT_CCU_DCE0_DCEUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x53C4 145 #define ALT_CCU_DCE0_DCEUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5464 146 #define ALT_CCU_DCE0_DCEUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5468 147 #define ALT_CCU_DCE0_DCEUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5460 148 #define ALT_CCU_DCE0_DCEUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5484 149 #define ALT_CCU_DCE0_DCEUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5488 150 #define ALT_CCU_DCE0_DCEUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x5480 151 #define ALT_CCU_DCE0_DCEUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x54A4 152 #define ALT_CCU_DCE0_DCEUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x54A8 153 #define ALT_CCU_DCE0_DCEUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x54A0 154 #define ALT_CCU_DCE1_DCEUAMIGR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x63C0 155 #define ALT_CCU_DCE1_DCEUMIFSR_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x63C4 156 #define ALT_CCU_DCE1_DCEUGPRBLR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6464 157 #define ALT_CCU_DCE1_DCEUGPRBHR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6468 158 #define ALT_CCU_DCE1_DCEUGPRAR6_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6460 159 #define ALT_CCU_DCE1_DCEUGPRBLR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6484 160 #define ALT_CCU_DCE1_DCEUGPRBHR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6488 161 #define ALT_CCU_DCE1_DCEUGPRAR8_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x6480 162 #define ALT_CCU_DCE1_DCEUGPRBLR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x64A4 163 #define ALT_CCU_DCE1_DCEUGPRBHR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x64A8 164 #define ALT_CCU_DCE1_DCEUGPRAR10_ADDR SOCFPGA_CCU_NOC_REG_BASE + 0x64A0 165 #define offset_NRS_GPRAR0 0x400 166 #define offset_NRS_GPRBLR0 0x404 167 #define offset_NRS_GPRBHR0 0x408 168 #define offset_NRS_GPRAR1 0x410 169 #define offset_NRS_GPRBLR1 0x414 170 #define offset_NRS_GPRBHR1 0x418 171 #define offset_NRS_GPRAR2 0x420 172 #define offset_NRS_GPRBLR2 0x424 173 #define offset_NRS_GPRBHR2 0x428 174 #define offset_NRS_GPRAR3 0x430 175 #define offset_NRS_GPRBLR3 0x434 176 #define offset_NRS_GPRBHR3 0x438 177 #define offset_NRS_GPRAR4 0x440 178 #define offset_NRS_GPRBLR4 0x444 179 #define offset_NRS_GPRBHR4 0x448 180 #define offset_NRS_GPRAR5 0x450 181 #define offset_NRS_GPRBLR5 0x454 182 #define offset_NRS_GPRBHR5 0x458 183 #define offset_NRS_GPRAR6 0x460 184 #define offset_NRS_GPRBLR6 0x464 185 #define offset_NRS_GPRBHR6 0x468 186 #define offset_NRS_GPRAR7 0x470 187 #define offset_NRS_GPRBLR7 0x474 188 #define offset_NRS_GPRBHR7 0x478 189 #define offset_NRS_GPRAR8 0x480 190 #define offset_NRS_GPRBLR8 0x484 191 #define offset_NRS_GPRBHR8 0x488 192 #define offset_NRS_GPRAR9 0x490 193 #define offset_NRS_GPRBLR9 0x494 194 #define offset_NRS_GPRBHR9 0x498 195 #define offset_NRS_GPRAR10 0x4A0 196 #define offset_NRS_GPRBLR10 0x4A4 197 #define offset_NRS_GPRBHR10 0x4A8 198 #define offset_NRS_AMIGR 0x3C0 199 #define offset_NRS_MIFSR 0x3C4 200 #define offset_NRS_DMIUSMCTCR 0x300 201 #define base_addr_DII0_PSSPERIPHS 0x10000 202 #define base_addr_DII0_LWHPS2FPGA 0x20000 203 #define base_addr_DII0_HPS2FPGA_1G 0x40000 204 #define base_addr_DII0_HPS2FPGA_15G 0x400000 205 #define base_addr_DII0_HPS2FPGA_240G 0x4000000 206 #define base_addr_DII1_MPFEREGS 0x18000 207 #define base_addr_DII2_GICREGS 0x1D000 208 #define base_addr_DII3_OCRAM 0x0 209 #define base_addr_BHR 0x0 210 #define base_addr_DMI_SDRAM_2G 0x80000 211 #define base_addr_DMI_SDRAM_30G 0x800000 212 #define base_addr_DMI_SDRAM_480G 0x8000000 213 // ((0x0<<9) | (0xf<<20) | (0x1<<30) | (0x1<<31)) 214 #define wr_DII0_PSSPERIPHS 0xC0F00000 215 // ((0x0<<9) | (0x11<<20) | (0x1<<30) | (0x1<<31)) 216 #define wr_DII0_LWHPS2FPGA 0xC1100000 217 // ((0x0<<9) | (0x12<<20) | (0x1<<30) | (0x1<<31)) 218 #define wr_DII0_HPS2FPGA_1G 0xC1200000 219 // ((0x0<<9) | (0x16<<20) | (0x1<<30) | (0x1<<31)) 220 #define wr_DII0_HPS2FPGA_15G 0xC1600000 221 // ((0x0<<9) | (0x1a<<20) | (0x1<<30) | (0x1<<31)) 222 #define wr_DII0_HPS2FPGA_240G 0xC1A00000 223 // ((0x1<<9) | (0xe<<20) | (0x1<<30) | (0x1<<31)) 224 #define wr_DII1_MPFEREGS 0xC0E00200 225 // ((0x2<<9) | (0x8<<20) | (0x1<<30) | (0x1<<31)) 226 #define wr_DII2_GICREGS 0xC0800400 227 // ((0x3<<9) | (0x9<<20) | (0x1<<30) | (0x1<<31)) 228 #define wr_DII3_OCRAM 0xC0900600 229 // ((0x0<<9) | (0x12<<20) | (0x0<<30) | (0x1<<31)) 230 #define wr_DMI_SDRAM_1G_ORDERED 0x81200000 231 // ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x12<<20) | (0x0<<30) | (0x1<<31)) 232 #define wr_DMI_SDRAM_1G 0x81200006 233 // ((0x0<<9) | (0x13<<20) | (0x0<<30) | (0x1<<31)) 234 #define wr_DMI_SDRAM_2G_ORDERED 0x81300000 235 // ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x13<<20) | (0x0<<30) | (0x1<<31)) 236 #define wr_DMI_SDRAM_2G 0x81300006 237 // ((0x0<<9) | (0x16<<20) | (0x0<<30) | (0x1<<31)) 238 #define wr_DMI_SDRAM_15G_ORDERED 0x81600000 239 // ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x16<<20) | (0x0<<30) | (0x1<<31)) 240 #define wr_DMI_SDRAM_15G 0x81600006 241 // ((0x0<<9) | (0x17<<20) | (0x0<<30) | (0x1<<31)) 242 #define wr_DMI_SDRAM_30G_ORDERED 0x81700000 243 // ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x17<<20) | (0x0<<30) | (0x1<<31)) 244 #define wr_DMI_SDRAM_30G 0x81700006 245 // ((0x0<<9) | (0x1a<<20) | (0x0<<30) | (0x1<<31)) 246 #define wr_DMI_SDRAM_240G_ORDERED 0x81A00000 247 // ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x1a<<20) | (0x0<<30) | (0x1<<31)) 248 #define wr_DMI_SDRAM_240G 0x81A00006 249 // ((0x0<<9) | (0x1b<<20) | (0x0<<30) | (0x1<<31)) 250 #define wr_DMI_SDRAM_480G_ORDERED 0x81B00000 251 // ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x1b<<20) | (0x0<<30) | (0x1<<31)) 252 #define wr_DMI_SDRAM_480G 0x81B00006 253 254 typedef enum CCU_REGION_SECURITY_e { 255 /* Allow secure accesses only. */ 256 CCU_REGION_SECURITY_SECURE_ONLY, 257 258 /* Allow non-secure accesses only. */ 259 CCU_REGION_SECURITY_NON_SECURE_ONLY, 260 261 /* Allow accesses of any security state. */ 262 CCU_REGION_SECURITY_DONT_CARE 263 } CCU_REGION_SECURITY_t; 264 265 typedef enum CCU_REGION_PRIVILEGE_e { 266 /* Allow privileged accesses only. */ 267 CCU_REGION_PRIVILEGE_PRIVILEGED_ONLY, 268 /* Allow unprivileged accesses only. */ 269 CCU_REGION_PRIVILEGE_NON_PRIVILEGED_ONLY, 270 /* Allow accesses of any privilege. */ 271 CCU_REGION_PRIVILEGE_DONT_CARE 272 } CCU_REGION_PRIVILEGE_t; 273 274 /* 275 * Initializes the CCU by enabling all regions except RAM 1 - 5. 276 * This is needed because of an RTL change around 2016.02.24. 277 * 278 * Runtime measurement: 279 * - arm : 14,830,000 ps (2016.05.31; sanity/printf_aarch32) 280 * - aarch64 : 14,837,500 ps (2016.05.31; sanity/printf) 281 * 282 * Runtime history: 283 * - arm : 20,916,668 ps (2016.05.30; sanity/printf_aarch32) 284 * - aarch64 : 20,924,168 ps (2016.05.30; sanity/printf) 285 */ 286 int ccu_hps_init(void); 287 288 typedef enum ccu_hps_ram_region_e { 289 ccu_hps_ram_region_ramspace0 = 0, 290 ccu_hps_ram_region_ramspace1 = 1, 291 ccu_hps_ram_region_ramspace2 = 2, 292 ccu_hps_ram_region_ramspace3 = 3, 293 ccu_hps_ram_region_ramspace4 = 4, 294 ccu_hps_ram_region_ramspace5 = 5, 295 } ccu_hps_ram_region_t; 296 297 /* Disables a RAM (OCRAM) region with the given ID. */ 298 int ccu_hps_ram_region_disable(int id); 299 300 /* Enables a RAM (OCRAM) region with the given ID. */ 301 int ccu_hps_ram_region_enable(int id); 302 303 /* 304 * Attempts to remap a RAM (OCRAM) region with the given ID to span the given 305 * start and end address. It also assigns the security and privilege policy. 306 * Regions must be a power-of-two size with a minimum size of 64B. 307 */ 308 int ccu_hps_ram_region_remap(int id, uintptr_t start, uintptr_t end, 309 CCU_REGION_SECURITY_t security, CCU_REGION_PRIVILEGE_t privilege); 310 311 /* Verifies that all enabled RAM (OCRAM) regions does not overlap. */ 312 int ccu_hps_ram_validate(void); 313 314 typedef enum ccu_hps_mem_region_e { 315 ccu_hps_mem_region_ddrspace0 = 0, 316 ccu_hps_mem_region_memspace0 = 1, 317 ccu_hps_mem_region_memspace1a = 2, 318 ccu_hps_mem_region_memspace1b = 3, 319 ccu_hps_mem_region_memspace1c = 4, 320 ccu_hps_mem_region_memspace1d = 5, 321 ccu_hps_mem_region_memspace1e = 6, 322 } ccu_hps_mem_region_t; 323 324 /* Disables mem0 (DDR) region with the given ID. */ 325 int ccu_hps_mem0_region_disable(int id); 326 327 /* Enables mem0 (DDR) region with the given ID. */ 328 int ccu_hps_mem0_region_enable(int id); 329 330 /* 331 * Attempts to remap mem0 (DDR) region with the given ID to span the given 332 * start and end address. It also assigns the security nad privlege policy. 333 * Regions must be a power-of-two in size with a minimum size of 64B. 334 */ 335 int ccu_hps_mem0_region_remap(int id, uintptr_t start, uintptr_t end, 336 CCU_REGION_SECURITY_t security, CCU_REGION_PRIVILEGE_t privilege); 337 338 /* Verifies that all enabled mem0 (DDR) regions does not overlap. */ 339 int ccu_hps_mem0_validate(void); 340 341 typedef enum ccu_hps_ios_region_e { 342 ccu_hps_ios_region_iospace0a = 0, 343 ccu_hps_ios_region_iospace0b = 1, 344 ccu_hps_ios_region_iospace1a = 2, 345 ccu_hps_ios_region_iospace1b = 3, 346 ccu_hps_ios_region_iospace1c = 4, 347 ccu_hps_ios_region_iospace1d = 5, 348 ccu_hps_ios_region_iospace1e = 6, 349 ccu_hps_ios_region_iospace1f = 7, 350 ccu_hps_ios_region_iospace1g = 8, 351 ccu_hps_ios_region_iospace2a = 9, 352 ccu_hps_ios_region_iospace2b = 10, 353 ccu_hps_ios_region_iospace2c = 11, 354 } ccu_hps_ios_region_t; 355 356 /* Disables the IOS (IO Slave) region with the given ID. */ 357 int ccu_hps_ios_region_disable(int id); 358 359 /* Enables the IOS (IO Slave) region with the given ID. */ 360 int ccu_hps_ios_region_enable(int id); 361 362 typedef struct ncore_ccu_reg { 363 char name[50]; 364 uint32_t base; 365 uint32_t size; 366 } ncore_ccu_reg_t; 367 368 typedef struct ncore_ccu { 369 uint32_t offset; 370 uint32_t val; 371 uint32_t mask; 372 } ncore_ccu_t; 373 374 /* Coherent Sub-System Address Map */ 375 #define NCORE_CAIU_OFFSET 0x00000 376 #define NCORE_CAIU_SIZE 0x01000 377 #define NCORE_NCBU_OFFSET 0x60000 378 #define NCORE_NCBU_SIZE 0x01000 379 #define NCORE_DIRU_OFFSET 0x80000 380 #define NCORE_DIRU_SIZE 0x01000 381 #define NCORE_CMIU_OFFSET 0xC0000 382 #define NCORE_CMIU_SIZE 0x01000 383 #define NCORE_CSR_OFFSET 0xFF000 384 #define NCORE_CSADSERO 0x00040 385 #define NCORE_CSUIDR 0x00FF8 386 #define NCORE_CSIDR 0x00FFC 387 388 /* Directory Unit Register Map */ 389 #define NCORE_DIRUSFER 0x00010 390 #define NCORE_DIRUMRHER 0x00070 391 #define NCORE_DIRUSFMCR 0x00080 392 #define NCORE_DIRUSFMAR 0x00084 393 394 /* Coherent Agent Interface Unit Register Map */ 395 #define NCORE_CAIUIDR 0x00FFC 396 397 /* Snoop Enable Register */ 398 #define NCORE_DIRUCASER0 0x00040 399 #define NCORE_DIRUCASER1 0x00044 400 #define NCORE_DIRUCASER2 0x00048 401 #define NCORE_DIRUCASER3 0x0004C 402 #define NCORE_CSADSER0 0x00040 403 #define NCORE_CSADSER1 0x00044 404 #define NCORE_CSADSER2 0x00048 405 #define NCORE_CSADSER3 0x0004C 406 407 /* Protocols Definition */ 408 #define ACE_W_DVM 0 409 #define ACE_L_W_DVM 1 410 #define ACE_WO_DVM 2 411 #define ACE_L_WO_DVM 3 412 413 /* Bypass OCRAM Firewall */ 414 #define NCORE_FW_OCRAM_BLK_BASE 0x100200 415 #define NCORE_FW_OCRAM_BLK_CGF1 0x04 416 #define NCORE_FW_OCRAM_BLK_CGF2 0x08 417 #define NCORE_FW_OCRAM_BLK_CGF3 0x0C 418 #define NCORE_FW_OCRAM_BLK_CGF4 0x10 419 #define OCRAM_PRIVILEGED_MASK BIT(29) 420 #define OCRAM_SECURE_MASK BIT(30) 421 422 /* Macros */ 423 #define NCORE_CCU_REG(base) (SOCFPGA_CCU_NOC_REG_BASE + (base)) 424 #define NCORE_CCU_CSR(reg) (NCORE_CCU_REG(NCORE_CSR_OFFSET)\ 425 + (reg)) 426 #define NCORE_CCU_DIR(reg) (NCORE_CCU_REG(NCORE_DIRU_OFFSET)\ 427 + (reg)) 428 #define NCORE_CCU_CAI(reg) (NCORE_CCU_REG(NCORE_CAIU_OFFSET)\ 429 + (reg)) 430 #define DIRECTORY_UNIT(x, reg) (NCORE_CCU_DIR(reg)\ 431 + NCORE_DIRU_SIZE * (x)) 432 #define COH_AGENT_UNIT(x, reg) (NCORE_CCU_CAI(reg)\ 433 + NCORE_CAIU_SIZE * (x)) 434 #define COH_CPU0_BYPASS_REG(reg) (NCORE_CCU_REG(NCORE_FW_OCRAM_BLK_BASE)\ 435 + (reg)) 436 #define CSUIDR_NUM_CMI(x) (((x) & 0x3F000000) >> 24) 437 #define CSUIDR_NUM_DIR(x) (((x) & 0x003F0000) >> 16) 438 #define CSUIDR_NUM_NCB(x) (((x) & 0x00003F00) >> 8) 439 #define CSUIDR_NUM_CAI(x) (((x) & 0x0000007F) >> 0) 440 #define CSIDR_NUM_SF(x) (((x) & 0x007C0000) >> 18) 441 #define SNOOP_FILTER_ID(x) (((x) << 16)) 442 #define CACHING_AGENT_BIT(x) (((x) & 0x08000) >> 15) 443 #define CACHING_AGENT_TYPE(x) (((x) & 0xF0000) >> 16) 444 445 typedef struct coh_ss_id { 446 uint8_t num_coh_mem; 447 uint8_t num_directory; 448 uint8_t num_non_coh_bridge; 449 uint8_t num_coh_agent; 450 uint8_t num_snoop_filter; 451 } coh_ss_id_t; 452 453 uint32_t init_ncore_ccu(void); 454 void ncore_enable_ocram_firewall(void); 455 void setup_smmu_stream_id(void); 456 int flush_l3_dcache(void); 457 458 #endif 459