1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <console/console.h>
4 #include <device/pci_ops.h>
5 #include <device/pci_def.h>
6 #include <northbridge/intel/pineview/pineview.h>
7 #include <northbridge/intel/pineview/chip.h>
8 #include <option.h>
9 #include <types.h>
10
11 #define LPC_DEV PCI_DEV(0, 0x1f, 0)
12
13 #define CRCLK_PINEVIEW 0x02
14 #define CDCLK_PINEVIEW 0x10
15
early_graphics_setup(void)16 static void early_graphics_setup(void)
17 {
18 u8 reg8;
19 u16 reg16;
20 u32 reg32;
21
22 const struct device *d0f0 = pcidev_on_root(0, 0);
23 const struct northbridge_intel_pineview_config *config = d0f0->chip_info;
24
25 pci_write_config8(HOST_BRIDGE, DEVEN, BOARD_DEVEN);
26
27 /* Fetch VRAM size from CMOS option */
28 reg8 = get_uint_option("gfx_uma_size", 0); /* 0 for 8MB */
29
30 /* Ensure the setting is valid */
31 if (reg8 > 6)
32 reg8 = 0;
33
34 /* Select 1M GTT */
35 pci_write_config16(HOST_BRIDGE, GGC, (1 << 8) | ((reg8 + 3) << 4));
36
37 printk(BIOS_SPEW, "Set GFX clocks...");
38 reg16 = mchbar_read16(MCH_GCFGC);
39 mchbar_write16(MCH_GCFGC, reg16 | 1 << 9);
40 reg16 &= ~0x7f;
41 reg16 |= CDCLK_PINEVIEW | CRCLK_PINEVIEW;
42 reg16 &= ~(1 << 9);
43 mchbar_write16(MCH_GCFGC, reg16);
44
45 /* Graphics core */
46 reg8 = mchbar_read8(HPLLVCO);
47 reg8 &= 0x7;
48
49 reg16 = pci_read_config16(GMCH_IGD, 0xcc) & ~0x1ff;
50
51 if (reg8 == 0x4) {
52 /* 2666MHz */
53 reg16 |= 0xad;
54 } else if (reg8 == 0) {
55 /* 3200MHz */
56 reg16 |= 0xa0;
57 } else if (reg8 == 1) {
58 /* 4000MHz */
59 reg16 |= 0xad;
60 }
61
62 pci_write_config16(GMCH_IGD, 0xcc, reg16);
63
64 pci_and_config8(GMCH_IGD, 0x62, ~0x3);
65 pci_or_config8(GMCH_IGD, 0x62, 2);
66
67 if (config->use_crt) {
68 /* Enable VGA */
69 mchbar_setbits32(DACGIOCTRL1, 1 << 15);
70 } else {
71 /* Disable VGA */
72 mchbar_clrbits32(DACGIOCTRL1, 1 << 15);
73 }
74
75 if (config->use_lvds) {
76 /* Enable LVDS */
77 reg32 = mchbar_read32(LVDSICR2);
78 reg32 &= ~0xf1000000;
79 reg32 |= 0x90000000;
80 mchbar_write32(LVDSICR2, reg32);
81 mchbar_setbits32(IOCKTRR1, 1 << 9);
82 } else {
83 /* Disable LVDS */
84 mchbar_setbits32(DACGIOCTRL1, 3 << 25);
85 }
86
87 mchbar_write32(CICTRL, 0xc6db8b5f);
88 mchbar_write16(CISDCTRL, 0x024f);
89
90 mchbar_clrbits32(DACGIOCTRL1, 0xff);
91 mchbar_setbits32(DACGIOCTRL1, 1 << 5);
92
93 /* Legacy backlight control */
94 pci_write_config8(GMCH_IGD, 0xf4, 0x4c);
95 }
96
early_misc_setup(void)97 static void early_misc_setup(void)
98 {
99 mchbar_read32(HIT0);
100 mchbar_write32(HIT0, 0x00021800);
101 dmibar_write32(0x2c, 0x86000040);
102 pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00020200);
103 pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00000000);
104
105 early_graphics_setup();
106
107 mchbar_read32(HIT4);
108 mchbar_write32(HIT4, 0);
109 mchbar_read32(HIT4);
110 mchbar_write32(HIT4, 1 << 3);
111
112 pci_write_config8(LPC_DEV, 0x08, 0x1d);
113 pci_write_config8(LPC_DEV, 0x08, 0x00);
114 RCBA32(0x3410) = 0x00020465;
115
116 pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1);
117 pci_write_config32(PCI_DEV(0, 0x1d, 1), 0xca, 0x1);
118 pci_write_config32(PCI_DEV(0, 0x1d, 2), 0xca, 0x1);
119 pci_write_config32(PCI_DEV(0, 0x1d, 3), 0xca, 0x1);
120
121 RCBA32(0x3100) = 0x00042210;
122 RCBA32(0x3108) = 0x10004321;
123 RCBA32(0x310c) = 0x00214321;
124 RCBA32(0x3110) = 1;
125 RCBA32(0x3140) = 0x01460132;
126 RCBA32(0x3142) = 0x02370146;
127 RCBA32(0x3144) = 0x32010237;
128 RCBA32(0x3146) = 0x01463201;
129 RCBA32(0x3148) = 0x00000146;
130 }
131
pineview_setup_bars(void)132 static void pineview_setup_bars(void)
133 {
134 printk(BIOS_DEBUG, "Setting up static northbridge registers...");
135 pci_write_config8(HOST_BRIDGE, 0x08, 0x69);
136
137 /* Set up all hardcoded northbridge BARs */
138 pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1);
139 pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1);
140 pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
141 pci_write_config32(HOST_BRIDGE, PMIOBAR, DEFAULT_PMIOBAR | 1);
142
143 /* Set C0000-FFFFF to access RAM on both reads and writes */
144 pci_write_config8(HOST_BRIDGE, PAM0, 0x30);
145 pci_write_config8(HOST_BRIDGE, PAM1, 0x33);
146 pci_write_config8(HOST_BRIDGE, PAM2, 0x33);
147 pci_write_config8(HOST_BRIDGE, PAM3, 0x33);
148 pci_write_config8(HOST_BRIDGE, PAM4, 0x33);
149 pci_write_config8(HOST_BRIDGE, PAM5, 0x33);
150 pci_write_config8(HOST_BRIDGE, PAM6, 0x33);
151
152 printk(BIOS_DEBUG, " done.\n");
153 }
154
pineview_early_init(void)155 void pineview_early_init(void)
156 {
157 /* Print some chipset specific information */
158 printk(BIOS_DEBUG, "Intel Pineview northbridge\n");
159
160 /* Setup all BARs required for early PCIe and raminit */
161 pineview_setup_bars();
162
163 /* Miscellaneous setup */
164 early_misc_setup();
165
166 /* Route port80 to LPC */
167 RCBA32(GCS) &= (~0x04);
168 RCBA32(0x2010) |= (1 << 10);
169 }
170