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Searched defs:pll_div (Results 1 – 7 of 7) sorted by relevance

/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/
Dsoc.h123 struct pll_div { struct
124 uint32_t mhz;
125 uint32_t refdiv;
126 uint32_t fbdiv;
127 uint32_t postdiv1;
128 uint32_t postdiv2;
129 uint32_t frac;
130 uint32_t freq;
/external/trusty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/
Dsoc.h123 struct pll_div { struct
124 uint32_t mhz;
125 uint32_t refdiv;
126 uint32_t fbdiv;
127 uint32_t postdiv1;
128 uint32_t postdiv2;
129 uint32_t frac;
130 uint32_t freq;
/external/coreboot/src/soc/rockchip/rk3399/
Dclock.c15 struct pll_div { struct
33 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1); argument
/external/coreboot/src/soc/rockchip/rk3288/
Dclock.c16 struct pll_div { struct
17 u32 nr;
18 u32 nf;
19 u32 no;
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
Ddfs.c1966 static void m0_configure_ddr(struct pll_div pll_div, uint32_t ddr_index) in m0_configure_ddr()
/external/trusty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
Ddfs.c1966 static void m0_configure_ddr(struct pll_div pll_div, uint32_t ddr_index) in m0_configure_ddr()
/external/coreboot/src/vendorcode/cavium/include/bdk/libbdk-arch/
Dbdk-csrs-gser.h7979 …uint64_t pll_div : 9; /**< [ 8: 0](R/W/H) PLL divider in feedback path which sets… member
8129 …uint64_t pll_div : 9; /**< [ 8: 0](R/W/H) PLL divider in feedback path which sets… member