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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <arch/io.h>
4 #include <arch/ioapic.h>
5 #include <console/console.h>
6 #include <cpu/cpu.h>
7 #include <cpu/x86/lapic_def.h>
8 #include <cpu/x86/mp.h>
9 #include <device/pci_def.h>
10 #include <device/pci_ops.h>
11 #include <device/device.h>
12 #include <identity.h>
13 #include <stdlib.h>
14 #include <smbios.h>
15 #include <types.h>
16 #include "memory.h"
17 
18 #include "fw_cfg.h"
19 #include "fw_cfg_if.h"
20 
21 #include "acpi.h"
22 
qemu_reserve_ports(struct device * dev,unsigned int idx,unsigned int base,unsigned int size,const char * name)23 static void qemu_reserve_ports(struct device *dev, unsigned int idx,
24 			       unsigned int base, unsigned int size,
25 			       const char *name)
26 {
27 	unsigned int end = base + size -1;
28 	struct resource *res;
29 
30 	printk(BIOS_DEBUG, "QEMU: reserve ioports 0x%04x-0x%04x [%s]\n",
31 	       base, end, name);
32 	res = new_resource(dev, idx);
33 	res->base = base;
34 	res->size = size;
35 	res->limit = 0xffff;
36 	res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_STORED |
37 		IORESOURCE_ASSIGNED;
38 }
39 
cpu_pci_domain_set_resources(struct device * dev)40 static void cpu_pci_domain_set_resources(struct device *dev)
41 {
42 	assign_resources(dev->downstream);
43 }
44 
cpu_pci_domain_read_resources(struct device * dev)45 static void cpu_pci_domain_read_resources(struct device *dev)
46 {
47 	u16 nbid   = pci_read_config16(pcidev_on_root(0x0, 0), PCI_DEVICE_ID);
48 	int i440fx = (nbid == 0x1237);
49 	int q35    = (nbid == 0x29c0);
50 	struct resource *res;
51 	uint64_t tomk = 0;
52 	int idx = 10;
53 	FWCfgFile f;
54 
55 	pci_domain_read_resources(dev);
56 
57 	if (!fw_cfg_check_file(&f, "etc/e820") && f.size > 0) {
58 		/* supported by qemu 1.7+ */
59 		FwCfgE820Entry *list = malloc(f.size);
60 		int i;
61 		fw_cfg_get(f.select, list, f.size);
62 		for (i = 0; i < f.size / sizeof(*list); i++) {
63 			switch (list[i].type) {
64 			case 1: /* RAM */
65 				printk(BIOS_DEBUG, "QEMU: e820/ram: 0x%08llx + 0x%08llx\n",
66 				       list[i].address, list[i].length);
67 				if (list[i].address == 0) {
68 					tomk = list[i].length / 1024;
69 					ram_from_to(dev, idx++, 0, 0xa0000);
70 					ram_from_to(dev, idx++, 0xc0000, tomk * KiB);
71 				} else {
72 					ram_range(dev, idx++, list[i].address, list[i].length);
73 				}
74 				break;
75 			case 2: /* reserved */
76 				printk(BIOS_DEBUG, "QEMU: e820/res: 0x%08llx +0x%08llx\n",
77 				       list[i].address, list[i].length);
78 				res = new_resource(dev, idx++);
79 				res->base = list[i].address;
80 				res->size = list[i].length;
81 				res->limit = 0xffffffff;
82 				res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
83 					IORESOURCE_STORED | IORESOURCE_ASSIGNED;
84 				break;
85 			default:
86 				/* skip unknown */
87 				break;
88 			}
89 		}
90 		free(list);
91 	}
92 
93 	if (!tomk) {
94 		/* qemu older than 1.7, or reading etc/e820 failed. Fallback to cmos. */
95 		tomk = qemu_get_memory_size();
96 		uint64_t high = qemu_get_high_memory_size();
97 		printk(BIOS_DEBUG, "QEMU: cmos: %llu MiB RAM below 4G.\n", tomk / 1024);
98 		printk(BIOS_DEBUG, "QEMU: cmos: %llu MiB RAM above 4G.\n", high / 1024);
99 
100 		/* Report the memory regions. */
101 		ram_from_to(dev, idx++, 0, 0xa0000);
102 		ram_from_to(dev, idx++, 0xc0000, tomk * KiB);
103 
104 		if (high)
105 			upper_ram_end(dev, idx++, 4ull * GiB + high * KiB);
106 	}
107 
108 	/* Reserve I/O ports used by QEMU */
109 	qemu_reserve_ports(dev, idx++, 0x0510, 0x02, "firmware-config");
110 	qemu_reserve_ports(dev, idx++, 0x5658, 0x01, "vmware-port");
111 	if (i440fx) {
112 		qemu_reserve_ports(dev, idx++, 0xae00, 0x10, "pci-hotplug");
113 		qemu_reserve_ports(dev, idx++, 0xaf00, 0x20, "cpu-hotplug");
114 		qemu_reserve_ports(dev, idx++, 0xafe0, 0x04, "piix4-gpe0");
115 	}
116 	if (inb(CONFIG_CONSOLE_QEMU_DEBUGCON_PORT) == 0xe9) {
117 		qemu_reserve_ports(dev, idx++, CONFIG_CONSOLE_QEMU_DEBUGCON_PORT, 1,
118 				   "debugcon");
119 	}
120 
121 	/* A segment is legacy VGA region */
122 	mmio_from_to(dev, idx++, 0xa0000, 0xc0000);
123 
124 	/* C segment to 1MB is reserved RAM (low tables) */
125 	reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB);
126 
127 	if (q35 && ((tomk * 1024) < 0xb0000000)) {
128 		/*
129 		 * Reserve the region between top-of-ram and the
130 		 * mmconf xbar (ar 0xb0000000), so coreboot doesn't
131 		 * place pci bars there.  The region isn't declared as
132 		 * pci io window in the ACPI tables (\_SB.PCI0._CRS).
133 		 */
134 		res = new_resource(dev, idx++);
135 		res->base = tomk * 1024;
136 		res->size = 0xb0000000 - tomk * 1024;
137 		res->limit = 0xffffffff;
138 		res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
139 			IORESOURCE_STORED | IORESOURCE_ASSIGNED;
140 	}
141 
142 	if (i440fx) {
143 		/* Reserve space for the IOAPIC.  This should be in
144 		 * the southbridge, but I couldn't tell which device
145 		 * to put it in. */
146 		res = new_resource(dev, 2);
147 		res->base = IO_APIC_ADDR;
148 		res->size = 0x100000UL;
149 		res->limit = 0xffffffffUL;
150 		res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
151 			IORESOURCE_STORED | IORESOURCE_ASSIGNED;
152 	}
153 
154 	/* Reserve space for the LAPIC.  There's one in every processor, but
155 	 * the space only needs to be reserved once, so we do it here. */
156 	res = new_resource(dev, 3);
157 	res->base = cpu_get_lapic_addr();
158 	res->size = 0x10000UL;
159 	res->limit = 0xffffffffUL;
160 	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
161 		     IORESOURCE_ASSIGNED;
162 }
163 
164 #if CONFIG(GENERATE_SMBIOS_TABLES)
qemu_get_smbios_data16(int handle,unsigned long * current)165 static int qemu_get_smbios_data16(int handle, unsigned long *current)
166 {
167 	struct smbios_type16 *t = smbios_carve_table(*current, SMBIOS_PHYS_MEMORY_ARRAY,
168 						     sizeof(*t), handle);
169 
170 	t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD;
171 	t->use = MEMORY_ARRAY_USE_SYSTEM;
172 	t->memory_error_correction = MEMORY_ARRAY_ECC_NONE;
173 	t->maximum_capacity = qemu_get_memory_size();
174 
175 	const int len = smbios_full_table_len(&t->header, t->eos);
176 	*current += len;
177 	return len;
178 }
179 
qemu_get_smbios_data17(int handle,int parent_handle,unsigned long * current)180 static int qemu_get_smbios_data17(int handle, int parent_handle, unsigned long *current)
181 {
182 	struct smbios_type17 *t = smbios_carve_table(*current, SMBIOS_MEMORY_DEVICE,
183 						     sizeof(*t), handle);
184 
185 	t->phys_memory_array_handle = parent_handle;
186 	t->size = qemu_get_memory_size() / 1024;
187 	t->data_width = 64;
188 	t->total_width = 64;
189 	t->form_factor = MEMORY_FORMFACTOR_DIMM;
190 	t->device_locator = smbios_add_string(t->eos, "Virtual");
191 	t->memory_type = MEMORY_TYPE_DDR;
192 	t->type_detail = MEMORY_TYPE_DETAIL_SYNCHRONOUS;
193 	t->speed = 200;
194 	t->clock_speed = 200;
195 	t->manufacturer = smbios_add_string(t->eos, mainboard_vendor);
196 
197 	const int len = smbios_full_table_len(&t->header, t->eos);
198 	*current += len;
199 	return len;
200 }
201 
qemu_get_smbios_data(struct device * dev,int * handle,unsigned long * current)202 static int qemu_get_smbios_data(struct device *dev, int *handle, unsigned long *current)
203 {
204 	int len;
205 
206 	len = fw_cfg_smbios_tables(handle, current);
207 	if (len != 0)
208 		return len;
209 
210 	len = qemu_get_smbios_data16(*handle, current);
211 	len += qemu_get_smbios_data17(*handle+1, *handle, current);
212 	*handle += 2;
213 	return len;
214 }
215 #endif
216 
217 #if CONFIG(HAVE_ACPI_TABLES)
qemu_acpi_name(const struct device * dev)218 static const char *qemu_acpi_name(const struct device *dev)
219 {
220 	if (dev->path.type == DEVICE_PATH_DOMAIN)
221 		return "PCI0";
222 
223 	if (!is_pci_dev_on_bus(dev, 0))
224 		return NULL;
225 
226 	return NULL;
227 }
228 #endif
229 
230 static struct device_operations pci_domain_ops = {
231 	.read_resources		= cpu_pci_domain_read_resources,
232 	.set_resources		= cpu_pci_domain_set_resources,
233 	.scan_bus		= pci_host_bridge_scan_bus,
234 #if CONFIG(GENERATE_SMBIOS_TABLES)
235 	.get_smbios_data	= qemu_get_smbios_data,
236 #endif
237 #if CONFIG(HAVE_ACPI_TABLES)
238 	.acpi_name		= qemu_acpi_name,
239 #endif
240 };
241 
242 static const struct mp_ops mp_ops_no_smm = {
243 	.get_cpu_count = fw_cfg_max_cpus,
244 };
245 
246 extern const struct mp_ops mp_ops_with_smm;
247 
mp_init_cpus(struct bus * cpu_bus)248 void mp_init_cpus(struct bus *cpu_bus)
249 {
250 	const struct mp_ops *ops = CONFIG(NO_SMM) ? &mp_ops_no_smm : &mp_ops_with_smm;
251 
252 	/* TODO: Handle mp_init_with_smm failure? */
253 	mp_init_with_smm(cpu_bus, ops);
254 }
255 
cpu_bus_init(struct device * dev)256 static void cpu_bus_init(struct device *dev)
257 {
258 	mp_cpu_bus_init(dev);
259 }
260 
261 static struct device_operations cpu_bus_ops = {
262 	.read_resources   = noop_read_resources,
263 	.set_resources    = noop_set_resources,
264 	.init             = cpu_bus_init,
265 };
266 
northbridge_enable(struct device * dev)267 static void northbridge_enable(struct device *dev)
268 {
269 	/* Set the operations if it is a special bus type */
270 	if (dev->path.type == DEVICE_PATH_DOMAIN) {
271 		dev->ops = &pci_domain_ops;
272 	}
273 	else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
274 		dev->ops = &cpu_bus_ops;
275 	}
276 }
277 
278 struct chip_operations mainboard_emulation_qemu_i440fx_ops = {
279 	.name = "QEMU Northbridge i440fx",
280 	.enable_dev = northbridge_enable,
281 };
282 
283 struct chip_operations mainboard_emulation_qemu_q35_ops = {
284 	.name = "QEMU Northbridge q35",
285 	.enable_dev = northbridge_enable,
286 };
287