1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * SPDX-License-Identifier: MIT
4 */
5
6 #include "r500_fragprog.h"
7
8 #include <stdio.h>
9
10 #include "r300_reg.h"
11 #include "radeon_compiler_util.h"
12 #include "radeon_list.h"
13 #include "radeon_variable.h"
14
15 #include "util/compiler.h"
16
17 /**
18 * Rewrite IF instructions to use the ALU result special register.
19 */
20 static void
r500_transform_IF_instr(struct radeon_compiler * c,struct rc_instruction * inst_if,struct rc_list * var_list)21 r500_transform_IF_instr(struct radeon_compiler *c, struct rc_instruction *inst_if,
22 struct rc_list *var_list)
23 {
24
25 struct rc_variable *writer;
26 struct rc_list *writer_list, *list_ptr;
27 unsigned int generic_if = 0;
28 unsigned int alu_chan;
29
30 writer_list = rc_variable_list_get_writers(var_list, inst_if->Type, &inst_if->U.I.SrcReg[0]);
31 if (!writer_list) {
32 generic_if = 1;
33 } else {
34
35 /* Make sure it is safe for the writers to write to
36 * ALU Result */
37 for (list_ptr = writer_list; list_ptr; list_ptr = list_ptr->Next) {
38 struct rc_instruction *inst;
39 writer = list_ptr->Item;
40 /* We are going to modify the destination register
41 * of writer, so if it has a reader other than
42 * inst_if (aka ReaderCount > 1) we must fall back to
43 * our generic IF.
44 * If the writer has a lower IP than inst_if, this
45 * means that inst_if is above the writer in a loop.
46 * I'm not sure why this would ever happen, but
47 * if it does we want to make sure we fall back
48 * to our generic IF. */
49 if (writer->ReaderCount > 1 || writer->Inst->IP < inst_if->IP) {
50 generic_if = 1;
51 break;
52 }
53
54 /* The ALU Result is not preserved across IF
55 * instructions, so if there is another IF
56 * instruction between writer and inst_if, then
57 * we need to fall back to generic IF. */
58 for (inst = writer->Inst; inst != inst_if; inst = inst->Next) {
59 const struct rc_opcode_info *info = rc_get_opcode_info(inst->U.I.Opcode);
60 if (info->IsFlowControl) {
61 generic_if = 1;
62 break;
63 }
64 }
65 if (generic_if) {
66 break;
67 }
68 }
69 }
70
71 if (GET_SWZ(inst_if->U.I.SrcReg[0].Swizzle, 0) == RC_SWIZZLE_X) {
72 alu_chan = RC_ALURESULT_X;
73 } else {
74 alu_chan = RC_ALURESULT_W;
75 }
76 if (generic_if) {
77 struct rc_instruction *inst_mov = rc_insert_new_instruction(c, inst_if->Prev);
78
79 inst_mov->U.I.Opcode = RC_OPCODE_MOV;
80 inst_mov->U.I.DstReg.WriteMask = 0;
81 inst_mov->U.I.DstReg.File = RC_FILE_NONE;
82 inst_mov->U.I.ALUResultCompare = RC_COMPARE_FUNC_NOTEQUAL;
83 inst_mov->U.I.WriteALUResult = alu_chan;
84 inst_mov->U.I.SrcReg[0] = inst_if->U.I.SrcReg[0];
85 if (alu_chan == RC_ALURESULT_X) {
86 inst_mov->U.I.SrcReg[0].Swizzle =
87 combine_swizzles4(inst_mov->U.I.SrcReg[0].Swizzle, RC_SWIZZLE_X, RC_SWIZZLE_UNUSED,
88 RC_SWIZZLE_UNUSED, RC_SWIZZLE_UNUSED);
89 } else {
90 inst_mov->U.I.SrcReg[0].Swizzle =
91 combine_swizzles4(inst_mov->U.I.SrcReg[0].Swizzle, RC_SWIZZLE_UNUSED, RC_SWIZZLE_UNUSED,
92 RC_SWIZZLE_UNUSED, RC_SWIZZLE_Z);
93 }
94 } else {
95 rc_compare_func compare_func = RC_COMPARE_FUNC_NEVER;
96 unsigned int preserve_opcode = 0;
97 for (list_ptr = writer_list; list_ptr; list_ptr = list_ptr->Next) {
98 writer = list_ptr->Item;
99 switch (writer->Inst->U.I.Opcode) {
100 case RC_OPCODE_SEQ:
101 compare_func = RC_COMPARE_FUNC_EQUAL;
102 break;
103 case RC_OPCODE_SNE:
104 compare_func = RC_COMPARE_FUNC_NOTEQUAL;
105 break;
106 case RC_OPCODE_SGE:
107 compare_func = RC_COMPARE_FUNC_GEQUAL;
108 break;
109 case RC_OPCODE_SLT:
110 compare_func = RC_COMPARE_FUNC_LESS;
111 break;
112 default:
113 compare_func = RC_COMPARE_FUNC_NOTEQUAL;
114 preserve_opcode = 1;
115 break;
116 }
117 if (!preserve_opcode) {
118 writer->Inst->U.I.Opcode = RC_OPCODE_ADD;
119 writer->Inst->U.I.SrcReg[1].Negate = ~writer->Inst->U.I.SrcReg[1].Negate;
120 }
121 writer->Inst->U.I.DstReg.WriteMask = 0;
122 writer->Inst->U.I.DstReg.File = RC_FILE_NONE;
123 writer->Inst->U.I.WriteALUResult = alu_chan;
124 writer->Inst->U.I.ALUResultCompare = compare_func;
125 }
126 }
127
128 inst_if->U.I.SrcReg[0].File = RC_FILE_SPECIAL;
129 inst_if->U.I.SrcReg[0].Index = RC_SPECIAL_ALU_RESULT;
130 inst_if->U.I.SrcReg[0].Swizzle =
131 RC_MAKE_SWIZZLE(RC_SWIZZLE_X, RC_SWIZZLE_UNUSED, RC_SWIZZLE_UNUSED, RC_SWIZZLE_UNUSED);
132 inst_if->U.I.SrcReg[0].Negate = 0;
133 }
134
135 void
r500_transform_IF(struct radeon_compiler * c,void * user)136 r500_transform_IF(struct radeon_compiler *c, void *user)
137 {
138 struct rc_list *var_list = rc_get_variables(c);
139
140 struct rc_instruction *inst = c->Program.Instructions.Next;
141 while (inst != &c->Program.Instructions) {
142 struct rc_instruction *current = inst;
143 inst = inst->Next;
144
145 if (current->U.I.Opcode == RC_OPCODE_IF)
146 r500_transform_IF_instr(c, current, var_list);
147 }
148 }
149
150 static int
r500_swizzle_is_native(rc_opcode opcode,struct rc_src_register reg)151 r500_swizzle_is_native(rc_opcode opcode, struct rc_src_register reg)
152 {
153 unsigned int relevant;
154 int i;
155
156 if (opcode == RC_OPCODE_TEX || opcode == RC_OPCODE_TXB || opcode == RC_OPCODE_TXP ||
157 opcode == RC_OPCODE_TXD || opcode == RC_OPCODE_TXL || opcode == RC_OPCODE_KIL) {
158 if (reg.Abs)
159 return 0;
160
161 if (opcode == RC_OPCODE_KIL && (reg.Swizzle != RC_SWIZZLE_XYZW || reg.Negate != RC_MASK_NONE))
162 return 0;
163
164 for (i = 0; i < 4; ++i) {
165 unsigned int swz = GET_SWZ(reg.Swizzle, i);
166 if (swz == RC_SWIZZLE_UNUSED) {
167 reg.Negate &= ~(1 << i);
168 continue;
169 }
170 if (swz >= 4)
171 return 0;
172 }
173
174 if (reg.Negate)
175 return 0;
176
177 return 1;
178 } else if (opcode == RC_OPCODE_DDX || opcode == RC_OPCODE_DDY) {
179 /* DDX/MDH and DDY/MDV explicitly ignore incoming swizzles;
180 * if it doesn't fit perfectly into a .xyzw case... */
181 if (reg.Swizzle == RC_SWIZZLE_XYZW && !reg.Abs && !reg.Negate)
182 return 1;
183
184 return 0;
185 } else {
186 /* ALU instructions support almost everything */
187 relevant = 0;
188 for (i = 0; i < 3; ++i) {
189 unsigned int swz = GET_SWZ(reg.Swizzle, i);
190 if (swz != RC_SWIZZLE_UNUSED && swz != RC_SWIZZLE_ZERO)
191 relevant |= 1 << i;
192 }
193 if ((reg.Negate & relevant) && ((reg.Negate & relevant) != relevant))
194 return 0;
195
196 return 1;
197 }
198 }
199
200 /**
201 * Split source register access.
202 *
203 * The only thing we *cannot* do in an ALU instruction is per-component
204 * negation.
205 */
206 static void
r500_swizzle_split(struct rc_src_register src,unsigned int usemask,struct rc_swizzle_split * split)207 r500_swizzle_split(struct rc_src_register src, unsigned int usemask, struct rc_swizzle_split *split)
208 {
209 unsigned int negatebase[2] = {0, 0};
210 int i;
211
212 for (i = 0; i < 4; ++i) {
213 unsigned int swz = GET_SWZ(src.Swizzle, i);
214 if (swz == RC_SWIZZLE_UNUSED || !GET_BIT(usemask, i))
215 continue;
216 negatebase[GET_BIT(src.Negate, i)] |= 1 << i;
217 }
218
219 split->NumPhases = 0;
220
221 for (i = 0; i <= 1; ++i) {
222 if (!negatebase[i])
223 continue;
224
225 split->Phase[split->NumPhases++] = negatebase[i];
226 }
227 }
228
229 const struct rc_swizzle_caps r500_swizzle_caps = {.IsNative = r500_swizzle_is_native,
230 .Split = r500_swizzle_split};
231
232 static char *
toswiz(int swiz_val)233 toswiz(int swiz_val)
234 {
235 switch (swiz_val) {
236 case 0: return "R";
237 case 1: return "G";
238 case 2: return "B";
239 case 3: return "A";
240 case 4: return "0";
241 case 5: return "H";
242 case 6: return "1";
243 case 7: return "U";
244 }
245 return NULL;
246 }
247
248 static char *
toop(int op_val)249 toop(int op_val)
250 {
251 char *str = NULL;
252 switch (op_val) {
253 case 0: str = "MAD"; break;
254 case 1: str = "DP3"; break;
255 case 2: str = "DP4"; break;
256 case 3: str = "D2A"; break;
257 case 4: str = "MIN"; break;
258 case 5: str = "MAX"; break;
259 case 6: str = "Reserved"; break;
260 case 7: str = "CND"; break;
261 case 8: str = "CMP"; break;
262 case 9: str = "FRC"; break;
263 case 10: str = "SOP"; break;
264 case 11: str = "MDH"; break;
265 case 12: str = "MDV"; break;
266 }
267 return str;
268 }
269
270 static char *
to_alpha_op(int op_val)271 to_alpha_op(int op_val)
272 {
273 char *str = NULL;
274 switch (op_val) {
275 case 0: str = "MAD"; break;
276 case 1: str = "DP"; break;
277 case 2: str = "MIN"; break;
278 case 3: str = "MAX"; break;
279 case 4: str = "Reserved"; break;
280 case 5: str = "CND"; break;
281 case 6: str = "CMP"; break;
282 case 7: str = "FRC"; break;
283 case 8: str = "EX2"; break;
284 case 9: str = "LN2"; break;
285 case 10: str = "RCP"; break;
286 case 11: str = "RSQ"; break;
287 case 12: str = "SIN"; break;
288 case 13: str = "COS"; break;
289 case 14: str = "MDH"; break;
290 case 15: str = "MDV"; break;
291 }
292 return str;
293 }
294
295 static char *
to_mask(int val)296 to_mask(int val)
297 {
298 char *str = NULL;
299 switch (val) {
300 case 0: str = "NONE"; break;
301 case 1: str = "R"; break;
302 case 2: str = "G"; break;
303 case 3: str = "RG"; break;
304 case 4: str = "B"; break;
305 case 5: str = "RB"; break;
306 case 6: str = "GB"; break;
307 case 7: str = "RGB"; break;
308 case 8: str = "A"; break;
309 case 9: str = "AR"; break;
310 case 10: str = "AG"; break;
311 case 11: str = "ARG"; break;
312 case 12: str = "AB"; break;
313 case 13: str = "ARB"; break;
314 case 14: str = "AGB"; break;
315 case 15: str = "ARGB"; break;
316 }
317 return str;
318 }
319
320 static char *
to_texop(int val)321 to_texop(int val)
322 {
323 switch (val) {
324 case 0: return "NOP";
325 case 1: return "LD";
326 case 2: return "TEXKILL";
327 case 3: return "PROJ";
328 case 4: return "LODBIAS";
329 case 5: return "LOD";
330 case 6: return "DXDY";
331 }
332 return NULL;
333 }
334
335 void
r500FragmentProgramDump(struct radeon_compiler * c,void * user)336 r500FragmentProgramDump(struct radeon_compiler *c, void *user)
337 {
338 struct r300_fragment_program_compiler *compiler = (struct r300_fragment_program_compiler *)c;
339 struct r500_fragment_program_code *code = &compiler->code->code.r500;
340 int n, i;
341 uint32_t inst;
342 uint32_t inst0;
343 char *str = NULL;
344 fprintf(stderr, "R500 Fragment Program:\n--------\n");
345
346 for (n = 0; n < code->inst_end + 1; n++) {
347 inst0 = inst = code->inst[n].inst0;
348 fprintf(stderr, "%d\t0:CMN_INST 0x%08x:", n, inst);
349 switch (inst & 0x3) {
350 case R500_INST_TYPE_ALU: str = "ALU"; break;
351 case R500_INST_TYPE_OUT: str = "OUT"; break;
352 case R500_INST_TYPE_FC: str = "FC"; break;
353 case R500_INST_TYPE_TEX: str = "TEX"; break;
354 }
355 fprintf(stderr, "%s %s %s %s %s ", str, inst & R500_INST_TEX_SEM_WAIT ? "TEX_WAIT" : "",
356 inst & R500_INST_LAST ? "LAST" : "", inst & R500_INST_NOP ? "NOP" : "",
357 inst & R500_INST_ALU_WAIT ? "ALU WAIT" : "");
358 fprintf(stderr, "wmask: %s omask: %s\n", to_mask((inst >> 11) & 0xf),
359 to_mask((inst >> 15) & 0xf));
360
361 switch (inst0 & 0x3) {
362 case R500_INST_TYPE_ALU:
363 case R500_INST_TYPE_OUT:
364 fprintf(stderr, "\t1:RGB_ADDR 0x%08x:", code->inst[n].inst1);
365 inst = code->inst[n].inst1;
366
367 fprintf(stderr, "Addr0: %d%c, Addr1: %d%c, Addr2: %d%c, srcp:%d\n", inst & 0xff,
368 (inst & (1 << 8)) ? 'c' : 't', (inst >> 10) & 0xff, (inst & (1 << 18)) ? 'c' : 't',
369 (inst >> 20) & 0xff, (inst & (1 << 28)) ? 'c' : 't', (inst >> 30));
370
371 fprintf(stderr, "\t2:ALPHA_ADDR 0x%08x:", code->inst[n].inst2);
372 inst = code->inst[n].inst2;
373 fprintf(stderr, "Addr0: %d%c, Addr1: %d%c, Addr2: %d%c, srcp:%d\n", inst & 0xff,
374 (inst & (1 << 8)) ? 'c' : 't', (inst >> 10) & 0xff, (inst & (1 << 18)) ? 'c' : 't',
375 (inst >> 20) & 0xff, (inst & (1 << 28)) ? 'c' : 't', (inst >> 30));
376 fprintf(stderr, "\t3 RGB_INST: 0x%08x:", code->inst[n].inst3);
377 inst = code->inst[n].inst3;
378 fprintf(stderr, "rgb_A_src:%d %s/%s/%s %d rgb_B_src:%d %s/%s/%s %d targ: %d\n",
379 (inst) & 0x3, toswiz((inst >> 2) & 0x7), toswiz((inst >> 5) & 0x7),
380 toswiz((inst >> 8) & 0x7), (inst >> 11) & 0x3, (inst >> 13) & 0x3,
381 toswiz((inst >> 15) & 0x7), toswiz((inst >> 18) & 0x7), toswiz((inst >> 21) & 0x7),
382 (inst >> 24) & 0x3, (inst >> 29) & 0x3);
383
384 fprintf(stderr, "\t4 ALPHA_INST:0x%08x:", code->inst[n].inst4);
385 inst = code->inst[n].inst4;
386 fprintf(stderr, "%s dest:%d%s alp_A_src:%d %s %d alp_B_src:%d %s %d targ %d w:%d\n",
387 to_alpha_op(inst & 0xf), (inst >> 4) & 0x7f, inst & (1 << 11) ? "(rel)" : "",
388 (inst >> 12) & 0x3, toswiz((inst >> 14) & 0x7), (inst >> 17) & 0x3,
389 (inst >> 19) & 0x3, toswiz((inst >> 21) & 0x7), (inst >> 24) & 0x3,
390 (inst >> 29) & 0x3, (inst >> 31) & 0x1);
391
392 fprintf(stderr, "\t5 RGBA_INST: 0x%08x:", code->inst[n].inst5);
393 inst = code->inst[n].inst5;
394 fprintf(stderr, "%s dest:%d%s rgb_C_src:%d %s/%s/%s %d alp_C_src:%d %s %d\n",
395 toop(inst & 0xf), (inst >> 4) & 0x7f, inst & (1 << 11) ? "(rel)" : "",
396 (inst >> 12) & 0x3, toswiz((inst >> 14) & 0x7), toswiz((inst >> 17) & 0x7),
397 toswiz((inst >> 20) & 0x7), (inst >> 23) & 0x3, (inst >> 25) & 0x3,
398 toswiz((inst >> 27) & 0x7), (inst >> 30) & 0x3);
399 break;
400 case R500_INST_TYPE_FC:
401 fprintf(stderr, "\t2:FC_INST 0x%08x:", code->inst[n].inst2);
402 inst = code->inst[n].inst2;
403 /* JUMP_FUNC JUMP_ANY*/
404 fprintf(stderr, "0x%02x %1x ", inst >> 8 & 0xff, (inst & R500_FC_JUMP_ANY) >> 5);
405
406 /* OP */
407 switch (inst & 0x7) {
408 case R500_FC_OP_JUMP: fprintf(stderr, "JUMP"); break;
409 case R500_FC_OP_LOOP: fprintf(stderr, "LOOP"); break;
410 case R500_FC_OP_ENDLOOP: fprintf(stderr, "ENDLOOP"); break;
411 case R500_FC_OP_REP: fprintf(stderr, "REP"); break;
412 case R500_FC_OP_ENDREP: fprintf(stderr, "ENDREP"); break;
413 case R500_FC_OP_BREAKLOOP: fprintf(stderr, "BREAKLOOP"); break;
414 case R500_FC_OP_BREAKREP: fprintf(stderr, "BREAKREP"); break;
415 case R500_FC_OP_CONTINUE: fprintf(stderr, "CONTINUE"); break;
416 }
417 fprintf(stderr, " ");
418 /* A_OP */
419 switch (inst & (0x3 << 6)) {
420 case R500_FC_A_OP_NONE: fprintf(stderr, "NONE"); break;
421 case R500_FC_A_OP_POP: fprintf(stderr, "POP"); break;
422 case R500_FC_A_OP_PUSH: fprintf(stderr, "PUSH"); break;
423 }
424 /* B_OP0 B_OP1 */
425 for (i = 0; i < 2; i++) {
426 fprintf(stderr, " ");
427 switch (inst & (0x3 << (24 + (i * 2)))) {
428 /* R500_FC_B_OP0_NONE
429 * R500_FC_B_OP1_NONE */
430 case 0:
431 fprintf(stderr, "NONE");
432 break;
433 case R500_FC_B_OP0_DECR:
434 case R500_FC_B_OP1_DECR:
435 fprintf(stderr, "DECR");
436 break;
437 case R500_FC_B_OP0_INCR:
438 case R500_FC_B_OP1_INCR:
439 fprintf(stderr, "INCR");
440 break;
441 }
442 }
443 /*POP_CNT B_ELSE */
444 fprintf(stderr, " %d %1x", (inst >> 16) & 0x1f, (inst & R500_FC_B_ELSE) >> 4);
445 inst = code->inst[n].inst3;
446 /* JUMP_ADDR */
447 fprintf(stderr, " %d", inst >> 16);
448
449 if (code->inst[n].inst2 & R500_FC_IGNORE_UNCOVERED) {
450 fprintf(stderr, " IGN_UNC");
451 }
452 inst = code->inst[n].inst3;
453 fprintf(stderr, "\n\t3:FC_ADDR 0x%08x:", inst);
454 fprintf(stderr, "BOOL: 0x%02x, INT: 0x%02x, JUMP_ADDR: %d, JMP_GLBL: %1x\n", inst & 0x1f,
455 (inst >> 8) & 0x1f, (inst >> 16) & 0x1ff, inst >> 31);
456 break;
457 case R500_INST_TYPE_TEX:
458 inst = code->inst[n].inst1;
459 fprintf(stderr, "\t1:TEX_INST: 0x%08x: id: %d op:%s, %s, %s %s\n", inst,
460 (inst >> 16) & 0xf, to_texop((inst >> 22) & 0x7), (inst & (1 << 25)) ? "ACQ" : "",
461 (inst & (1 << 26)) ? "IGNUNC" : "", (inst & (1 << 27)) ? "UNSCALED" : "SCALED");
462 inst = code->inst[n].inst2;
463 fprintf(stderr, "\t2:TEX_ADDR: 0x%08x: src: %d%s %s/%s/%s/%s dst: %d%s %s/%s/%s/%s\n",
464 inst, inst & 127, inst & (1 << 7) ? "(rel)" : "", toswiz((inst >> 8) & 0x3),
465 toswiz((inst >> 10) & 0x3), toswiz((inst >> 12) & 0x3), toswiz((inst >> 14) & 0x3),
466 (inst >> 16) & 127, inst & (1 << 23) ? "(rel)" : "", toswiz((inst >> 24) & 0x3),
467 toswiz((inst >> 26) & 0x3), toswiz((inst >> 28) & 0x3),
468 toswiz((inst >> 30) & 0x3));
469
470 fprintf(stderr, "\t3:TEX_DXDY: 0x%08x\n", code->inst[n].inst3);
471 break;
472 }
473 fprintf(stderr, "\n");
474 }
475 }
476