1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Copyright 2023 Red Hat Inc.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28 #include "radv_buffer.h"
29 #include "radv_cs.h"
30 #include "radv_debug.h"
31 #include "radv_device_memory.h"
32 #include "radv_entrypoints.h"
33 #include "radv_image_view.h"
34 #include "radv_physical_device.h"
35 #include "radv_query.h"
36 #include "radv_video.h"
37
38 #include "ac_vcn_enc.h"
39
40 #define RENCODE_V4_FW_INTERFACE_MAJOR_VERSION 1
41 #define RENCODE_V4_FW_INTERFACE_MINOR_VERSION 7
42
43 #define RENCODE_V4_IB_PARAM_ENCODE_STATISTICS 0x0000001a
44
45 #define RENCODE_V3_FW_INTERFACE_MAJOR_VERSION 1
46 #define RENCODE_V3_FW_INTERFACE_MINOR_VERSION 27
47
48 #define RENCODE_V2_IB_PARAM_SESSION_INFO 0x00000001
49 #define RENCODE_V2_IB_PARAM_TASK_INFO 0x00000002
50 #define RENCODE_V2_IB_PARAM_SESSION_INIT 0x00000003
51 #define RENCODE_V2_IB_PARAM_LAYER_CONTROL 0x00000004
52 #define RENCODE_V2_IB_PARAM_LAYER_SELECT 0x00000005
53 #define RENCODE_V2_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
54 #define RENCODE_V2_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000007
55 #define RENCODE_V2_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x00000008
56 #define RENCODE_V2_IB_PARAM_QUALITY_PARAMS 0x00000009
57 #define RENCODE_V2_IB_PARAM_DIRECT_OUTPUT_NALU 0x0000000a
58 #define RENCODE_V2_IB_PARAM_SLICE_HEADER 0x0000000b
59 #define RENCODE_V2_IB_PARAM_INPUT_FORMAT 0x0000000c
60 #define RENCODE_V2_IB_PARAM_OUTPUT_FORMAT 0x0000000d
61 #define RENCODE_V2_IB_PARAM_ENCODE_PARAMS 0x0000000f
62 #define RENCODE_V2_IB_PARAM_INTRA_REFRESH 0x00000010
63 #define RENCODE_V2_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x00000011
64 #define RENCODE_V2_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x00000012
65 #define RENCODE_V2_IB_PARAM_FEEDBACK_BUFFER 0x00000015
66 #define RENCODE_V2_IB_PARAM_ENCODE_STATISTICS 0x00000019
67 #define RENCODE_V2_IB_PARAM_RATE_CONTROL_PER_PIC_EX 0x0000001d
68
69 #define RENCODE_V2_HEVC_IB_PARAM_SLICE_CONTROL 0x00100001
70 #define RENCODE_V2_HEVC_IB_PARAM_SPEC_MISC 0x00100002
71 #define RENCODE_V2_HEVC_IB_PARAM_LOOP_FILTER 0x00100003
72
73 #define RENCODE_V2_H264_IB_PARAM_SLICE_CONTROL 0x00200001
74 #define RENCODE_V2_H264_IB_PARAM_SPEC_MISC 0x00200002
75 #define RENCODE_V2_H264_IB_PARAM_ENCODE_PARAMS 0x00200003
76 #define RENCODE_V2_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004
77
78 #define RENCODE_V2_FW_INTERFACE_MAJOR_VERSION 1
79 #define RENCODE_V2_FW_INTERFACE_MINOR_VERSION 18
80
81 #define RENCODE_IB_PARAM_SESSION_INFO 0x00000001
82 #define RENCODE_IB_PARAM_TASK_INFO 0x00000002
83 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003
84 #define RENCODE_IB_PARAM_LAYER_CONTROL 0x00000004
85 #define RENCODE_IB_PARAM_LAYER_SELECT 0x00000005
86 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
87 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000007
88 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x00000008
89 #define RENCODE_IB_PARAM_QUALITY_PARAMS 0x00000009
90 #define RENCODE_IB_PARAM_SLICE_HEADER 0x0000000a
91 #define RENCODE_IB_PARAM_ENCODE_PARAMS 0x0000000b
92 #define RENCODE_IB_PARAM_INTRA_REFRESH 0x0000000c
93 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x0000000d
94 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x0000000e
95 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER 0x00000010
96 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PIC_EX 0x0000001d
97 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU 0x00000020
98 #define RENCODE_IB_PARAM_ENCODE_STATISTICS 0x00000024
99
100 #define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL 0x00100001
101 #define RENCODE_HEVC_IB_PARAM_SPEC_MISC 0x00100002
102 #define RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER 0x00100003
103
104 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL 0x00200001
105 #define RENCODE_H264_IB_PARAM_SPEC_MISC 0x00200002
106 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS 0x00200003
107 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004
108
109 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
110 #define RENCODE_FW_INTERFACE_MINOR_VERSION 15
111
112 void
radv_probe_video_encode(struct radv_physical_device * pdev)113 radv_probe_video_encode(struct radv_physical_device *pdev)
114 {
115 pdev->video_encode_enabled = false;
116 if (pdev->info.vcn_ip_version >= VCN_4_0_0) {
117 if (pdev->info.vcn_enc_major_version != RENCODE_V4_FW_INTERFACE_MAJOR_VERSION)
118 return;
119 if (pdev->info.vcn_enc_minor_version < RENCODE_V4_FW_INTERFACE_MINOR_VERSION)
120 return;
121
122 /* VCN 4 FW 1.22 has all the necessary pieces to pass CTS */
123 if (pdev->info.vcn_enc_minor_version >= 22) {
124 pdev->video_encode_enabled = true;
125 return;
126 }
127 } else if (pdev->info.vcn_ip_version >= VCN_3_0_0) {
128 if (pdev->info.vcn_enc_major_version != RENCODE_V3_FW_INTERFACE_MAJOR_VERSION)
129 return;
130 if (pdev->info.vcn_enc_minor_version < RENCODE_V3_FW_INTERFACE_MINOR_VERSION)
131 return;
132
133 /* VCN 3 FW 1.33 has all the necessary pieces to pass CTS */
134 if (pdev->info.vcn_enc_minor_version >= 33) {
135 pdev->video_encode_enabled = true;
136 return;
137 }
138 } else if (pdev->info.vcn_ip_version >= VCN_2_0_0) {
139 if (pdev->info.vcn_enc_major_version != RENCODE_V2_FW_INTERFACE_MAJOR_VERSION)
140 return;
141 if (pdev->info.vcn_enc_minor_version < RENCODE_V2_FW_INTERFACE_MINOR_VERSION)
142 return;
143
144 /* VCN 2 FW 1.24 has all the necessary pieces to pass CTS */
145 if (pdev->info.vcn_enc_minor_version >= 24) {
146 pdev->video_encode_enabled = true;
147 return;
148 }
149 } else {
150 if (pdev->info.vcn_enc_major_version != RENCODE_FW_INTERFACE_MAJOR_VERSION)
151 return;
152 if (pdev->info.vcn_enc_minor_version < RENCODE_FW_INTERFACE_MINOR_VERSION)
153 return;
154 }
155
156 struct radv_instance *instance = radv_physical_device_instance(pdev);
157 pdev->video_encode_enabled = !!(instance->perftest_flags & RADV_PERFTEST_VIDEO_ENCODE);
158 }
159
160 void
radv_init_physical_device_encoder(struct radv_physical_device * pdev)161 radv_init_physical_device_encoder(struct radv_physical_device *pdev)
162 {
163 if (pdev->info.vcn_ip_version >= VCN_4_0_0) {
164 pdev->enc_hw_ver = RADV_VIDEO_ENC_HW_4;
165 pdev->encoder_interface_version = ((RENCODE_V4_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
166 (RENCODE_V4_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
167 } else if (pdev->info.vcn_ip_version >= VCN_3_0_0) {
168 pdev->enc_hw_ver = RADV_VIDEO_ENC_HW_3;
169 pdev->encoder_interface_version = ((RENCODE_V3_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
170 (RENCODE_V3_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
171 } else if (pdev->info.vcn_ip_version >= VCN_2_0_0) {
172 pdev->enc_hw_ver = RADV_VIDEO_ENC_HW_2;
173 pdev->encoder_interface_version = ((RENCODE_V2_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
174 (RENCODE_V2_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
175 } else {
176 pdev->enc_hw_ver = RADV_VIDEO_ENC_HW_1_2;
177 pdev->encoder_interface_version = ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
178 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
179 }
180
181 if (pdev->info.vcn_ip_version >= VCN_2_0_0) {
182 pdev->vcn_enc_cmds.session_info = RENCODE_V2_IB_PARAM_SESSION_INFO;
183 pdev->vcn_enc_cmds.task_info = RENCODE_V2_IB_PARAM_TASK_INFO;
184 pdev->vcn_enc_cmds.session_init = RENCODE_V2_IB_PARAM_SESSION_INIT;
185 pdev->vcn_enc_cmds.layer_control = RENCODE_V2_IB_PARAM_LAYER_CONTROL;
186 pdev->vcn_enc_cmds.layer_select = RENCODE_V2_IB_PARAM_LAYER_SELECT;
187 pdev->vcn_enc_cmds.rc_session_init = RENCODE_V2_IB_PARAM_RATE_CONTROL_SESSION_INIT;
188 pdev->vcn_enc_cmds.rc_layer_init = RENCODE_V2_IB_PARAM_RATE_CONTROL_LAYER_INIT;
189 pdev->vcn_enc_cmds.rc_per_pic = RENCODE_V2_IB_PARAM_RATE_CONTROL_PER_PIC_EX;
190 pdev->vcn_enc_cmds.quality_params = RENCODE_V2_IB_PARAM_QUALITY_PARAMS;
191 pdev->vcn_enc_cmds.nalu = RENCODE_V2_IB_PARAM_DIRECT_OUTPUT_NALU;
192 pdev->vcn_enc_cmds.slice_header = RENCODE_V2_IB_PARAM_SLICE_HEADER;
193 pdev->vcn_enc_cmds.input_format = RENCODE_V2_IB_PARAM_INPUT_FORMAT;
194 pdev->vcn_enc_cmds.output_format = RENCODE_V2_IB_PARAM_OUTPUT_FORMAT;
195 pdev->vcn_enc_cmds.enc_params = RENCODE_V2_IB_PARAM_ENCODE_PARAMS;
196 pdev->vcn_enc_cmds.intra_refresh = RENCODE_V2_IB_PARAM_INTRA_REFRESH;
197 pdev->vcn_enc_cmds.ctx = RENCODE_V2_IB_PARAM_ENCODE_CONTEXT_BUFFER;
198 pdev->vcn_enc_cmds.bitstream = RENCODE_V2_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
199 pdev->vcn_enc_cmds.feedback = RENCODE_V2_IB_PARAM_FEEDBACK_BUFFER;
200 pdev->vcn_enc_cmds.slice_control_hevc = RENCODE_V2_HEVC_IB_PARAM_SLICE_CONTROL;
201 pdev->vcn_enc_cmds.spec_misc_hevc = RENCODE_V2_HEVC_IB_PARAM_SPEC_MISC;
202 pdev->vcn_enc_cmds.deblocking_filter_hevc = RENCODE_V2_HEVC_IB_PARAM_LOOP_FILTER;
203 pdev->vcn_enc_cmds.slice_control_h264 = RENCODE_V2_H264_IB_PARAM_SLICE_CONTROL;
204 pdev->vcn_enc_cmds.spec_misc_h264 = RENCODE_V2_H264_IB_PARAM_SPEC_MISC;
205 pdev->vcn_enc_cmds.enc_params_h264 = RENCODE_V2_H264_IB_PARAM_ENCODE_PARAMS;
206 pdev->vcn_enc_cmds.deblocking_filter_h264 = RENCODE_V2_H264_IB_PARAM_DEBLOCKING_FILTER;
207 if (pdev->enc_hw_ver == RADV_VIDEO_ENC_HW_4) {
208 pdev->vcn_enc_cmds.enc_statistics = RENCODE_V4_IB_PARAM_ENCODE_STATISTICS;
209 } else
210 pdev->vcn_enc_cmds.enc_statistics = RENCODE_V2_IB_PARAM_ENCODE_STATISTICS;
211 } else {
212 pdev->vcn_enc_cmds.session_info = RENCODE_IB_PARAM_SESSION_INFO;
213 pdev->vcn_enc_cmds.task_info = RENCODE_IB_PARAM_TASK_INFO;
214 pdev->vcn_enc_cmds.session_init = RENCODE_IB_PARAM_SESSION_INIT;
215 pdev->vcn_enc_cmds.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
216 pdev->vcn_enc_cmds.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
217 pdev->vcn_enc_cmds.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
218 pdev->vcn_enc_cmds.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
219 pdev->vcn_enc_cmds.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PIC_EX;
220 pdev->vcn_enc_cmds.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
221 pdev->vcn_enc_cmds.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
222 pdev->vcn_enc_cmds.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
223 pdev->vcn_enc_cmds.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
224 pdev->vcn_enc_cmds.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
225 pdev->vcn_enc_cmds.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
226 pdev->vcn_enc_cmds.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
227 pdev->vcn_enc_cmds.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
228 pdev->vcn_enc_cmds.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
229 pdev->vcn_enc_cmds.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
230 pdev->vcn_enc_cmds.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER;
231 pdev->vcn_enc_cmds.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
232 pdev->vcn_enc_cmds.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
233 pdev->vcn_enc_cmds.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
234 pdev->vcn_enc_cmds.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
235 pdev->vcn_enc_cmds.enc_statistics = RENCODE_IB_PARAM_ENCODE_STATISTICS;
236 }
237 }
238
239 /* to process invalid frame rate */
240 static void
radv_vcn_enc_invalid_frame_rate(uint32_t * den,uint32_t * num)241 radv_vcn_enc_invalid_frame_rate(uint32_t *den, uint32_t *num)
242 {
243 if (*den == 0 || *num == 0) {
244 *den = 1;
245 *num = 30;
246 }
247 }
248
249 static uint32_t
radv_vcn_per_frame_integer(uint32_t bitrate,uint32_t den,uint32_t num)250 radv_vcn_per_frame_integer(uint32_t bitrate, uint32_t den, uint32_t num)
251 {
252 uint64_t rate_den = (uint64_t)bitrate * (uint64_t)den;
253
254 return (uint32_t)(rate_den / num);
255 }
256
257 static uint32_t
radv_vcn_per_frame_frac(uint32_t bitrate,uint32_t den,uint32_t num)258 radv_vcn_per_frame_frac(uint32_t bitrate, uint32_t den, uint32_t num)
259 {
260 uint64_t rate_den = (uint64_t)bitrate * (uint64_t)den;
261 uint64_t remainder = rate_den % num;
262
263 return (uint32_t)((remainder << 32) / num);
264 }
265
266 static void
radv_enc_set_emulation_prevention(struct radv_cmd_buffer * cmd_buffer,bool set)267 radv_enc_set_emulation_prevention(struct radv_cmd_buffer *cmd_buffer, bool set)
268 {
269 struct radv_enc_state *enc = &cmd_buffer->video.enc;
270 if (set != enc->emulation_prevention) {
271 enc->emulation_prevention = set;
272 enc->num_zeros = 0;
273 }
274 }
275
276 static uint32_t
radv_enc_value_bits(uint32_t value)277 radv_enc_value_bits(uint32_t value)
278 {
279 uint32_t i = 1;
280
281 while (value > 1) {
282 i++;
283 value >>= 1;
284 }
285
286 return i;
287 }
288
289 static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
290
291 static void
radv_enc_output_one_byte(struct radv_cmd_buffer * cmd_buffer,unsigned char byte)292 radv_enc_output_one_byte(struct radv_cmd_buffer *cmd_buffer, unsigned char byte)
293 {
294 struct radeon_cmdbuf *cs = cmd_buffer->cs;
295 struct radv_enc_state *enc = &cmd_buffer->video.enc;
296 if (enc->byte_index == 0)
297 cs->buf[cs->cdw] = 0;
298 cs->buf[cs->cdw] |= ((unsigned int)(byte) << index_to_shifts[enc->byte_index]);
299 enc->byte_index++;
300
301 if (enc->byte_index >= 4) {
302 enc->byte_index = 0;
303 cs->cdw++;
304 }
305 }
306
307 static void
radv_enc_emulation_prevention(struct radv_cmd_buffer * cmd_buffer,unsigned char byte)308 radv_enc_emulation_prevention(struct radv_cmd_buffer *cmd_buffer, unsigned char byte)
309 {
310 struct radv_enc_state *enc = &cmd_buffer->video.enc;
311 if (enc->emulation_prevention) {
312 if ((enc->num_zeros >= 2) && ((byte == 0x00) || (byte == 0x01) || (byte == 0x02) || (byte == 0x03))) {
313 radv_enc_output_one_byte(cmd_buffer, 0x03);
314 enc->bits_output += 8;
315 enc->num_zeros = 0;
316 }
317 enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
318 }
319 }
320
321 static void
radv_enc_code_fixed_bits(struct radv_cmd_buffer * cmd_buffer,unsigned int value,unsigned int num_bits)322 radv_enc_code_fixed_bits(struct radv_cmd_buffer *cmd_buffer, unsigned int value, unsigned int num_bits)
323 {
324 struct radv_enc_state *enc = &cmd_buffer->video.enc;
325 unsigned int bits_to_pack = 0;
326 enc->bits_size += num_bits;
327
328 while (num_bits > 0) {
329 unsigned int value_to_pack = value & (0xffffffff >> (32 - num_bits));
330 bits_to_pack = num_bits > (32 - enc->bits_in_shifter) ? (32 - enc->bits_in_shifter) : num_bits;
331
332 if (bits_to_pack < num_bits)
333 value_to_pack = value_to_pack >> (num_bits - bits_to_pack);
334
335 enc->shifter |= value_to_pack << (32 - enc->bits_in_shifter - bits_to_pack);
336 num_bits -= bits_to_pack;
337 enc->bits_in_shifter += bits_to_pack;
338
339 while (enc->bits_in_shifter >= 8) {
340 unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
341 enc->shifter <<= 8;
342 radv_enc_emulation_prevention(cmd_buffer, output_byte);
343 radv_enc_output_one_byte(cmd_buffer, output_byte);
344 enc->bits_in_shifter -= 8;
345 enc->bits_output += 8;
346 }
347 }
348 }
349
350 static void
radv_enc_reset(struct radv_cmd_buffer * cmd_buffer)351 radv_enc_reset(struct radv_cmd_buffer *cmd_buffer)
352 {
353 struct radv_enc_state *enc = &cmd_buffer->video.enc;
354 enc->emulation_prevention = false;
355 enc->shifter = 0;
356 enc->bits_in_shifter = 0;
357 enc->bits_output = 0;
358 enc->num_zeros = 0;
359 enc->byte_index = 0;
360 enc->bits_size = 0;
361 }
362
363 static void
radv_enc_byte_align(struct radv_cmd_buffer * cmd_buffer)364 radv_enc_byte_align(struct radv_cmd_buffer *cmd_buffer)
365 {
366 struct radv_enc_state *enc = &cmd_buffer->video.enc;
367 unsigned int num_padding_zeros = (32 - enc->bits_in_shifter) % 8;
368
369 if (num_padding_zeros > 0)
370 radv_enc_code_fixed_bits(cmd_buffer, 0, num_padding_zeros);
371 }
372
373 static void
radv_enc_flush_headers(struct radv_cmd_buffer * cmd_buffer)374 radv_enc_flush_headers(struct radv_cmd_buffer *cmd_buffer)
375 {
376 struct radv_enc_state *enc = &cmd_buffer->video.enc;
377 struct radeon_cmdbuf *cs = cmd_buffer->cs;
378 if (enc->bits_in_shifter != 0) {
379 unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
380 radv_enc_emulation_prevention(cmd_buffer, output_byte);
381 radv_enc_output_one_byte(cmd_buffer, output_byte);
382 enc->bits_output += enc->bits_in_shifter;
383 enc->shifter = 0;
384 enc->bits_in_shifter = 0;
385 enc->num_zeros = 0;
386 }
387
388 if (enc->byte_index > 0) {
389 cs->cdw++;
390 enc->byte_index = 0;
391 }
392 }
393
394 static void
radv_enc_code_ue(struct radv_cmd_buffer * cmd_buffer,unsigned int value)395 radv_enc_code_ue(struct radv_cmd_buffer *cmd_buffer, unsigned int value)
396 {
397 unsigned int x = 0;
398 unsigned int ue_code = value + 1;
399 value += 1;
400
401 while (value) {
402 value = (value >> 1);
403 x += 1;
404 }
405 if (x > 1)
406 radv_enc_code_fixed_bits(cmd_buffer, 0, x - 1);
407 radv_enc_code_fixed_bits(cmd_buffer, ue_code, x);
408 }
409
410 static void
radv_enc_code_se(struct radv_cmd_buffer * cmd_buffer,int value)411 radv_enc_code_se(struct radv_cmd_buffer *cmd_buffer, int value)
412 {
413 unsigned int v = 0;
414
415 if (value != 0)
416 v = (value < 0 ? ((unsigned int)(0 - value) << 1) : (((unsigned int)(value) << 1) - 1));
417
418 radv_enc_code_ue(cmd_buffer, v);
419 }
420
421 #define ENC_BEGIN \
422 { \
423 uint32_t begin = cs->cdw++;
424
425 #define ENC_END \
426 radeon_emit_direct(cs, begin, (cs->cdw - begin) * 4); \
427 cmd_buffer->video.enc.total_task_size += cs->buf[begin]; \
428 }
429
430 static void
radv_enc_session_info(struct radv_cmd_buffer * cmd_buffer)431 radv_enc_session_info(struct radv_cmd_buffer *cmd_buffer)
432 {
433 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
434 const struct radv_physical_device *pdev = radv_device_physical(device);
435 struct radeon_cmdbuf *cs = cmd_buffer->cs;
436 ENC_BEGIN;
437 radeon_emit(cs, pdev->vcn_enc_cmds.session_info);
438 radeon_emit(cs, pdev->encoder_interface_version);
439
440 radv_cs_add_buffer(device->ws, cs, cmd_buffer->video.vid->sessionctx.mem->bo);
441 uint64_t va = radv_buffer_get_va(cmd_buffer->video.vid->sessionctx.mem->bo);
442 va += cmd_buffer->video.vid->sessionctx.offset;
443 radeon_emit(cs, va >> 32);
444 radeon_emit(cs, va & 0xffffffff);
445 radeon_emit(cs, RENCODE_ENGINE_TYPE_ENCODE);
446 ENC_END;
447 }
448
449 static void
radv_enc_task_info(struct radv_cmd_buffer * cmd_buffer,bool feedback)450 radv_enc_task_info(struct radv_cmd_buffer *cmd_buffer, bool feedback)
451 {
452 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
453 const struct radv_physical_device *pdev = radv_device_physical(device);
454 struct radeon_cmdbuf *cs = cmd_buffer->cs;
455 struct radv_enc_state *enc = &cmd_buffer->video.enc;
456
457 enc->task_id++;
458 ENC_BEGIN;
459 radeon_emit(cs, pdev->vcn_enc_cmds.task_info);
460 enc->task_size_offset = cs->cdw++;
461 radeon_emit(cs, enc->task_id);
462 radeon_emit(cs, feedback ? 1 : 0);
463 ENC_END;
464 }
465
466 static void
radv_enc_session_init(struct radv_cmd_buffer * cmd_buffer,const struct VkVideoEncodeInfoKHR * enc_info)467 radv_enc_session_init(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEncodeInfoKHR *enc_info)
468 {
469 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
470 const struct radv_physical_device *pdev = radv_device_physical(device);
471 struct radv_video_session *vid = cmd_buffer->video.vid;
472 struct radeon_cmdbuf *cs = cmd_buffer->cs;
473 unsigned alignment_w = 16;
474 unsigned alignment_h = 16;
475 if (vid->vk.op == VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR) {
476 alignment_w = 64;
477 }
478
479 uint32_t w = enc_info->srcPictureResource.codedExtent.width;
480 uint32_t h = enc_info->srcPictureResource.codedExtent.height;
481 uint32_t aligned_picture_width = align(w, alignment_w);
482 uint32_t aligned_picture_height = align(h, alignment_h);
483 uint32_t padding_width = aligned_picture_width - w;
484 uint32_t padding_height = aligned_picture_height - h;
485
486 ENC_BEGIN;
487 radeon_emit(cs, pdev->vcn_enc_cmds.session_init);
488 radeon_emit(cs, vid->enc_session.encode_standard);
489 radeon_emit(cs, aligned_picture_width);
490 radeon_emit(cs, aligned_picture_height);
491 radeon_emit(cs, padding_width);
492 radeon_emit(cs, padding_height);
493 radeon_emit(cs, vid->enc_session.pre_encode_mode);
494 radeon_emit(cs, vid->enc_session.pre_encode_chroma_enabled);
495 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3) {
496 radeon_emit(cs, 0); // slice output enabled.
497 }
498 radeon_emit(cs, vid->enc_session.display_remote);
499 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4) {
500 radeon_emit(cs, 0);
501 }
502 ENC_END;
503 }
504
505 static void
radv_enc_layer_control(struct radv_cmd_buffer * cmd_buffer,const rvcn_enc_layer_control_t * rc_layer_control)506 radv_enc_layer_control(struct radv_cmd_buffer *cmd_buffer, const rvcn_enc_layer_control_t *rc_layer_control)
507 {
508 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
509 const struct radv_physical_device *pdev = radv_device_physical(device);
510 struct radeon_cmdbuf *cs = cmd_buffer->cs;
511 ENC_BEGIN;
512 radeon_emit(cs, pdev->vcn_enc_cmds.layer_control);
513 radeon_emit(cs, rc_layer_control->max_num_temporal_layers); // max num temporal layesr
514 radeon_emit(cs, rc_layer_control->num_temporal_layers); // num temporal layers
515 ENC_END;
516 }
517
518 static void
radv_enc_layer_select(struct radv_cmd_buffer * cmd_buffer,int tl_idx)519 radv_enc_layer_select(struct radv_cmd_buffer *cmd_buffer, int tl_idx)
520 {
521 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
522 const struct radv_physical_device *pdev = radv_device_physical(device);
523 struct radeon_cmdbuf *cs = cmd_buffer->cs;
524 ENC_BEGIN;
525 radeon_emit(cs, pdev->vcn_enc_cmds.layer_select);
526 radeon_emit(cs, tl_idx); // temporal layer index
527 ENC_END;
528 }
529
530 static void
radv_enc_slice_control(struct radv_cmd_buffer * cmd_buffer,const struct VkVideoEncodeInfoKHR * enc_info)531 radv_enc_slice_control(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEncodeInfoKHR *enc_info)
532 {
533 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
534 const struct radv_physical_device *pdev = radv_device_physical(device);
535 struct radeon_cmdbuf *cs = cmd_buffer->cs;
536
537 uint32_t num_mbs_in_slice;
538 uint32_t width_in_mbs = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.width, 16);
539 uint32_t height_in_mbs = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.height, 16);
540 num_mbs_in_slice = width_in_mbs * height_in_mbs;
541 ENC_BEGIN;
542 radeon_emit(cs, pdev->vcn_enc_cmds.slice_control_h264);
543 radeon_emit(cs, RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS); // slice control mode
544 radeon_emit(cs, num_mbs_in_slice); // num mbs per slice
545 ENC_END;
546 }
547
548 static void
radv_enc_spec_misc_h264(struct radv_cmd_buffer * cmd_buffer,const struct VkVideoEncodeInfoKHR * enc_info)549 radv_enc_spec_misc_h264(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEncodeInfoKHR *enc_info)
550 {
551 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
552 const struct radv_physical_device *pdev = radv_device_physical(device);
553 struct radeon_cmdbuf *cs = cmd_buffer->cs;
554 const struct VkVideoEncodeH264PictureInfoKHR *h264_picture_info =
555 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H264_PICTURE_INFO_KHR);
556 const StdVideoEncodeH264PictureInfo *pic = h264_picture_info->pStdPictureInfo;
557 const StdVideoH264SequenceParameterSet *sps =
558 vk_video_find_h264_enc_std_sps(&cmd_buffer->video.params->vk, pic->seq_parameter_set_id);
559 const StdVideoH264PictureParameterSet *pps =
560 vk_video_find_h264_enc_std_pps(&cmd_buffer->video.params->vk, pic->pic_parameter_set_id);
561 ENC_BEGIN;
562 radeon_emit(cs, pdev->vcn_enc_cmds.spec_misc_h264);
563 radeon_emit(cs, pps->flags.constrained_intra_pred_flag); // constrained_intra_pred_flag
564 radeon_emit(cs, pps->flags.entropy_coding_mode_flag); // cabac enable
565 radeon_emit(cs, 0); // cabac init idc
566 radeon_emit(cs, 1); // half pel enabled
567 radeon_emit(cs, 1); // quarter pel enabled
568 radeon_emit(cs, cmd_buffer->video.vid->vk.h264.profile_idc); // profile_idc
569 radeon_emit(cs, vk_video_get_h264_level(sps->level_idc));
570
571 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3) {
572 radeon_emit(cs, 0); // v3 b_picture_enabled
573 radeon_emit(cs, pps->weighted_bipred_idc); // v3 weighted bipred idc
574 }
575
576 ENC_END;
577 }
578
579 static void
radv_enc_spec_misc_hevc(struct radv_cmd_buffer * cmd_buffer,const struct VkVideoEncodeInfoKHR * enc_info)580 radv_enc_spec_misc_hevc(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEncodeInfoKHR *enc_info)
581 {
582 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
583 const struct radv_physical_device *pdev = radv_device_physical(device);
584 struct radeon_cmdbuf *cs = cmd_buffer->cs;
585 const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
586 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
587 const StdVideoEncodeH265PictureInfo *pic = h265_picture_info->pStdPictureInfo;
588 const VkVideoEncodeH265NaluSliceSegmentInfoKHR *h265_slice = &h265_picture_info->pNaluSliceSegmentEntries[0];
589 const StdVideoEncodeH265SliceSegmentHeader *slice = h265_slice->pStdSliceSegmentHeader;
590 const StdVideoH265SequenceParameterSet *sps =
591 vk_video_find_h265_enc_std_sps(&cmd_buffer->video.params->vk, pic->pps_seq_parameter_set_id);
592 const StdVideoH265PictureParameterSet *pps =
593 vk_video_find_h265_enc_std_pps(&cmd_buffer->video.params->vk, pic->pps_pic_parameter_set_id);
594 ENC_BEGIN;
595 radeon_emit(cs, pdev->vcn_enc_cmds.spec_misc_hevc);
596 radeon_emit(cs, sps->log2_min_luma_coding_block_size_minus3);
597 radeon_emit(cs, !sps->flags.amp_enabled_flag);
598 radeon_emit(cs, sps->flags.strong_intra_smoothing_enabled_flag);
599 radeon_emit(cs, pps->flags.constrained_intra_pred_flag);
600 radeon_emit(cs, slice->flags.cabac_init_flag);
601 radeon_emit(cs, 1); // enc->enc_pic.hevc_spec_misc.half_pel_enabled
602 radeon_emit(cs, 1); // enc->enc_pic.hevc_spec_misc.quarter_pel_enabled
603 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3) {
604 radeon_emit(cs, !pps->flags.transform_skip_enabled_flag);
605 radeon_emit(cs, pps->flags.cu_qp_delta_enabled_flag);
606 }
607 ENC_END;
608 }
609
610 static void
radv_enc_slice_control_hevc(struct radv_cmd_buffer * cmd_buffer,const struct VkVideoEncodeInfoKHR * enc_info)611 radv_enc_slice_control_hevc(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEncodeInfoKHR *enc_info)
612 {
613 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
614 const struct radv_physical_device *pdev = radv_device_physical(device);
615 struct radeon_cmdbuf *cs = cmd_buffer->cs;
616
617 uint32_t width_in_ctb, height_in_ctb, num_ctbs_in_slice;
618
619 width_in_ctb = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.width, 64);
620 height_in_ctb = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.height, 64);
621 num_ctbs_in_slice = width_in_ctb * height_in_ctb;
622 ENC_BEGIN;
623 radeon_emit(cs, pdev->vcn_enc_cmds.slice_control_hevc);
624 radeon_emit(cs, RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS);
625 radeon_emit(cs, num_ctbs_in_slice); // num_ctbs_in_slice
626 radeon_emit(cs, num_ctbs_in_slice); // num_ctbs_in_slice_segment
627 ENC_END;
628 }
629
630 static void
radv_enc_rc_session_init(struct radv_cmd_buffer * cmd_buffer)631 radv_enc_rc_session_init(struct radv_cmd_buffer *cmd_buffer)
632 {
633 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
634 const struct radv_physical_device *pdev = radv_device_physical(device);
635 struct radeon_cmdbuf *cs = cmd_buffer->cs;
636 struct radv_video_session *vid = cmd_buffer->video.vid;
637 ENC_BEGIN;
638 radeon_emit(cs, pdev->vcn_enc_cmds.rc_session_init);
639 radeon_emit(cs, vid->enc_rate_control_method); // rate_control_method);
640 radeon_emit(cs, vid->enc_vbv_buffer_level); // vbv_buffer_level);
641 ENC_END;
642 }
643
644 static void
radv_enc_rc_layer_init(struct radv_cmd_buffer * cmd_buffer,rvcn_enc_rate_ctl_layer_init_t * layer_init)645 radv_enc_rc_layer_init(struct radv_cmd_buffer *cmd_buffer, rvcn_enc_rate_ctl_layer_init_t *layer_init)
646 {
647 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
648 const struct radv_physical_device *pdev = radv_device_physical(device);
649 struct radeon_cmdbuf *cs = cmd_buffer->cs;
650 ENC_BEGIN;
651 radeon_emit(cs, pdev->vcn_enc_cmds.rc_layer_init);
652 radeon_emit(cs, layer_init->target_bit_rate); // target bit rate
653 radeon_emit(cs, layer_init->peak_bit_rate); // peak bit rate
654 radeon_emit(cs, layer_init->frame_rate_num); // frame rate num
655 radeon_emit(cs, layer_init->frame_rate_den); // frame rate dem
656 radeon_emit(cs, layer_init->vbv_buffer_size); // vbv buffer size
657 radeon_emit(cs, layer_init->avg_target_bits_per_picture); // avg target bits per picture
658 radeon_emit(cs, layer_init->peak_bits_per_picture_integer); // peak bit per picture int
659 radeon_emit(cs, layer_init->peak_bits_per_picture_fractional); // peak bit per picture fract
660 ENC_END;
661 }
662
663 static void
radv_enc_deblocking_filter_h264(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)664 radv_enc_deblocking_filter_h264(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
665 {
666 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
667 const struct radv_physical_device *pdev = radv_device_physical(device);
668 struct radeon_cmdbuf *cs = cmd_buffer->cs;
669 const struct VkVideoEncodeH264PictureInfoKHR *h264_picture_info =
670 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H264_PICTURE_INFO_KHR);
671 const VkVideoEncodeH264NaluSliceInfoKHR *h264_slice = &h264_picture_info->pNaluSliceEntries[0];
672 const StdVideoEncodeH264SliceHeader *slice = h264_slice->pStdSliceHeader;
673 ENC_BEGIN;
674 radeon_emit(cs, pdev->vcn_enc_cmds.deblocking_filter_h264);
675 radeon_emit(cs, slice->disable_deblocking_filter_idc);
676 radeon_emit(cs, slice->slice_alpha_c0_offset_div2);
677 radeon_emit(cs, slice->slice_beta_offset_div2);
678 radeon_emit(cs, 0); // cb qp offset
679 radeon_emit(cs, 0); // cr qp offset
680 ENC_END;
681 }
682
683 static void
radv_enc_deblocking_filter_hevc(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)684 radv_enc_deblocking_filter_hevc(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
685 {
686 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
687 const struct radv_physical_device *pdev = radv_device_physical(device);
688 struct radeon_cmdbuf *cs = cmd_buffer->cs;
689 const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
690 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
691 const StdVideoEncodeH265PictureInfo *pic = h265_picture_info->pStdPictureInfo;
692 const VkVideoEncodeH265NaluSliceSegmentInfoKHR *h265_slice = &h265_picture_info->pNaluSliceSegmentEntries[0];
693 const StdVideoEncodeH265SliceSegmentHeader *slice = h265_slice->pStdSliceSegmentHeader;
694 const StdVideoH265SequenceParameterSet *sps =
695 vk_video_find_h265_enc_std_sps(&cmd_buffer->video.params->vk, pic->pps_seq_parameter_set_id);
696
697 ENC_BEGIN;
698 radeon_emit(cs, pdev->vcn_enc_cmds.deblocking_filter_hevc);
699 radeon_emit(cs, slice->flags.slice_loop_filter_across_slices_enabled_flag);
700 radeon_emit(cs, slice->flags.slice_deblocking_filter_disabled_flag);
701 radeon_emit(cs, slice->slice_beta_offset_div2);
702 radeon_emit(cs, slice->slice_tc_offset_div2);
703 radeon_emit(cs, slice->slice_cb_qp_offset);
704 radeon_emit(cs, slice->slice_cr_qp_offset);
705 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_2)
706 radeon_emit(cs, !sps->flags.sample_adaptive_offset_enabled_flag);
707 ENC_END;
708 }
709
710 static void
radv_enc_quality_params(struct radv_cmd_buffer * cmd_buffer)711 radv_enc_quality_params(struct radv_cmd_buffer *cmd_buffer)
712 {
713 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
714 const struct radv_physical_device *pdev = radv_device_physical(device);
715 struct radeon_cmdbuf *cs = cmd_buffer->cs;
716 ENC_BEGIN;
717 radeon_emit(cs, pdev->vcn_enc_cmds.quality_params);
718 radeon_emit(cs, 0);
719 radeon_emit(cs, 0);
720 radeon_emit(cs, 0);
721 radeon_emit(cs, 0);
722 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_2)
723 radeon_emit(cs, 0);
724 ENC_END;
725 }
726
727 static void
radv_enc_slice_header(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)728 radv_enc_slice_header(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
729 {
730 struct radv_enc_state *enc = &cmd_buffer->video.enc;
731 uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
732 uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
733 const struct VkVideoEncodeH264PictureInfoKHR *h264_picture_info =
734 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H264_PICTURE_INFO_KHR);
735 int slice_count = h264_picture_info->naluSliceEntryCount;
736 const StdVideoEncodeH264PictureInfo *pic = h264_picture_info->pStdPictureInfo;
737 const StdVideoH264SequenceParameterSet *sps =
738 vk_video_find_h264_enc_std_sps(&cmd_buffer->video.params->vk, pic->seq_parameter_set_id);
739 const StdVideoH264PictureParameterSet *pps =
740 vk_video_find_h264_enc_std_pps(&cmd_buffer->video.params->vk, pic->pic_parameter_set_id);
741 const VkVideoEncodeH264NaluSliceInfoKHR *slice_info = &h264_picture_info->pNaluSliceEntries[0];
742
743 unsigned int inst_index = 0;
744 unsigned int cdw_start = 0;
745 unsigned int cdw_filled = 0;
746 unsigned int bits_copied = 0;
747
748 assert(slice_count <= 1);
749
750 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
751 const struct radv_physical_device *pdev = radv_device_physical(device);
752 struct radeon_cmdbuf *cs = cmd_buffer->cs;
753 ENC_BEGIN;
754 radeon_emit(cs, pdev->vcn_enc_cmds.slice_header);
755 radv_enc_reset(cmd_buffer);
756 radv_enc_set_emulation_prevention(cmd_buffer, false);
757
758 cdw_start = cs->cdw;
759
760 if (pic->flags.IdrPicFlag)
761 radv_enc_code_fixed_bits(cmd_buffer, 0x65, 8);
762 else if (!pic->flags.is_reference)
763 radv_enc_code_fixed_bits(cmd_buffer, 0x01, 8);
764 else
765 radv_enc_code_fixed_bits(cmd_buffer, 0x41, 8);
766
767 radv_enc_flush_headers(cmd_buffer);
768 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
769 num_bits[inst_index] = enc->bits_output - bits_copied;
770 bits_copied = enc->bits_output;
771 inst_index++;
772
773 instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB;
774 inst_index++;
775
776 switch (pic->primary_pic_type) {
777 case STD_VIDEO_H264_PICTURE_TYPE_I:
778 case STD_VIDEO_H264_PICTURE_TYPE_IDR:
779 default:
780 radv_enc_code_ue(cmd_buffer, 7);
781 break;
782 case STD_VIDEO_H264_PICTURE_TYPE_P:
783 radv_enc_code_ue(cmd_buffer, 5);
784 break;
785 case STD_VIDEO_H264_PICTURE_TYPE_B:
786 radv_enc_code_ue(cmd_buffer, 6);
787 break;
788 }
789 radv_enc_code_ue(cmd_buffer, 0x0);
790
791 unsigned int max_frame_num_bits = sps->log2_max_frame_num_minus4 + 4;
792 radv_enc_code_fixed_bits(cmd_buffer, pic->frame_num % (1 << max_frame_num_bits), max_frame_num_bits);
793 #if 0
794 if (enc->enc_pic.h264_enc_params.input_picture_structure !=
795 RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
796 radv_enc_code_fixed_bits(cmd_buffer, 0x1, 1);
797 radv_enc_code_fixed_bits(cmd_buffer,
798 enc->enc_pic.h264_enc_params.input_picture_structure ==
799 RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD
800 ? 1
801 : 0,
802 1);
803 }
804 #endif
805
806 if (pic->flags.IdrPicFlag)
807 radv_enc_code_ue(cmd_buffer, pic->idr_pic_id);
808
809 if (sps->pic_order_cnt_type == STD_VIDEO_H264_POC_TYPE_0) {
810 unsigned int max_poc_bits = sps->log2_max_pic_order_cnt_lsb_minus4 + 4;
811 radv_enc_code_fixed_bits(cmd_buffer, pic->PicOrderCnt % (1 << max_poc_bits), max_poc_bits);
812 }
813
814 if (pps->flags.redundant_pic_cnt_present_flag)
815 radv_enc_code_ue(cmd_buffer, 0);
816
817 if (pic->primary_pic_type == STD_VIDEO_H264_PICTURE_TYPE_B) {
818 radv_enc_code_fixed_bits(cmd_buffer, slice_info->pStdSliceHeader->flags.direct_spatial_mv_pred_flag, 1);
819 }
820 const StdVideoEncodeH264ReferenceListsInfo *ref_lists = pic->pRefLists;
821 /* ref_pic_list_modification() */
822 if (pic->primary_pic_type != STD_VIDEO_H264_PICTURE_TYPE_IDR &&
823 pic->primary_pic_type != STD_VIDEO_H264_PICTURE_TYPE_I) {
824
825 /* num ref idx active override flag */
826 radv_enc_code_fixed_bits(cmd_buffer, slice_info->pStdSliceHeader->flags.num_ref_idx_active_override_flag, 1);
827 if (slice_info->pStdSliceHeader->flags.num_ref_idx_active_override_flag) {
828 radv_enc_code_ue(cmd_buffer, ref_lists->num_ref_idx_l0_active_minus1);
829 if (pic->primary_pic_type == STD_VIDEO_H264_PICTURE_TYPE_B)
830 radv_enc_code_ue(cmd_buffer, ref_lists->num_ref_idx_l1_active_minus1);
831 }
832
833 radv_enc_code_fixed_bits(cmd_buffer, ref_lists->flags.ref_pic_list_modification_flag_l0, 1);
834 if (ref_lists->flags.ref_pic_list_modification_flag_l0) {
835 for (unsigned op = 0; op < ref_lists->refList0ModOpCount; op++) {
836 const StdVideoEncodeH264RefListModEntry *entry = &ref_lists->pRefList0ModOperations[op];
837
838 radv_enc_code_ue(cmd_buffer, entry->modification_of_pic_nums_idc);
839 if (entry->modification_of_pic_nums_idc ==
840 STD_VIDEO_H264_MODIFICATION_OF_PIC_NUMS_IDC_SHORT_TERM_SUBTRACT ||
841 entry->modification_of_pic_nums_idc == STD_VIDEO_H264_MODIFICATION_OF_PIC_NUMS_IDC_SHORT_TERM_ADD)
842 radv_enc_code_ue(cmd_buffer, entry->abs_diff_pic_num_minus1);
843 else if (entry->modification_of_pic_nums_idc == STD_VIDEO_H264_MODIFICATION_OF_PIC_NUMS_IDC_LONG_TERM)
844 radv_enc_code_ue(cmd_buffer, entry->long_term_pic_num);
845 }
846 }
847
848 if (pic->primary_pic_type == STD_VIDEO_H264_PICTURE_TYPE_B) {
849 radv_enc_code_fixed_bits(cmd_buffer, ref_lists->flags.ref_pic_list_modification_flag_l1, 1);
850 if (ref_lists->flags.ref_pic_list_modification_flag_l1) {
851 for (unsigned op = 0; op < ref_lists->refList1ModOpCount; op++) {
852 const StdVideoEncodeH264RefListModEntry *entry = &ref_lists->pRefList1ModOperations[op];
853
854 radv_enc_code_ue(cmd_buffer, entry->modification_of_pic_nums_idc);
855 if (entry->modification_of_pic_nums_idc ==
856 STD_VIDEO_H264_MODIFICATION_OF_PIC_NUMS_IDC_SHORT_TERM_SUBTRACT ||
857 entry->modification_of_pic_nums_idc == STD_VIDEO_H264_MODIFICATION_OF_PIC_NUMS_IDC_SHORT_TERM_ADD)
858 radv_enc_code_ue(cmd_buffer, entry->abs_diff_pic_num_minus1);
859 else if (entry->modification_of_pic_nums_idc == STD_VIDEO_H264_MODIFICATION_OF_PIC_NUMS_IDC_LONG_TERM)
860 radv_enc_code_ue(cmd_buffer, entry->long_term_pic_num);
861 }
862 }
863 }
864 }
865
866 if (pic->flags.IdrPicFlag) {
867 radv_enc_code_fixed_bits(cmd_buffer, 0x0, 1);
868 radv_enc_code_fixed_bits(cmd_buffer, pic->flags.long_term_reference_flag, 1); /* long_term_reference_flag */
869 } else if (pic->flags.is_reference) {
870 radv_enc_code_fixed_bits(cmd_buffer, ref_lists->refPicMarkingOpCount > 0 ? 1 : 0, 1);
871 for (unsigned op = 0; op < ref_lists->refPicMarkingOpCount; op++) {
872 const StdVideoEncodeH264RefPicMarkingEntry *entry = &ref_lists->pRefPicMarkingOperations[op];
873 radv_enc_code_ue(cmd_buffer, entry->memory_management_control_operation);
874 if (entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_UNMARK_SHORT_TERM ||
875 entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_MARK_LONG_TERM)
876 radv_enc_code_ue(cmd_buffer, entry->difference_of_pic_nums_minus1);
877 if (entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_UNMARK_LONG_TERM)
878 radv_enc_code_ue(cmd_buffer, entry->long_term_pic_num);
879 if (entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_MARK_LONG_TERM ||
880 entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_MARK_CURRENT_AS_LONG_TERM)
881 radv_enc_code_ue(cmd_buffer, entry->long_term_frame_idx);
882 if (entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_SET_MAX_LONG_TERM_INDEX)
883 radv_enc_code_ue(cmd_buffer, entry->max_long_term_frame_idx_plus1);
884 if (entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_END)
885 break;
886 }
887 }
888
889 if (pic->primary_pic_type != STD_VIDEO_H264_PICTURE_TYPE_IDR &&
890 pic->primary_pic_type != STD_VIDEO_H264_PICTURE_TYPE_I && pps->flags.entropy_coding_mode_flag)
891 radv_enc_code_ue(cmd_buffer, slice_info->pStdSliceHeader->cabac_init_idc);
892
893 radv_enc_flush_headers(cmd_buffer);
894 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
895 num_bits[inst_index] = enc->bits_output - bits_copied;
896 bits_copied = enc->bits_output;
897 inst_index++;
898
899 instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
900 inst_index++;
901
902 if (pps->flags.deblocking_filter_control_present_flag) {
903 radv_enc_code_ue(cmd_buffer, slice_info->pStdSliceHeader->disable_deblocking_filter_idc);
904 if (!slice_info->pStdSliceHeader->disable_deblocking_filter_idc) {
905 radv_enc_code_se(cmd_buffer, slice_info->pStdSliceHeader->slice_alpha_c0_offset_div2);
906 radv_enc_code_se(cmd_buffer, slice_info->pStdSliceHeader->slice_beta_offset_div2);
907 }
908 }
909
910 radv_enc_flush_headers(cmd_buffer);
911 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
912 num_bits[inst_index] = enc->bits_output - bits_copied;
913 bits_copied = enc->bits_output;
914 inst_index++;
915
916 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
917
918 cdw_filled = cs->cdw - cdw_start;
919 for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
920 radeon_emit(cs, 0x00000000);
921 for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
922 radeon_emit(cs, instruction[j]);
923 radeon_emit(cs, num_bits[j]);
924 }
925 ENC_END;
926 }
927
928 static void
radv_enc_slice_header_hevc(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)929 radv_enc_slice_header_hevc(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
930 {
931 struct radv_enc_state *enc = &cmd_buffer->video.enc;
932 uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
933 uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
934 const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
935 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
936 const StdVideoEncodeH265PictureInfo *pic = h265_picture_info->pStdPictureInfo;
937 const VkVideoEncodeH265NaluSliceSegmentInfoKHR *h265_slice = &h265_picture_info->pNaluSliceSegmentEntries[0];
938 const StdVideoEncodeH265SliceSegmentHeader *slice = h265_slice->pStdSliceSegmentHeader;
939 const StdVideoH265SequenceParameterSet *sps =
940 vk_video_find_h265_enc_std_sps(&cmd_buffer->video.params->vk, pic->pps_seq_parameter_set_id);
941 const StdVideoH265PictureParameterSet *pps =
942 vk_video_find_h265_enc_std_pps(&cmd_buffer->video.params->vk, pic->pps_pic_parameter_set_id);
943 unsigned int inst_index = 0;
944 unsigned int cdw_start = 0;
945 unsigned int cdw_filled = 0;
946 unsigned int bits_copied = 0;
947 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
948 const struct radv_physical_device *pdev = radv_device_physical(device);
949 struct radeon_cmdbuf *cs = cmd_buffer->cs;
950 unsigned nal_unit_type = vk_video_get_h265_nal_unit(pic);
951
952 ENC_BEGIN;
953 radeon_emit(cs, pdev->vcn_enc_cmds.slice_header);
954 radv_enc_reset(cmd_buffer);
955 radv_enc_set_emulation_prevention(cmd_buffer, false);
956
957 cdw_start = cs->cdw;
958 radv_enc_code_fixed_bits(cmd_buffer, 0x0, 1);
959 radv_enc_code_fixed_bits(cmd_buffer, nal_unit_type, 6);
960 radv_enc_code_fixed_bits(cmd_buffer, 0x0, 6);
961 radv_enc_code_fixed_bits(cmd_buffer, pic->TemporalId + 1, 3);
962
963 radv_enc_flush_headers(cmd_buffer);
964 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
965 num_bits[inst_index] = enc->bits_output - bits_copied;
966 bits_copied = enc->bits_output;
967 inst_index++;
968
969 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
970 inst_index++;
971
972 if ((nal_unit_type >= 16) && (nal_unit_type <= 23))
973 radv_enc_code_fixed_bits(cmd_buffer, 0x0, 1);
974
975 radv_enc_code_ue(cmd_buffer, pic->pps_pic_parameter_set_id);
976
977 radv_enc_flush_headers(cmd_buffer);
978 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
979 num_bits[inst_index] = enc->bits_output - bits_copied;
980 bits_copied = enc->bits_output;
981 inst_index++;
982
983 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
984 inst_index++;
985
986 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
987 inst_index++;
988
989 /* slice_type */
990 switch (pic->pic_type) {
991 case STD_VIDEO_H265_PICTURE_TYPE_I:
992 case STD_VIDEO_H265_PICTURE_TYPE_IDR:
993 radv_enc_code_ue(cmd_buffer, 0x2);
994 break;
995 case STD_VIDEO_H265_PICTURE_TYPE_P:
996 radv_enc_code_ue(cmd_buffer, 0x1);
997 break;
998 case STD_VIDEO_H265_PICTURE_TYPE_B:
999 radv_enc_code_ue(cmd_buffer, 0x0);
1000 break;
1001 default:
1002 radv_enc_code_ue(cmd_buffer, 0x1);
1003 }
1004
1005 if ((nal_unit_type != 19) && nal_unit_type != 20) {
1006 /* slice_pic_order_cnt_lsb */
1007 unsigned int max_poc_bits = sps->log2_max_pic_order_cnt_lsb_minus4 + 4;
1008 radv_enc_code_fixed_bits(cmd_buffer, pic->PicOrderCntVal % (1 << max_poc_bits), max_poc_bits);
1009 radv_enc_code_fixed_bits(cmd_buffer, pic->flags.short_term_ref_pic_set_sps_flag, 0x1);
1010 if (!pic->flags.short_term_ref_pic_set_sps_flag) {
1011 int st_rps_idx = sps->num_short_term_ref_pic_sets;
1012 const StdVideoH265ShortTermRefPicSet *rps = &pic->pShortTermRefPicSet[st_rps_idx];
1013
1014 if (st_rps_idx != 0)
1015 radv_enc_code_fixed_bits(cmd_buffer, rps->flags.inter_ref_pic_set_prediction_flag, 0x1);
1016
1017 if (rps->flags.inter_ref_pic_set_prediction_flag) {
1018 int ref_rps_idx = st_rps_idx - (rps->delta_idx_minus1 + 1);
1019 if (st_rps_idx == sps->num_short_term_ref_pic_sets)
1020 radv_enc_code_ue(cmd_buffer, rps->delta_idx_minus1);
1021 radv_enc_code_fixed_bits(cmd_buffer, rps->flags.delta_rps_sign, 0x1);
1022 radv_enc_code_ue(cmd_buffer, rps->abs_delta_rps_minus1);
1023
1024 const StdVideoH265ShortTermRefPicSet *rps_ref = &sps->pShortTermRefPicSet[ref_rps_idx];
1025 int num_delta_pocs = rps_ref->num_negative_pics + rps_ref->num_positive_pics;
1026 for (int j = 0; j < num_delta_pocs; j++) {
1027 radv_enc_code_fixed_bits(cmd_buffer, !!(rps->used_by_curr_pic_flag & (1 << j)), 0x1);
1028 if (!(rps->used_by_curr_pic_flag & (1 << j))) {
1029 radv_enc_code_fixed_bits(cmd_buffer, !!(rps->use_delta_flag & (1 << j)), 0x1);
1030 }
1031 }
1032 } else {
1033 radv_enc_code_ue(cmd_buffer, rps->num_negative_pics);
1034 radv_enc_code_ue(cmd_buffer, rps->num_positive_pics);
1035
1036 for (int i = 0; i < rps->num_negative_pics; i++) {
1037 radv_enc_code_ue(cmd_buffer, rps->delta_poc_s0_minus1[i]);
1038 radv_enc_code_fixed_bits(cmd_buffer, !!(rps->used_by_curr_pic_s0_flag & (1 << i)), 0x1);
1039 }
1040 for (int i = 0; i < rps->num_positive_pics; i++) {
1041 radv_enc_code_ue(cmd_buffer, rps->delta_poc_s1_minus1[i]);
1042 radv_enc_code_fixed_bits(cmd_buffer, !!(rps->used_by_curr_pic_s1_flag & (1 << i)), 0x1);
1043 }
1044 }
1045 } else if (sps->num_short_term_ref_pic_sets > 1)
1046 radv_enc_code_ue(cmd_buffer, pic->short_term_ref_pic_set_idx);
1047
1048 if (sps->flags.sps_temporal_mvp_enabled_flag)
1049 radv_enc_code_fixed_bits(cmd_buffer, pic->flags.slice_temporal_mvp_enabled_flag, 1);
1050 }
1051
1052 if (sps->flags.sample_adaptive_offset_enabled_flag) {
1053 radv_enc_flush_headers(cmd_buffer);
1054 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1055 num_bits[inst_index] = enc->bits_output - bits_copied;
1056 bits_copied = enc->bits_output;
1057 inst_index++;
1058
1059 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SAO_ENABLE;
1060 inst_index++;
1061 }
1062
1063 if ((pic->pic_type == STD_VIDEO_H265_PICTURE_TYPE_P) || (pic->pic_type == STD_VIDEO_H265_PICTURE_TYPE_B)) {
1064 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.num_ref_idx_active_override_flag, 1);
1065 if (slice->flags.num_ref_idx_active_override_flag) {
1066 radv_enc_code_ue(cmd_buffer, pic->pRefLists->num_ref_idx_l0_active_minus1);
1067 if (pic->pic_type == STD_VIDEO_H265_PICTURE_TYPE_B)
1068 radv_enc_code_ue(cmd_buffer, pic->pRefLists->num_ref_idx_l1_active_minus1);
1069 }
1070 if (pic->pic_type == STD_VIDEO_H265_PICTURE_TYPE_B)
1071 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.mvd_l1_zero_flag, 1);
1072 if (pps->flags.cabac_init_present_flag)
1073 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.cabac_init_flag, 1);
1074 if (pic->flags.slice_temporal_mvp_enabled_flag) {
1075 if (pic->pic_type == STD_VIDEO_H265_PICTURE_TYPE_B)
1076 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.collocated_from_l0_flag, 1);
1077 }
1078 radv_enc_code_ue(cmd_buffer, 5 - slice->MaxNumMergeCand);
1079 }
1080
1081 radv_enc_flush_headers(cmd_buffer);
1082 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1083 num_bits[inst_index] = enc->bits_output - bits_copied;
1084 bits_copied = enc->bits_output;
1085 inst_index++;
1086
1087 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
1088 inst_index++;
1089
1090 if (pps->flags.pps_slice_chroma_qp_offsets_present_flag) {
1091 radv_enc_code_se(cmd_buffer, slice->slice_cb_qp_offset);
1092 radv_enc_code_se(cmd_buffer, slice->slice_cr_qp_offset);
1093 }
1094
1095 if (pps->flags.pps_slice_act_qp_offsets_present_flag) {
1096 radv_enc_code_se(cmd_buffer, slice->slice_act_y_qp_offset);
1097 radv_enc_code_se(cmd_buffer, slice->slice_act_cb_qp_offset);
1098 radv_enc_code_se(cmd_buffer, slice->slice_act_cr_qp_offset);
1099 }
1100
1101 if (pps->flags.chroma_qp_offset_list_enabled_flag) {
1102 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.cu_chroma_qp_offset_enabled_flag, 1);
1103 }
1104
1105 if (pps->flags.deblocking_filter_override_enabled_flag) {
1106 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.deblocking_filter_override_flag, 1);
1107 if (slice->flags.deblocking_filter_override_flag) {
1108 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.slice_deblocking_filter_disabled_flag, 1);
1109 if (!slice->flags.slice_deblocking_filter_disabled_flag) {
1110 radv_enc_code_se(cmd_buffer, slice->slice_beta_offset_div2);
1111 radv_enc_code_se(cmd_buffer, slice->slice_tc_offset_div2);
1112 }
1113 }
1114 }
1115 if ((pps->flags.pps_loop_filter_across_slices_enabled_flag) &&
1116 (!slice->flags.slice_deblocking_filter_disabled_flag || slice->flags.slice_sao_luma_flag ||
1117 slice->flags.slice_sao_chroma_flag)) {
1118
1119 if (slice->flags.slice_sao_luma_flag || slice->flags.slice_sao_chroma_flag) {
1120 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_LOOP_FILTER_ACROSS_SLICES_ENABLE;
1121 inst_index++;
1122 } else {
1123 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.slice_loop_filter_across_slices_enabled_flag, 1);
1124 radv_enc_flush_headers(cmd_buffer);
1125 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1126 num_bits[inst_index] = enc->bits_output - bits_copied;
1127 bits_copied = enc->bits_output;
1128 inst_index++;
1129 }
1130 }
1131
1132 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
1133
1134 cdw_filled = cs->cdw - cdw_start;
1135 for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
1136 radeon_emit(cs, 0x00000000);
1137 for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
1138 radeon_emit(cs, instruction[j]);
1139 radeon_emit(cs, num_bits[j]);
1140 }
1141 ENC_END;
1142 }
1143
1144 static void
radv_enc_ctx(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * info)1145 radv_enc_ctx(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *info)
1146 {
1147 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1148 const struct radv_physical_device *pdev = radv_device_physical(device);
1149 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1150 struct radv_image_view *dpb_iv = NULL;
1151 struct radv_image *dpb = NULL;
1152 struct radv_image_plane *dpb_luma = NULL;
1153 struct radv_image_plane *dpb_chroma = NULL;
1154 uint64_t va = 0;
1155 uint32_t luma_pitch = 0;
1156 int max_ref_slot_idx = 0;
1157
1158 if (info->pSetupReferenceSlot) {
1159 dpb_iv = radv_image_view_from_handle(info->pSetupReferenceSlot->pPictureResource->imageViewBinding);
1160 if (info->pSetupReferenceSlot->slotIndex > max_ref_slot_idx)
1161 max_ref_slot_idx = info->pSetupReferenceSlot->slotIndex;
1162 }
1163
1164 if (info->referenceSlotCount > 0) {
1165 dpb_iv = radv_image_view_from_handle(info->pReferenceSlots[0].pPictureResource->imageViewBinding);
1166 for (unsigned i = 0; i < info->referenceSlotCount; i++) {
1167 if (info->pReferenceSlots[i].slotIndex > max_ref_slot_idx)
1168 max_ref_slot_idx = info->pReferenceSlots[i].slotIndex;
1169 }
1170 }
1171
1172 if (dpb_iv) {
1173 dpb = dpb_iv->image;
1174 dpb_luma = &dpb->planes[0];
1175 dpb_chroma = &dpb->planes[1];
1176 radv_cs_add_buffer(device->ws, cs, dpb->bindings[0].bo);
1177 va = radv_buffer_get_va(dpb->bindings[0].bo) + dpb->bindings[0].offset; // TODO DPB resource
1178 luma_pitch = dpb_luma->surface.u.gfx9.surf_pitch * dpb_luma->surface.blk_w; // rec_luma_pitch
1179 }
1180
1181 uint32_t swizzle_mode = 0;
1182
1183 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4)
1184 swizzle_mode = RENCODE_REC_SWIZZLE_MODE_256B_D;
1185 else if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_2)
1186 swizzle_mode = RENCODE_REC_SWIZZLE_MODE_256B_S;
1187 ENC_BEGIN;
1188 radeon_emit(cs, pdev->vcn_enc_cmds.ctx);
1189 radeon_emit(cs, va >> 32);
1190 radeon_emit(cs, va & 0xffffffff);
1191 radeon_emit(cs, swizzle_mode);
1192 radeon_emit(cs, luma_pitch); // rec_luma_pitch
1193 radeon_emit(cs, luma_pitch); // rec_luma_pitch0); //rec_chromma_pitch
1194 radeon_emit(cs, max_ref_slot_idx + 1); // num_reconstructed_pictures
1195
1196 int i;
1197 for (i = 0; i < max_ref_slot_idx + 1; i++) {
1198 radeon_emit(cs, dpb_luma ? dpb_luma->surface.u.gfx9.surf_offset + i * dpb_luma->surface.u.gfx9.surf_slice_size
1199 : 0); // luma offset
1200 radeon_emit(cs, dpb_chroma
1201 ? dpb_chroma->surface.u.gfx9.surf_offset + i * dpb_chroma->surface.u.gfx9.surf_slice_size
1202 : 0); // chroma offset
1203
1204 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4) {
1205 radeon_emit(cs, 0); /* unused offset 1 */
1206 radeon_emit(cs, 0); /* unused offset 2 */
1207 }
1208 }
1209
1210 for (; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
1211 radeon_emit(cs, 0);
1212 radeon_emit(cs, 0);
1213 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4) {
1214 radeon_emit(cs, 0); /* unused offset 1 */
1215 radeon_emit(cs, 0); /* unused offset 2 */
1216 }
1217 }
1218
1219 if (pdev->enc_hw_ver == RADV_VIDEO_ENC_HW_3) {
1220 radeon_emit(cs, 0); // colloc buffer offset
1221 }
1222 radeon_emit(cs, 0); // enc pic pre encode luma pitch
1223 radeon_emit(cs, 0); // enc pic pre encode chroma pitch
1224
1225 for (i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
1226 radeon_emit(cs, 0); // pre encode luma offset
1227 radeon_emit(cs, 0); // pre encode chroma offset
1228 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4) {
1229 radeon_emit(cs, 0); /* unused offset 1 */
1230 radeon_emit(cs, 0); /* unused offset 2 */
1231 }
1232 }
1233
1234 if (pdev->enc_hw_ver == RADV_VIDEO_ENC_HW_2) {
1235 radeon_emit(cs, 0); // enc pic yuv luma offset
1236 radeon_emit(cs, 0); // enc pic yuv chroma offset
1237
1238 radeon_emit(cs, 0); // two pass search center map offset
1239
1240 // rgboffsets
1241 radeon_emit(cs, 0); // red
1242 radeon_emit(cs, 0); // green
1243 radeon_emit(cs, 0); // blue
1244 } else if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3) {
1245 radeon_emit(cs, 0); // red
1246 radeon_emit(cs, 0); // green
1247 radeon_emit(cs, 0); // blue
1248 radeon_emit(cs, 0); // v3 two pass search center map offset
1249 radeon_emit(cs, 0);
1250 if (pdev->enc_hw_ver == RADV_VIDEO_ENC_HW_3) {
1251 radeon_emit(cs, 0);
1252 }
1253 }
1254 ENC_END;
1255 }
1256
1257 static void
radv_enc_bitstream(struct radv_cmd_buffer * cmd_buffer,struct radv_buffer * buffer,VkDeviceSize offset)1258 radv_enc_bitstream(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buffer, VkDeviceSize offset)
1259 {
1260 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1261 const struct radv_physical_device *pdev = radv_device_physical(device);
1262 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1263 uint64_t va = radv_buffer_get_va(buffer->bo) + buffer->offset + offset;
1264 radv_cs_add_buffer(device->ws, cs, buffer->bo);
1265
1266 ENC_BEGIN;
1267 radeon_emit(cs, pdev->vcn_enc_cmds.bitstream);
1268 radeon_emit(cs, RENCODE_REC_SWIZZLE_MODE_LINEAR);
1269 radeon_emit(cs, va >> 32);
1270 radeon_emit(cs, va & 0xffffffff);
1271 radeon_emit(cs, buffer->vk.size);
1272 radeon_emit(cs, 0);
1273 ENC_END;
1274 }
1275
1276 static void
radv_enc_feedback(struct radv_cmd_buffer * cmd_buffer,uint64_t feedback_query_va)1277 radv_enc_feedback(struct radv_cmd_buffer *cmd_buffer, uint64_t feedback_query_va)
1278 {
1279 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1280 const struct radv_physical_device *pdev = radv_device_physical(device);
1281 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1282 ENC_BEGIN;
1283
1284 radeon_emit(cs, pdev->vcn_enc_cmds.feedback);
1285 radeon_emit(cs, RENCODE_FEEDBACK_BUFFER_MODE_LINEAR);
1286 radeon_emit(cs, feedback_query_va >> 32);
1287 radeon_emit(cs, feedback_query_va & 0xffffffff);
1288 radeon_emit(cs, 16); // buffer_size
1289 radeon_emit(cs, 40); // data_size
1290 ENC_END;
1291 }
1292
1293 static void
radv_enc_intra_refresh(struct radv_cmd_buffer * cmd_buffer)1294 radv_enc_intra_refresh(struct radv_cmd_buffer *cmd_buffer)
1295 {
1296 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1297 const struct radv_physical_device *pdev = radv_device_physical(device);
1298 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1299 ENC_BEGIN;
1300 radeon_emit(cs, pdev->vcn_enc_cmds.intra_refresh);
1301 radeon_emit(cs, 0); // intra refresh mode
1302 radeon_emit(cs, 0); // intra ref offset
1303 radeon_emit(cs, 0); // intra region size
1304 ENC_END;
1305 }
1306
1307 static void
radv_enc_rc_per_pic(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info,rvcn_enc_rate_ctl_per_picture_t * per_pic)1308 radv_enc_rc_per_pic(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info,
1309 rvcn_enc_rate_ctl_per_picture_t *per_pic)
1310 {
1311 struct radv_video_session *vid = cmd_buffer->video.vid;
1312 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1313 const struct radv_physical_device *pdev = radv_device_physical(device);
1314 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1315
1316 unsigned qp = per_pic->qp_i;
1317
1318 if (vid->enc_rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE && !vid->enc_rate_control_default) {
1319 switch (vid->vk.op) {
1320 case VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR: {
1321 const struct VkVideoEncodeH264PictureInfoKHR *h264_picture_info =
1322 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H264_PICTURE_INFO_KHR);
1323 const VkVideoEncodeH264NaluSliceInfoKHR *h264_slice = &h264_picture_info->pNaluSliceEntries[0];
1324 qp = h264_slice->constantQp;
1325 break;
1326 }
1327 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR: {
1328 const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
1329 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
1330 const VkVideoEncodeH265NaluSliceSegmentInfoKHR *h265_slice = &h265_picture_info->pNaluSliceSegmentEntries[0];
1331 qp = h265_slice->constantQp;
1332 break;
1333 }
1334 default:
1335 break;
1336 }
1337 }
1338 ENC_BEGIN;
1339 radeon_emit(cs, pdev->vcn_enc_cmds.rc_per_pic);
1340 radeon_emit(cs, qp); // qp_i
1341 radeon_emit(cs, qp); // qp_p
1342 radeon_emit(cs, qp); // qp_b
1343 radeon_emit(cs, per_pic->min_qp_i);
1344 radeon_emit(cs, per_pic->max_qp_i);
1345 radeon_emit(cs, per_pic->min_qp_p);
1346 radeon_emit(cs, per_pic->max_qp_p);
1347 radeon_emit(cs, per_pic->min_qp_b);
1348 radeon_emit(cs, per_pic->max_qp_b);
1349 radeon_emit(cs, per_pic->max_au_size_i);
1350 radeon_emit(cs, per_pic->max_au_size_p);
1351 radeon_emit(cs, per_pic->max_au_size_b);
1352 radeon_emit(cs, per_pic->enabled_filler_data);
1353 radeon_emit(cs, per_pic->skip_frame_enable);
1354 radeon_emit(cs, per_pic->enforce_hrd);
1355 radeon_emit(cs, 0xFFFFFFFF); // reserved_0xff
1356 ENC_END;
1357 }
1358
1359 static void
radv_enc_params(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)1360 radv_enc_params(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
1361 {
1362 const struct VkVideoEncodeH264PictureInfoKHR *h264_picture_info =
1363 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H264_PICTURE_INFO_KHR);
1364 const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
1365 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
1366 const StdVideoEncodeH264PictureInfo *h264_pic = h264_picture_info ? h264_picture_info->pStdPictureInfo : NULL;
1367 const StdVideoEncodeH265PictureInfo *h265_pic = h265_picture_info ? h265_picture_info->pStdPictureInfo : NULL;
1368 struct radv_image_view *src_iv = radv_image_view_from_handle(enc_info->srcPictureResource.imageViewBinding);
1369 struct radv_image *src_img = src_iv->image;
1370 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1371 const struct radv_physical_device *pdev = radv_device_physical(device);
1372 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1373 uint64_t va = radv_buffer_get_va(src_img->bindings[0].bo) + src_img->bindings[0].offset;
1374 uint64_t luma_va = va + src_img->planes[0].surface.u.gfx9.surf_offset;
1375 uint64_t chroma_va = va + src_img->planes[1].surface.u.gfx9.surf_offset;
1376 uint32_t pic_type;
1377 unsigned int slot_idx = 0xffffffff;
1378 unsigned int max_layers = cmd_buffer->video.vid->rc_layer_control.max_num_temporal_layers;
1379
1380 radv_cs_add_buffer(device->ws, cs, src_img->bindings[0].bo);
1381 if (h264_pic) {
1382 switch (h264_pic->primary_pic_type) {
1383 case STD_VIDEO_H264_PICTURE_TYPE_P:
1384 slot_idx = enc_info->pReferenceSlots[0].slotIndex;
1385 pic_type = RENCODE_PICTURE_TYPE_P;
1386 break;
1387 case STD_VIDEO_H264_PICTURE_TYPE_B:
1388 slot_idx = enc_info->pReferenceSlots[0].slotIndex;
1389 pic_type = RENCODE_PICTURE_TYPE_B;
1390 break;
1391 case STD_VIDEO_H264_PICTURE_TYPE_I:
1392 case STD_VIDEO_H264_PICTURE_TYPE_IDR:
1393 default:
1394 pic_type = RENCODE_PICTURE_TYPE_I;
1395 break;
1396 }
1397 radv_enc_layer_select(cmd_buffer, MIN2(h264_pic->temporal_id, max_layers));
1398 } else if (h265_pic) {
1399 switch (h265_pic->pic_type) {
1400 case STD_VIDEO_H265_PICTURE_TYPE_P:
1401 slot_idx = enc_info->pReferenceSlots[0].slotIndex;
1402 pic_type = RENCODE_PICTURE_TYPE_P;
1403 break;
1404 case STD_VIDEO_H265_PICTURE_TYPE_B:
1405 slot_idx = enc_info->pReferenceSlots[0].slotIndex;
1406 pic_type = RENCODE_PICTURE_TYPE_B;
1407 break;
1408 case STD_VIDEO_H265_PICTURE_TYPE_I:
1409 case STD_VIDEO_H265_PICTURE_TYPE_IDR:
1410 default:
1411 pic_type = RENCODE_PICTURE_TYPE_I;
1412 break;
1413 }
1414 radv_enc_layer_select(cmd_buffer, MIN2(h265_pic->TemporalId, max_layers));
1415 } else {
1416 assert(0);
1417 return;
1418 }
1419
1420 ENC_BEGIN;
1421 radeon_emit(cs, pdev->vcn_enc_cmds.enc_params);
1422 radeon_emit(cs, pic_type); // pic type
1423 radeon_emit(cs, enc_info->dstBufferRange); // allowed max bitstream size
1424 radeon_emit(cs, luma_va >> 32);
1425 radeon_emit(cs, luma_va & 0xffffffff);
1426 radeon_emit(cs, chroma_va >> 32);
1427 radeon_emit(cs, chroma_va & 0xffffffff);
1428 radeon_emit(cs, src_img->planes[0].surface.u.gfx9.surf_pitch); // luma pitch
1429 radeon_emit(cs, src_img->planes[1].surface.u.gfx9.surf_pitch); // chroma pitch
1430 radeon_emit(cs, src_img->planes[0].surface.u.gfx9.swizzle_mode); // swizzle mode
1431 radeon_emit(cs, slot_idx); // ref0_idx
1432
1433 if (enc_info->pSetupReferenceSlot)
1434 radeon_emit(cs, enc_info->pSetupReferenceSlot->slotIndex); // reconstructed picture index
1435 else
1436 radeon_emit(cs, 0);
1437 ENC_END;
1438 }
1439
1440 static void
radv_enc_params_h264(struct radv_cmd_buffer * cmd_buffer)1441 radv_enc_params_h264(struct radv_cmd_buffer *cmd_buffer)
1442 {
1443 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1444 const struct radv_physical_device *pdev = radv_device_physical(device);
1445 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1446 ENC_BEGIN;
1447 radeon_emit(cs, pdev->vcn_enc_cmds.enc_params_h264);
1448
1449 if (pdev->enc_hw_ver < RADV_VIDEO_ENC_HW_3) {
1450 radeon_emit(cs, RENCODE_H264_PICTURE_STRUCTURE_FRAME);
1451 radeon_emit(cs, RENCODE_H264_INTERLACING_MODE_PROGRESSIVE);
1452 radeon_emit(cs, RENCODE_H264_PICTURE_STRUCTURE_FRAME);
1453 radeon_emit(cs, 0xffffffff); // reference_picture1_index
1454 } else {
1455 // V3
1456 radeon_emit(cs, RENCODE_H264_PICTURE_STRUCTURE_FRAME);
1457 radeon_emit(cs, 0); // input pic order cnt
1458 radeon_emit(cs, RENCODE_H264_INTERLACING_MODE_PROGRESSIVE);
1459 radeon_emit(cs, 0); // l0 ref pic0 pic_type
1460 radeon_emit(cs, 0); // l0 ref pic0 is long term
1461 radeon_emit(cs, 0); // l0 ref pic0 picture structure
1462 radeon_emit(cs, 0); // l0 ref pic0 pic order cnt
1463 radeon_emit(cs, 0xffffffff); // l0 ref pic1 index
1464 radeon_emit(cs, 0); // l0 ref pic1 pic_type
1465 radeon_emit(cs, 0); // l0 ref pic1 is long term
1466 radeon_emit(cs, 0); // l0 ref pic1 picture structure
1467 radeon_emit(cs, 0); // l0 ref pic1 pic order cnt
1468 radeon_emit(cs, 0xffffffff); // l1 ref pic0 index
1469 radeon_emit(cs, 0); // l1 ref pic0 pic_type
1470 radeon_emit(cs, 0); // l1 ref pic0 is long term
1471 radeon_emit(cs, 0); // l1 ref pic0 picture structure
1472 radeon_emit(cs, 0); // l1 ref pic0 pic order cnt
1473 }
1474 ENC_END;
1475 }
1476
1477 static void
radv_enc_op_init(struct radv_cmd_buffer * cmd_buffer)1478 radv_enc_op_init(struct radv_cmd_buffer *cmd_buffer)
1479 {
1480 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1481 ENC_BEGIN;
1482 radeon_emit(cs, RENCODE_IB_OP_INITIALIZE);
1483 ENC_END;
1484 }
1485
1486 static void
radv_enc_op_enc(struct radv_cmd_buffer * cmd_buffer)1487 radv_enc_op_enc(struct radv_cmd_buffer *cmd_buffer)
1488 {
1489 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1490 ENC_BEGIN;
1491 radeon_emit(cs, RENCODE_IB_OP_ENCODE);
1492 ENC_END;
1493 }
1494
1495 static void
radv_enc_op_init_rc(struct radv_cmd_buffer * cmd_buffer)1496 radv_enc_op_init_rc(struct radv_cmd_buffer *cmd_buffer)
1497 {
1498 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1499 ENC_BEGIN;
1500 radeon_emit(cs, RENCODE_IB_OP_INIT_RC);
1501 ENC_END;
1502 }
1503
1504 static void
radv_enc_op_init_rc_vbv(struct radv_cmd_buffer * cmd_buffer)1505 radv_enc_op_init_rc_vbv(struct radv_cmd_buffer *cmd_buffer)
1506 {
1507 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1508 ENC_BEGIN;
1509 radeon_emit(cs, RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
1510 ENC_END;
1511 }
1512
1513 static void
radv_enc_op_preset(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)1514 radv_enc_op_preset(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
1515 {
1516 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1517 struct radv_video_session *vid = cmd_buffer->video.vid;
1518 uint32_t preset_mode;
1519
1520 switch (vid->vk.op) {
1521 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR: {
1522 const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
1523 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
1524 const StdVideoEncodeH265PictureInfo *pic = h265_picture_info->pStdPictureInfo;
1525 const StdVideoH265SequenceParameterSet *sps =
1526 vk_video_find_h265_enc_std_sps(&cmd_buffer->video.params->vk, pic->pps_seq_parameter_set_id);
1527 if (sps->flags.sample_adaptive_offset_enabled_flag && vid->enc_preset_mode == RENCODE_PRESET_MODE_SPEED) {
1528 preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE;
1529 return;
1530 }
1531 break;
1532 }
1533 default:
1534 break;
1535 }
1536
1537 if (vid->enc_preset_mode == RENCODE_PRESET_MODE_QUALITY)
1538 preset_mode = RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE;
1539 else if (vid->enc_preset_mode == RENCODE_PRESET_MODE_BALANCE)
1540 preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE;
1541 else
1542 preset_mode = RENCODE_IB_OP_SET_SPEED_ENCODING_MODE;
1543 ENC_BEGIN;
1544 radeon_emit(cs, preset_mode);
1545 ENC_END;
1546 }
1547
1548 static void
radv_enc_input_format(struct radv_cmd_buffer * cmd_buffer)1549 radv_enc_input_format(struct radv_cmd_buffer *cmd_buffer)
1550 {
1551 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1552 const struct radv_physical_device *pdev = radv_device_physical(device);
1553 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1554 struct radv_video_session *vid = cmd_buffer->video.vid;
1555 uint32_t color_bit_depth;
1556 uint32_t color_packing_format;
1557
1558 switch (vid->vk.picture_format) {
1559 case VK_FORMAT_G8_B8R8_2PLANE_420_UNORM:
1560 color_bit_depth = RENCODE_COLOR_BIT_DEPTH_8_BIT;
1561 color_packing_format = RENCODE_COLOR_PACKING_FORMAT_NV12;
1562 break;
1563 case VK_FORMAT_G10X6_B10X6R10X6_2PLANE_420_UNORM_3PACK16:
1564 color_bit_depth = RENCODE_COLOR_BIT_DEPTH_10_BIT;
1565 color_packing_format = RENCODE_COLOR_PACKING_FORMAT_P010;
1566 break;
1567 default:
1568 assert(0);
1569 return;
1570 }
1571
1572 ENC_BEGIN;
1573 radeon_emit(cs, pdev->vcn_enc_cmds.input_format);
1574 radeon_emit(cs, 0); // input color volume
1575 radeon_emit(cs, 0); // input color space
1576 radeon_emit(cs, RENCODE_COLOR_RANGE_STUDIO); // input color range
1577 radeon_emit(cs, 0); // input chroma subsampling
1578 radeon_emit(cs, 0); // input chroma location
1579 radeon_emit(cs, color_bit_depth); // input color bit depth
1580 radeon_emit(cs, color_packing_format); // input color packing format
1581 ENC_END;
1582 }
1583
1584 static void
radv_enc_output_format(struct radv_cmd_buffer * cmd_buffer)1585 radv_enc_output_format(struct radv_cmd_buffer *cmd_buffer)
1586 {
1587 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1588 const struct radv_physical_device *pdev = radv_device_physical(device);
1589 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1590 struct radv_video_session *vid = cmd_buffer->video.vid;
1591 uint32_t color_bit_depth;
1592
1593 switch (vid->vk.op) {
1594 case VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR:
1595 color_bit_depth = RENCODE_COLOR_BIT_DEPTH_8_BIT;
1596 break;
1597 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR:
1598 if (vid->vk.h265.profile_idc == STD_VIDEO_H265_PROFILE_IDC_MAIN_10)
1599 color_bit_depth = RENCODE_COLOR_BIT_DEPTH_10_BIT;
1600 else
1601 color_bit_depth = RENCODE_COLOR_BIT_DEPTH_8_BIT;
1602 break;
1603 default:
1604 assert(0);
1605 return;
1606 }
1607
1608 ENC_BEGIN;
1609 radeon_emit(cs, pdev->vcn_enc_cmds.output_format);
1610 radeon_emit(cs, 0); // output color volume
1611 radeon_emit(cs, RENCODE_COLOR_RANGE_STUDIO); // output color range
1612 radeon_emit(cs, 0); // output chroma location
1613 radeon_emit(cs, color_bit_depth); // output color bit depth
1614 ENC_END;
1615 }
1616
1617 static void
radv_enc_headers_h264(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)1618 radv_enc_headers_h264(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
1619 {
1620 radv_enc_slice_header(cmd_buffer, enc_info);
1621 radv_enc_params(cmd_buffer, enc_info);
1622 radv_enc_params_h264(cmd_buffer);
1623 }
1624
1625 static void
radv_enc_headers_hevc(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)1626 radv_enc_headers_hevc(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
1627 {
1628 radv_enc_slice_header_hevc(cmd_buffer, enc_info);
1629 radv_enc_params(cmd_buffer, enc_info);
1630 }
1631
1632 static void
begin(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)1633 begin(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
1634 {
1635 struct radv_video_session *vid = cmd_buffer->video.vid;
1636
1637 radv_enc_op_init(cmd_buffer);
1638 radv_enc_session_init(cmd_buffer, enc_info);
1639 if (vid->vk.op == VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR) {
1640 radv_enc_slice_control(cmd_buffer, enc_info);
1641 radv_enc_spec_misc_h264(cmd_buffer, enc_info);
1642 radv_enc_deblocking_filter_h264(cmd_buffer, enc_info);
1643 } else if (vid->vk.op == VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR) {
1644 radv_enc_slice_control_hevc(cmd_buffer, enc_info);
1645 radv_enc_spec_misc_hevc(cmd_buffer, enc_info);
1646 radv_enc_deblocking_filter_hevc(cmd_buffer, enc_info);
1647 }
1648 radv_enc_layer_control(cmd_buffer, &vid->rc_layer_control);
1649 radv_enc_rc_session_init(cmd_buffer);
1650 radv_enc_quality_params(cmd_buffer);
1651 // temporal layers init
1652 unsigned i = 0;
1653 do {
1654 radv_enc_layer_select(cmd_buffer, i);
1655 radv_enc_rc_layer_init(cmd_buffer, &vid->rc_layer_init[i]);
1656 radv_enc_layer_select(cmd_buffer, i);
1657 radv_enc_rc_per_pic(cmd_buffer, enc_info, &vid->rc_per_pic[i]);
1658 } while (++i < vid->rc_layer_control.num_temporal_layers);
1659 radv_enc_op_init_rc(cmd_buffer);
1660 radv_enc_op_init_rc_vbv(cmd_buffer);
1661 }
1662
1663 static void
radv_vcn_encode_video(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)1664 radv_vcn_encode_video(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
1665 {
1666 VK_FROM_HANDLE(radv_buffer, dst_buffer, enc_info->dstBuffer);
1667 struct radv_video_session *vid = cmd_buffer->video.vid;
1668 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1669 const struct radv_physical_device *pdev = radv_device_physical(device);
1670 struct radv_enc_state *enc = &cmd_buffer->video.enc;
1671 uint64_t feedback_query_va;
1672 switch (vid->vk.op) {
1673 case VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR:
1674 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR:
1675 break;
1676 default:
1677 assert(0);
1678 return;
1679 }
1680
1681 const struct VkVideoInlineQueryInfoKHR *inline_queries = NULL;
1682 if (vid->vk.flags & VK_VIDEO_SESSION_CREATE_INLINE_QUERIES_BIT_KHR) {
1683 inline_queries = vk_find_struct_const(enc_info->pNext, VIDEO_INLINE_QUERY_INFO_KHR);
1684
1685 if (inline_queries) {
1686 VK_FROM_HANDLE(radv_query_pool, pool, inline_queries->queryPool);
1687 feedback_query_va = radv_buffer_get_va(pool->bo);
1688 feedback_query_va += pool->stride * inline_queries->firstQuery;
1689 }
1690 }
1691
1692 if (!inline_queries)
1693 feedback_query_va = cmd_buffer->video.feedback_query_va;
1694
1695 // before encode
1696 // session info
1697 radv_enc_session_info(cmd_buffer);
1698
1699 cmd_buffer->video.enc.total_task_size = 0;
1700
1701 // task info
1702 radv_enc_task_info(cmd_buffer, true);
1703
1704 if (vid->enc_need_begin) {
1705 begin(cmd_buffer, enc_info);
1706 vid->enc_need_begin = false;
1707 } else {
1708 // temporal layers init
1709 unsigned i = 0;
1710 do {
1711 if (vid->enc_need_rate_control) {
1712 radv_enc_layer_select(cmd_buffer, i);
1713 radv_enc_rc_layer_init(cmd_buffer, &vid->rc_layer_init[i]);
1714 vid->enc_need_rate_control = false;
1715 }
1716 radv_enc_layer_select(cmd_buffer, i);
1717 radv_enc_rc_per_pic(cmd_buffer, enc_info, &vid->rc_per_pic[i]);
1718 } while (++i < vid->rc_layer_control.num_temporal_layers);
1719 }
1720
1721 // encode headers
1722 // ctx
1723 if (vid->vk.op == VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR) {
1724 radv_enc_headers_h264(cmd_buffer, enc_info);
1725 radv_enc_ctx(cmd_buffer, enc_info);
1726 } else if (vid->vk.op == VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR) {
1727 radv_enc_headers_hevc(cmd_buffer, enc_info);
1728 radv_enc_ctx(cmd_buffer, enc_info);
1729 }
1730 // bitstream
1731 radv_enc_bitstream(cmd_buffer, dst_buffer, enc_info->dstBufferOffset);
1732
1733 // feedback
1734 radv_enc_feedback(cmd_buffer, feedback_query_va);
1735
1736 // v2 encode statistics
1737 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_2) {
1738 }
1739 // intra_refresh
1740 radv_enc_intra_refresh(cmd_buffer);
1741 // v2 input format
1742 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_2) {
1743 radv_enc_input_format(cmd_buffer);
1744 radv_enc_output_format(cmd_buffer);
1745 }
1746 // v2 output format
1747
1748 // op_preset
1749 radv_enc_op_preset(cmd_buffer, enc_info);
1750 // op_enc
1751 radv_enc_op_enc(cmd_buffer);
1752
1753 radeon_emit_direct(cmd_buffer->cs, enc->task_size_offset, enc->total_task_size);
1754 }
1755
1756 static void
set_rate_control_defaults(struct radv_video_session * vid)1757 set_rate_control_defaults(struct radv_video_session *vid)
1758 {
1759 uint32_t frame_rate_den = 1, frame_rate_num = 30;
1760 vid->enc_rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
1761 vid->enc_vbv_buffer_level = 64;
1762 vid->rc_layer_control.num_temporal_layers = 1;
1763 vid->rc_layer_control.max_num_temporal_layers = 1;
1764 vid->rc_per_pic[0].qp_i = 26;
1765 vid->rc_per_pic[0].qp_p = 26;
1766 vid->rc_per_pic[0].qp_b = 26;
1767 vid->rc_per_pic[0].min_qp_i = 0;
1768 vid->rc_per_pic[0].max_qp_i = 51;
1769 vid->rc_per_pic[0].min_qp_p = 0;
1770 vid->rc_per_pic[0].max_qp_p = 51;
1771 vid->rc_per_pic[0].min_qp_b = 0;
1772 vid->rc_per_pic[0].max_qp_b = 51;
1773 vid->rc_per_pic[0].max_au_size_i = 0;
1774 vid->rc_per_pic[0].max_au_size_p = 0;
1775 vid->rc_per_pic[0].max_au_size_b = 0;
1776 vid->rc_per_pic[0].enabled_filler_data = 1;
1777 vid->rc_per_pic[0].skip_frame_enable = 0;
1778 vid->rc_per_pic[0].enforce_hrd = 1;
1779 vid->rc_layer_init[0].frame_rate_den = frame_rate_den;
1780 vid->rc_layer_init[0].frame_rate_num = frame_rate_num;
1781 vid->rc_layer_init[0].vbv_buffer_size = 20000000; // rate_control->virtualBufferSizeInMs;
1782 vid->rc_layer_init[0].target_bit_rate = 16000;
1783 vid->rc_layer_init[0].peak_bit_rate = 32000;
1784 vid->rc_layer_init[0].avg_target_bits_per_picture =
1785 radv_vcn_per_frame_integer(16000, frame_rate_den, frame_rate_num);
1786 vid->rc_layer_init[0].peak_bits_per_picture_integer =
1787 radv_vcn_per_frame_integer(32000, frame_rate_den, frame_rate_num);
1788 vid->rc_layer_init[0].peak_bits_per_picture_fractional =
1789 radv_vcn_per_frame_frac(32000, frame_rate_den, frame_rate_num);
1790 return;
1791 }
1792
1793 void
radv_video_enc_control_video_coding(struct radv_cmd_buffer * cmd_buffer,const VkVideoCodingControlInfoKHR * control_info)1794 radv_video_enc_control_video_coding(struct radv_cmd_buffer *cmd_buffer, const VkVideoCodingControlInfoKHR *control_info)
1795 {
1796 struct radv_video_session *vid = cmd_buffer->video.vid;
1797
1798 switch (vid->vk.op) {
1799 case VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR:
1800 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR:
1801 break;
1802 default:
1803 unreachable("Unsupported\n");
1804 }
1805
1806 if (control_info->flags & VK_VIDEO_CODING_CONTROL_RESET_BIT_KHR) {
1807 set_rate_control_defaults(vid);
1808 vid->enc_need_begin = true;
1809 }
1810
1811 if (control_info->flags & VK_VIDEO_CODING_CONTROL_ENCODE_RATE_CONTROL_BIT_KHR) {
1812 const VkVideoEncodeRateControlInfoKHR *rate_control = (VkVideoEncodeRateControlInfoKHR *)vk_find_struct_const(
1813 control_info->pNext, VIDEO_ENCODE_RATE_CONTROL_INFO_KHR);
1814
1815 assert(rate_control);
1816 const VkVideoEncodeH264RateControlInfoKHR *h264_rate_control =
1817 (VkVideoEncodeH264RateControlInfoKHR *)vk_find_struct_const(rate_control->pNext,
1818 VIDEO_ENCODE_H264_RATE_CONTROL_INFO_KHR);
1819 const VkVideoEncodeH265RateControlInfoKHR *h265_rate_control =
1820 (VkVideoEncodeH265RateControlInfoKHR *)vk_find_struct_const(rate_control->pNext,
1821 VIDEO_ENCODE_H265_RATE_CONTROL_INFO_KHR);
1822
1823 uint32_t rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
1824
1825 vid->enc_rate_control_default = false;
1826
1827 if (rate_control->rateControlMode == VK_VIDEO_ENCODE_RATE_CONTROL_MODE_DEFAULT_KHR) {
1828 vid->enc_rate_control_default = true;
1829 set_rate_control_defaults(vid);
1830 } else if (rate_control->rateControlMode == VK_VIDEO_ENCODE_RATE_CONTROL_MODE_CBR_BIT_KHR)
1831 rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
1832 else if (rate_control->rateControlMode == VK_VIDEO_ENCODE_RATE_CONTROL_MODE_VBR_BIT_KHR)
1833 rate_control_method = RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
1834
1835 vid->enc_need_rate_control = true;
1836 if (vid->enc_rate_control_method != rate_control_method)
1837 vid->enc_need_begin = true;
1838
1839 vid->enc_rate_control_method = rate_control_method;
1840
1841 if (rate_control->rateControlMode == VK_VIDEO_ENCODE_RATE_CONTROL_MODE_DEFAULT_KHR)
1842 return;
1843
1844 if (h264_rate_control) {
1845 vid->rc_layer_control.max_num_temporal_layers = h264_rate_control->temporalLayerCount;
1846 vid->rc_layer_control.num_temporal_layers = h264_rate_control->temporalLayerCount;
1847 } else if (h265_rate_control) {
1848 vid->rc_layer_control.max_num_temporal_layers = h265_rate_control->subLayerCount;
1849 vid->rc_layer_control.num_temporal_layers = h265_rate_control->subLayerCount;
1850 }
1851
1852 for (unsigned l = 0; l < rate_control->layerCount; l++) {
1853 const VkVideoEncodeRateControlLayerInfoKHR *layer = &rate_control->pLayers[l];
1854 const VkVideoEncodeH264RateControlLayerInfoKHR *h264_layer =
1855 (VkVideoEncodeH264RateControlLayerInfoKHR *)vk_find_struct_const(
1856 layer->pNext, VIDEO_ENCODE_H264_RATE_CONTROL_LAYER_INFO_KHR);
1857 const VkVideoEncodeH265RateControlLayerInfoKHR *h265_layer =
1858 (VkVideoEncodeH265RateControlLayerInfoKHR *)vk_find_struct_const(
1859 layer->pNext, VIDEO_ENCODE_H265_RATE_CONTROL_LAYER_INFO_KHR);
1860 uint32_t frame_rate_den, frame_rate_num;
1861 vid->rc_layer_init[l].target_bit_rate = layer->averageBitrate;
1862 vid->rc_layer_init[l].peak_bit_rate = layer->maxBitrate;
1863 frame_rate_den = layer->frameRateDenominator;
1864 frame_rate_num = layer->frameRateNumerator;
1865 radv_vcn_enc_invalid_frame_rate(&frame_rate_den, &frame_rate_num);
1866 vid->rc_layer_init[l].frame_rate_den = frame_rate_den;
1867 vid->rc_layer_init[l].frame_rate_num = frame_rate_num;
1868 vid->rc_layer_init[l].vbv_buffer_size =
1869 (rate_control->virtualBufferSizeInMs / 1000.) * layer->averageBitrate;
1870 vid->rc_layer_init[l].avg_target_bits_per_picture =
1871 radv_vcn_per_frame_integer(layer->averageBitrate, frame_rate_den, frame_rate_num);
1872 vid->rc_layer_init[l].peak_bits_per_picture_integer =
1873 radv_vcn_per_frame_integer(layer->maxBitrate, frame_rate_den, frame_rate_num);
1874 vid->rc_layer_init[l].peak_bits_per_picture_fractional =
1875 radv_vcn_per_frame_frac(layer->maxBitrate, frame_rate_den, frame_rate_num);
1876
1877 if (h264_layer) {
1878 vid->rc_per_pic[l].min_qp_i = h264_layer->useMinQp ? h264_layer->minQp.qpI : 0;
1879 vid->rc_per_pic[l].min_qp_p = h264_layer->useMinQp ? h264_layer->minQp.qpP : 0;
1880 vid->rc_per_pic[l].min_qp_b = h264_layer->useMinQp ? h264_layer->minQp.qpB : 0;
1881 vid->rc_per_pic[l].max_qp_i = h264_layer->useMaxQp ? h264_layer->maxQp.qpI : 51;
1882 vid->rc_per_pic[l].max_qp_p = h264_layer->useMaxQp ? h264_layer->maxQp.qpP : 51;
1883 vid->rc_per_pic[l].max_qp_b = h264_layer->useMaxQp ? h264_layer->maxQp.qpB : 51;
1884 vid->rc_per_pic[l].max_au_size_i = h264_layer->useMaxFrameSize ? h264_layer->maxFrameSize.frameISize : 0;
1885 vid->rc_per_pic[l].max_au_size_p = h264_layer->useMaxFrameSize ? h264_layer->maxFrameSize.framePSize : 0;
1886 vid->rc_per_pic[l].max_au_size_b = h264_layer->useMaxFrameSize ? h264_layer->maxFrameSize.frameBSize : 0;
1887 } else if (h265_layer) {
1888 vid->rc_per_pic[l].min_qp_i = h265_layer->useMinQp ? h265_layer->minQp.qpI : 0;
1889 vid->rc_per_pic[l].min_qp_p = h265_layer->useMinQp ? h265_layer->minQp.qpP : 0;
1890 vid->rc_per_pic[l].min_qp_b = h265_layer->useMinQp ? h265_layer->minQp.qpB : 0;
1891 vid->rc_per_pic[l].max_qp_i = h265_layer->useMaxQp ? h265_layer->maxQp.qpI : 51;
1892 vid->rc_per_pic[l].max_qp_p = h265_layer->useMaxQp ? h265_layer->maxQp.qpP : 51;
1893 vid->rc_per_pic[l].max_qp_b = h265_layer->useMaxQp ? h265_layer->maxQp.qpB : 51;
1894 vid->rc_per_pic[l].max_au_size_i = h265_layer->useMaxFrameSize ? h265_layer->maxFrameSize.frameISize : 0;
1895 vid->rc_per_pic[l].max_au_size_p = h265_layer->useMaxFrameSize ? h265_layer->maxFrameSize.framePSize : 0;
1896 vid->rc_per_pic[l].max_au_size_b = h265_layer->useMaxFrameSize ? h265_layer->maxFrameSize.frameBSize : 0;
1897 }
1898
1899 vid->rc_per_pic[l].enabled_filler_data = 1;
1900 vid->rc_per_pic[l].skip_frame_enable = 0;
1901 vid->rc_per_pic[l].enforce_hrd = 1;
1902 }
1903
1904 if (rate_control->virtualBufferSizeInMs > 0)
1905 vid->enc_vbv_buffer_level =
1906 lroundf((float)rate_control->initialVirtualBufferSizeInMs / rate_control->virtualBufferSizeInMs * 64);
1907 }
1908 }
1909
1910 VKAPI_ATTR void VKAPI_CALL
radv_CmdEncodeVideoKHR(VkCommandBuffer commandBuffer,const VkVideoEncodeInfoKHR * pEncodeInfo)1911 radv_CmdEncodeVideoKHR(VkCommandBuffer commandBuffer, const VkVideoEncodeInfoKHR *pEncodeInfo)
1912 {
1913 VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1914 radv_vcn_encode_video(cmd_buffer, pEncodeInfo);
1915 }
1916
1917 VKAPI_ATTR VkResult VKAPI_CALL
radv_GetPhysicalDeviceVideoEncodeQualityLevelPropertiesKHR(VkPhysicalDevice physicalDevice,const VkPhysicalDeviceVideoEncodeQualityLevelInfoKHR * pQualityLevelInfo,VkVideoEncodeQualityLevelPropertiesKHR * pQualityLevelProperties)1918 radv_GetPhysicalDeviceVideoEncodeQualityLevelPropertiesKHR(
1919 VkPhysicalDevice physicalDevice, const VkPhysicalDeviceVideoEncodeQualityLevelInfoKHR *pQualityLevelInfo,
1920 VkVideoEncodeQualityLevelPropertiesKHR *pQualityLevelProperties)
1921 {
1922 return VK_SUCCESS;
1923 }
1924
1925 void
radv_video_patch_encode_session_parameters(struct vk_video_session_parameters * params)1926 radv_video_patch_encode_session_parameters(struct vk_video_session_parameters *params)
1927 {
1928 switch (params->op) {
1929 case VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR:
1930 for (unsigned i = 0; i < params->h264_enc.h264_pps_count; i++) {
1931 params->h264_enc.h264_pps[i].base.pic_init_qp_minus26 = 0;
1932 }
1933 break;
1934 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR: {
1935 /*
1936 * AMD firmware requires these flags to be set in h265 with RC modes,
1937 * VCN 3 need 1.27 and VCN 4 needs 1.7 or newer to pass the CTS tests,
1938 * dEQP-VK.video.encode.h265_rc_*.
1939 */
1940 for (unsigned i = 0; i < params->h265_enc.h265_pps_count; i++) {
1941 params->h265_enc.h265_pps[i].base.flags.cu_qp_delta_enabled_flag = 1;
1942 params->h265_enc.h265_pps[i].base.diff_cu_qp_delta_depth = 0;
1943 params->h265_enc.h265_pps[i].base.init_qp_minus26 = 0;
1944 }
1945 break;
1946 }
1947 default:
1948 break;
1949 }
1950 }
1951
1952 VKAPI_ATTR VkResult VKAPI_CALL
radv_GetEncodedVideoSessionParametersKHR(VkDevice device,const VkVideoEncodeSessionParametersGetInfoKHR * pVideoSessionParametersInfo,VkVideoEncodeSessionParametersFeedbackInfoKHR * pFeedbackInfo,size_t * pDataSize,void * pData)1953 radv_GetEncodedVideoSessionParametersKHR(VkDevice device,
1954 const VkVideoEncodeSessionParametersGetInfoKHR *pVideoSessionParametersInfo,
1955 VkVideoEncodeSessionParametersFeedbackInfoKHR *pFeedbackInfo,
1956 size_t *pDataSize, void *pData)
1957 {
1958 VK_FROM_HANDLE(radv_video_session_params, templ, pVideoSessionParametersInfo->videoSessionParameters);
1959 size_t total_size = 0;
1960 size_t size_limit = 0;
1961
1962 if (pData)
1963 size_limit = *pDataSize;
1964
1965 switch (templ->vk.op) {
1966 case VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR: {
1967 const struct VkVideoEncodeH264SessionParametersGetInfoKHR *h264_get_info =
1968 vk_find_struct_const(pVideoSessionParametersInfo->pNext, VIDEO_ENCODE_H264_SESSION_PARAMETERS_GET_INFO_KHR);
1969 size_t sps_size = 0, pps_size = 0;
1970 if (h264_get_info->writeStdSPS) {
1971 const StdVideoH264SequenceParameterSet *sps =
1972 vk_video_find_h264_enc_std_sps(&templ->vk, h264_get_info->stdSPSId);
1973 assert(sps);
1974 vk_video_encode_h264_sps(sps, size_limit, &sps_size, pData);
1975 }
1976 if (h264_get_info->writeStdPPS) {
1977 const StdVideoH264PictureParameterSet *pps =
1978 vk_video_find_h264_enc_std_pps(&templ->vk, h264_get_info->stdPPSId);
1979 assert(pps);
1980 char *data_ptr = pData ? (char *)pData + sps_size : NULL;
1981 vk_video_encode_h264_pps(pps, templ->vk.h264_enc.profile_idc == STD_VIDEO_H264_PROFILE_IDC_HIGH, size_limit,
1982 &pps_size, data_ptr);
1983 if (pFeedbackInfo) {
1984 struct VkVideoEncodeH264SessionParametersFeedbackInfoKHR *h264_feedback_info =
1985 vk_find_struct(pFeedbackInfo->pNext, VIDEO_ENCODE_H264_SESSION_PARAMETERS_FEEDBACK_INFO_KHR);
1986 pFeedbackInfo->hasOverrides = VK_TRUE;
1987 if (h264_feedback_info)
1988 h264_feedback_info->hasStdPPSOverrides = VK_TRUE;
1989 }
1990 }
1991 total_size = sps_size + pps_size;
1992 break;
1993 }
1994 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR: {
1995 const struct VkVideoEncodeH265SessionParametersGetInfoKHR *h265_get_info =
1996 vk_find_struct_const(pVideoSessionParametersInfo->pNext, VIDEO_ENCODE_H265_SESSION_PARAMETERS_GET_INFO_KHR);
1997 size_t sps_size = 0, pps_size = 0, vps_size = 0;
1998 if (h265_get_info->writeStdVPS) {
1999 const StdVideoH265VideoParameterSet *vps = vk_video_find_h265_enc_std_vps(&templ->vk, h265_get_info->stdVPSId);
2000 assert(vps);
2001 vk_video_encode_h265_vps(vps, size_limit, &vps_size, pData);
2002 }
2003 if (h265_get_info->writeStdSPS) {
2004 const StdVideoH265SequenceParameterSet *sps =
2005 vk_video_find_h265_enc_std_sps(&templ->vk, h265_get_info->stdSPSId);
2006 assert(sps);
2007 char *data_ptr = pData ? (char *)pData + vps_size : NULL;
2008 vk_video_encode_h265_sps(sps, size_limit, &sps_size, data_ptr);
2009 }
2010 if (h265_get_info->writeStdPPS) {
2011 const StdVideoH265PictureParameterSet *pps =
2012 vk_video_find_h265_enc_std_pps(&templ->vk, h265_get_info->stdPPSId);
2013 assert(pps);
2014 char *data_ptr = pData ? (char *)pData + vps_size + sps_size : NULL;
2015 vk_video_encode_h265_pps(pps, size_limit, &pps_size, data_ptr);
2016
2017 if (pFeedbackInfo) {
2018 struct VkVideoEncodeH265SessionParametersFeedbackInfoKHR *h265_feedback_info =
2019 vk_find_struct(pFeedbackInfo->pNext, VIDEO_ENCODE_H265_SESSION_PARAMETERS_FEEDBACK_INFO_KHR);
2020 pFeedbackInfo->hasOverrides = VK_TRUE;
2021 if (h265_feedback_info)
2022 h265_feedback_info->hasStdPPSOverrides = VK_TRUE;
2023 }
2024 }
2025 total_size = sps_size + pps_size + vps_size;
2026 break;
2027 }
2028 default:
2029 break;
2030 }
2031
2032 *pDataSize = total_size;
2033 return VK_SUCCESS;
2034 }
2035
2036 void
radv_video_enc_begin_coding(struct radv_cmd_buffer * cmd_buffer)2037 radv_video_enc_begin_coding(struct radv_cmd_buffer *cmd_buffer)
2038 {
2039 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
2040 const struct radv_physical_device *pdev = radv_device_physical(device);
2041 radeon_check_space(device->ws, cmd_buffer->cs, 1024);
2042
2043 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4)
2044 radv_vcn_sq_header(cmd_buffer->cs, &cmd_buffer->video.sq, RADEON_VCN_ENGINE_TYPE_ENCODE, false);
2045 }
2046
2047 void
radv_video_enc_end_coding(struct radv_cmd_buffer * cmd_buffer)2048 radv_video_enc_end_coding(struct radv_cmd_buffer *cmd_buffer)
2049 {
2050 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
2051 const struct radv_physical_device *pdev = radv_device_physical(device);
2052 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4)
2053 radv_vcn_sq_tail(cmd_buffer->cs, &cmd_buffer->video.sq);
2054 }
2055
2056 #define VCN_ENC_SESSION_SIZE 128 * 1024
2057
2058 VkResult
radv_video_get_encode_session_memory_requirements(struct radv_device * device,struct radv_video_session * vid,uint32_t * pMemoryRequirementsCount,VkVideoSessionMemoryRequirementsKHR * pMemoryRequirements)2059 radv_video_get_encode_session_memory_requirements(struct radv_device *device, struct radv_video_session *vid,
2060 uint32_t *pMemoryRequirementsCount,
2061 VkVideoSessionMemoryRequirementsKHR *pMemoryRequirements)
2062 {
2063 struct radv_physical_device *pdev = radv_device_physical(device);
2064 uint32_t memory_type_bits = (1u << pdev->memory_properties.memoryTypeCount) - 1;
2065
2066 VK_OUTARRAY_MAKE_TYPED(VkVideoSessionMemoryRequirementsKHR, out, pMemoryRequirements, pMemoryRequirementsCount);
2067
2068 vk_outarray_append_typed(VkVideoSessionMemoryRequirementsKHR, &out, m)
2069 {
2070 m->memoryBindIndex = 0;
2071 m->memoryRequirements.size = VCN_ENC_SESSION_SIZE;
2072 m->memoryRequirements.alignment = 0;
2073 m->memoryRequirements.memoryTypeBits = memory_type_bits;
2074 }
2075
2076 return vk_outarray_status(&out);
2077 }
2078