1 /*
2 * Copyright © 2016 Red Hat
3 * based on intel anv code:
4 * Copyright © 2015 Intel Corporation
5 *
6 * SPDX-License-Identifier: MIT
7 */
8
9 #include "radv_meta.h"
10 #include "radv_printf.h"
11
12 #include "vk_common_entrypoints.h"
13 #include "vk_pipeline_cache.h"
14 #include "vk_util.h"
15
16 #include <fcntl.h>
17 #include <limits.h>
18 #ifndef _WIN32
19 #include <pwd.h>
20 #endif
21 #include <sys/stat.h>
22
23 static void
radv_suspend_queries(struct radv_meta_saved_state * state,struct radv_cmd_buffer * cmd_buffer)24 radv_suspend_queries(struct radv_meta_saved_state *state, struct radv_cmd_buffer *cmd_buffer)
25 {
26 const uint32_t num_pipeline_stat_queries = radv_get_num_pipeline_stat_queries(cmd_buffer);
27
28 if (num_pipeline_stat_queries > 0) {
29 cmd_buffer->state.flush_bits &= ~RADV_CMD_FLAG_START_PIPELINE_STATS;
30 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_STOP_PIPELINE_STATS;
31 }
32
33 /* Pipeline statistics queries. */
34 if (cmd_buffer->state.active_pipeline_queries > 0) {
35 state->active_emulated_pipeline_queries = cmd_buffer->state.active_emulated_pipeline_queries;
36 cmd_buffer->state.active_emulated_pipeline_queries = 0;
37 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_SHADER_QUERY;
38 }
39
40 /* Occlusion queries. */
41 if (cmd_buffer->state.active_occlusion_queries) {
42 state->active_occlusion_queries = cmd_buffer->state.active_occlusion_queries;
43 cmd_buffer->state.active_occlusion_queries = 0;
44 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_OCCLUSION_QUERY;
45 }
46
47 /* Primitives generated queries (legacy). */
48 if (cmd_buffer->state.active_prims_gen_queries) {
49 cmd_buffer->state.suspend_streamout = true;
50 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_ENABLE;
51 }
52
53 /* Primitives generated queries (NGG). */
54 if (cmd_buffer->state.active_emulated_prims_gen_queries) {
55 state->active_emulated_prims_gen_queries = cmd_buffer->state.active_emulated_prims_gen_queries;
56 cmd_buffer->state.active_emulated_prims_gen_queries = 0;
57 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_SHADER_QUERY;
58 }
59
60 /* Transform feedback queries (NGG). */
61 if (cmd_buffer->state.active_emulated_prims_xfb_queries) {
62 state->active_emulated_prims_xfb_queries = cmd_buffer->state.active_emulated_prims_xfb_queries;
63 cmd_buffer->state.active_emulated_prims_xfb_queries = 0;
64 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_SHADER_QUERY;
65 }
66 }
67
68 static void
radv_resume_queries(const struct radv_meta_saved_state * state,struct radv_cmd_buffer * cmd_buffer)69 radv_resume_queries(const struct radv_meta_saved_state *state, struct radv_cmd_buffer *cmd_buffer)
70 {
71 const uint32_t num_pipeline_stat_queries = radv_get_num_pipeline_stat_queries(cmd_buffer);
72
73 if (num_pipeline_stat_queries > 0) {
74 cmd_buffer->state.flush_bits &= ~RADV_CMD_FLAG_STOP_PIPELINE_STATS;
75 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_START_PIPELINE_STATS;
76 }
77
78 /* Pipeline statistics queries. */
79 if (cmd_buffer->state.active_pipeline_queries > 0) {
80 cmd_buffer->state.active_emulated_pipeline_queries = state->active_emulated_pipeline_queries;
81 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_SHADER_QUERY;
82 }
83
84 /* Occlusion queries. */
85 if (state->active_occlusion_queries) {
86 cmd_buffer->state.active_occlusion_queries = state->active_occlusion_queries;
87 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_OCCLUSION_QUERY;
88 }
89
90 /* Primitives generated queries (legacy). */
91 if (cmd_buffer->state.active_prims_gen_queries) {
92 cmd_buffer->state.suspend_streamout = false;
93 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_ENABLE;
94 }
95
96 /* Primitives generated queries (NGG). */
97 if (state->active_emulated_prims_gen_queries) {
98 cmd_buffer->state.active_emulated_prims_gen_queries = state->active_emulated_prims_gen_queries;
99 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_SHADER_QUERY;
100 }
101
102 /* Transform feedback queries (NGG). */
103 if (state->active_emulated_prims_xfb_queries) {
104 cmd_buffer->state.active_emulated_prims_xfb_queries = state->active_emulated_prims_xfb_queries;
105 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_SHADER_QUERY;
106 }
107 }
108
109 void
radv_meta_save(struct radv_meta_saved_state * state,struct radv_cmd_buffer * cmd_buffer,uint32_t flags)110 radv_meta_save(struct radv_meta_saved_state *state, struct radv_cmd_buffer *cmd_buffer, uint32_t flags)
111 {
112 VkPipelineBindPoint bind_point =
113 flags & RADV_META_SAVE_GRAPHICS_PIPELINE ? VK_PIPELINE_BIND_POINT_GRAPHICS : VK_PIPELINE_BIND_POINT_COMPUTE;
114 struct radv_descriptor_state *descriptors_state = radv_get_descriptors_state(cmd_buffer, bind_point);
115
116 assert(flags & (RADV_META_SAVE_GRAPHICS_PIPELINE | RADV_META_SAVE_COMPUTE_PIPELINE));
117
118 state->flags = flags;
119 state->active_occlusion_queries = 0;
120 state->active_emulated_prims_gen_queries = 0;
121 state->active_emulated_prims_xfb_queries = 0;
122
123 if (state->flags & RADV_META_SAVE_GRAPHICS_PIPELINE) {
124 assert(!(state->flags & RADV_META_SAVE_COMPUTE_PIPELINE));
125
126 state->old_graphics_pipeline = cmd_buffer->state.graphics_pipeline;
127
128 /* Save all dynamic states. */
129 state->dynamic = cmd_buffer->state.dynamic;
130 }
131
132 if (state->flags & RADV_META_SAVE_COMPUTE_PIPELINE) {
133 assert(!(state->flags & RADV_META_SAVE_GRAPHICS_PIPELINE));
134
135 state->old_compute_pipeline = cmd_buffer->state.compute_pipeline;
136 }
137
138 for (unsigned i = 0; i <= MESA_SHADER_MESH; i++) {
139 state->old_shader_objs[i] = cmd_buffer->state.shader_objs[i];
140 }
141
142 if (state->flags & RADV_META_SAVE_DESCRIPTORS) {
143 state->old_descriptor_set0 = descriptors_state->sets[0];
144 if (!(descriptors_state->valid & 1))
145 state->flags &= ~RADV_META_SAVE_DESCRIPTORS;
146 }
147
148 if (state->flags & RADV_META_SAVE_CONSTANTS) {
149 memcpy(state->push_constants, cmd_buffer->push_constants, MAX_PUSH_CONSTANTS_SIZE);
150 }
151
152 if (state->flags & RADV_META_SAVE_RENDER) {
153 state->render = cmd_buffer->state.render;
154 radv_cmd_buffer_reset_rendering(cmd_buffer);
155 }
156
157 if (state->flags & RADV_META_SUSPEND_PREDICATING) {
158 state->predicating = cmd_buffer->state.predicating;
159 cmd_buffer->state.predicating = false;
160 }
161
162 radv_suspend_queries(state, cmd_buffer);
163 }
164
165 void
radv_meta_restore(const struct radv_meta_saved_state * state,struct radv_cmd_buffer * cmd_buffer)166 radv_meta_restore(const struct radv_meta_saved_state *state, struct radv_cmd_buffer *cmd_buffer)
167 {
168 VkPipelineBindPoint bind_point = state->flags & RADV_META_SAVE_GRAPHICS_PIPELINE ? VK_PIPELINE_BIND_POINT_GRAPHICS
169 : VK_PIPELINE_BIND_POINT_COMPUTE;
170
171 if (state->flags & RADV_META_SAVE_GRAPHICS_PIPELINE) {
172 if (state->old_graphics_pipeline) {
173 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_GRAPHICS,
174 radv_pipeline_to_handle(&state->old_graphics_pipeline->base));
175 }
176
177 /* Restore all dynamic states. */
178 cmd_buffer->state.dynamic = state->dynamic;
179 cmd_buffer->state.dirty_dynamic |= RADV_DYNAMIC_ALL;
180
181 /* Re-emit the guardband state because meta operations changed dynamic states. */
182 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_GUARDBAND;
183 }
184
185 if (state->flags & RADV_META_SAVE_COMPUTE_PIPELINE) {
186 if (state->old_compute_pipeline) {
187 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
188 radv_pipeline_to_handle(&state->old_compute_pipeline->base));
189 }
190 }
191
192 VkShaderEXT shaders[MESA_SHADER_MESH + 1];
193 VkShaderStageFlagBits stages[MESA_SHADER_MESH + 1];
194 uint32_t stage_count = 0;
195
196 for (unsigned i = 0; i <= MESA_SHADER_MESH; i++) {
197 if (state->old_shader_objs[i]) {
198 stages[stage_count] = mesa_to_vk_shader_stage(i);
199 shaders[stage_count] = radv_shader_object_to_handle(state->old_shader_objs[i]);
200 stage_count++;
201 }
202 }
203
204 if (stage_count > 0) {
205 radv_CmdBindShadersEXT(radv_cmd_buffer_to_handle(cmd_buffer), stage_count, stages, shaders);
206 }
207
208 if (state->flags & RADV_META_SAVE_DESCRIPTORS) {
209 radv_set_descriptor_set(cmd_buffer, bind_point, state->old_descriptor_set0, 0);
210 }
211
212 if (state->flags & RADV_META_SAVE_CONSTANTS) {
213 VkShaderStageFlags stage_flags = VK_SHADER_STAGE_COMPUTE_BIT;
214
215 if (state->flags & RADV_META_SAVE_GRAPHICS_PIPELINE)
216 stage_flags |= VK_SHADER_STAGE_ALL_GRAPHICS;
217
218 vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), VK_NULL_HANDLE, stage_flags, 0,
219 MAX_PUSH_CONSTANTS_SIZE, state->push_constants);
220 }
221
222 if (state->flags & RADV_META_SAVE_RENDER) {
223 cmd_buffer->state.render = state->render;
224 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
225 }
226
227 if (state->flags & RADV_META_SUSPEND_PREDICATING)
228 cmd_buffer->state.predicating = state->predicating;
229
230 radv_resume_queries(state, cmd_buffer);
231 }
232
233 VkImageViewType
radv_meta_get_view_type(const struct radv_image * image)234 radv_meta_get_view_type(const struct radv_image *image)
235 {
236 switch (image->vk.image_type) {
237 case VK_IMAGE_TYPE_1D:
238 return VK_IMAGE_VIEW_TYPE_1D;
239 case VK_IMAGE_TYPE_2D:
240 return VK_IMAGE_VIEW_TYPE_2D;
241 case VK_IMAGE_TYPE_3D:
242 return VK_IMAGE_VIEW_TYPE_3D;
243 default:
244 unreachable("bad VkImageViewType");
245 }
246 }
247
248 /**
249 * When creating a destination VkImageView, this function provides the needed
250 * VkImageViewCreateInfo::subresourceRange::baseArrayLayer.
251 */
252 uint32_t
radv_meta_get_iview_layer(const struct radv_image * dst_image,const VkImageSubresourceLayers * dst_subresource,const VkOffset3D * dst_offset)253 radv_meta_get_iview_layer(const struct radv_image *dst_image, const VkImageSubresourceLayers *dst_subresource,
254 const VkOffset3D *dst_offset)
255 {
256 switch (dst_image->vk.image_type) {
257 case VK_IMAGE_TYPE_1D:
258 case VK_IMAGE_TYPE_2D:
259 return dst_subresource->baseArrayLayer;
260 case VK_IMAGE_TYPE_3D:
261 /* HACK: Vulkan does not allow attaching a 3D image to a framebuffer,
262 * but meta does it anyway. When doing so, we translate the
263 * destination's z offset into an array offset.
264 */
265 return dst_offset->z;
266 default:
267 assert(!"bad VkImageType");
268 return 0;
269 }
270 }
271
272 static VKAPI_ATTR void *VKAPI_CALL
meta_alloc(void * _device,size_t size,size_t alignment,VkSystemAllocationScope allocationScope)273 meta_alloc(void *_device, size_t size, size_t alignment, VkSystemAllocationScope allocationScope)
274 {
275 struct radv_device *device = _device;
276 return device->vk.alloc.pfnAllocation(device->vk.alloc.pUserData, size, alignment,
277 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
278 }
279
280 static VKAPI_ATTR void *VKAPI_CALL
meta_realloc(void * _device,void * original,size_t size,size_t alignment,VkSystemAllocationScope allocationScope)281 meta_realloc(void *_device, void *original, size_t size, size_t alignment, VkSystemAllocationScope allocationScope)
282 {
283 struct radv_device *device = _device;
284 return device->vk.alloc.pfnReallocation(device->vk.alloc.pUserData, original, size, alignment,
285 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
286 }
287
288 static VKAPI_ATTR void VKAPI_CALL
meta_free(void * _device,void * data)289 meta_free(void *_device, void *data)
290 {
291 struct radv_device *device = _device;
292 device->vk.alloc.pfnFree(device->vk.alloc.pUserData, data);
293 }
294
295 #ifndef _WIN32
296 static bool
radv_builtin_cache_path(char * path)297 radv_builtin_cache_path(char *path)
298 {
299 char *xdg_cache_home = secure_getenv("XDG_CACHE_HOME");
300 const char *suffix = "/radv_builtin_shaders";
301 const char *suffix2 = "/.cache/radv_builtin_shaders";
302 struct passwd pwd, *result;
303 char path2[PATH_MAX + 1]; /* PATH_MAX is not a real max,but suffices here. */
304 int ret;
305
306 if (xdg_cache_home) {
307 ret = snprintf(path, PATH_MAX + 1, "%s%s%zd", xdg_cache_home, suffix, sizeof(void *) * 8);
308 return ret > 0 && ret < PATH_MAX + 1;
309 }
310
311 getpwuid_r(getuid(), &pwd, path2, PATH_MAX - strlen(suffix2), &result);
312 if (!result)
313 return false;
314
315 strcpy(path, pwd.pw_dir);
316 strcat(path, "/.cache");
317 if (mkdir(path, 0755) && errno != EEXIST)
318 return false;
319
320 ret = snprintf(path, PATH_MAX + 1, "%s%s%zd", pwd.pw_dir, suffix2, sizeof(void *) * 8);
321 return ret > 0 && ret < PATH_MAX + 1;
322 }
323 #endif
324
325 static uint32_t
num_cache_entries(VkPipelineCache cache)326 num_cache_entries(VkPipelineCache cache)
327 {
328 struct set *s = vk_pipeline_cache_from_handle(cache)->object_cache;
329 if (!s)
330 return 0;
331 return s->entries;
332 }
333
334 static void
radv_load_meta_pipeline(struct radv_device * device)335 radv_load_meta_pipeline(struct radv_device *device)
336 {
337 #ifndef _WIN32
338 char path[PATH_MAX + 1];
339 struct stat st;
340 void *data = NULL;
341 int fd = -1;
342 struct vk_pipeline_cache *cache = NULL;
343
344 VkPipelineCacheCreateInfo create_info = {
345 .sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO,
346 };
347
348 struct vk_pipeline_cache_create_info info = {
349 .pCreateInfo = &create_info,
350 .skip_disk_cache = true,
351 };
352
353 if (!radv_builtin_cache_path(path))
354 goto fail;
355
356 fd = open(path, O_RDONLY);
357 if (fd < 0)
358 goto fail;
359 if (fstat(fd, &st))
360 goto fail;
361 data = malloc(st.st_size);
362 if (!data)
363 goto fail;
364 if (read(fd, data, st.st_size) == -1)
365 goto fail;
366
367 create_info.initialDataSize = st.st_size;
368 create_info.pInitialData = data;
369
370 fail:
371 cache = vk_pipeline_cache_create(&device->vk, &info, NULL);
372
373 if (cache) {
374 device->meta_state.cache = vk_pipeline_cache_to_handle(cache);
375 device->meta_state.initial_cache_entries = num_cache_entries(device->meta_state.cache);
376 }
377
378 free(data);
379 if (fd >= 0)
380 close(fd);
381 #endif
382 }
383
384 static void
radv_store_meta_pipeline(struct radv_device * device)385 radv_store_meta_pipeline(struct radv_device *device)
386 {
387 #ifndef _WIN32
388 char path[PATH_MAX + 1], path2[PATH_MAX + 7];
389 size_t size;
390 void *data = NULL;
391
392 if (device->meta_state.cache == VK_NULL_HANDLE)
393 return;
394
395 /* Skip serialization if no entries were added. */
396 if (num_cache_entries(device->meta_state.cache) <= device->meta_state.initial_cache_entries)
397 return;
398
399 if (vk_common_GetPipelineCacheData(radv_device_to_handle(device), device->meta_state.cache, &size, NULL))
400 return;
401
402 if (!radv_builtin_cache_path(path))
403 return;
404
405 strcpy(path2, path);
406 strcat(path2, "XXXXXX");
407 int fd = mkstemp(path2); // open(path, O_WRONLY | O_CREAT, 0600);
408 if (fd < 0)
409 return;
410 data = malloc(size);
411 if (!data)
412 goto fail;
413
414 if (vk_common_GetPipelineCacheData(radv_device_to_handle(device), device->meta_state.cache, &size, data))
415 goto fail;
416 if (write(fd, data, size) == -1)
417 goto fail;
418
419 rename(path2, path);
420 fail:
421 free(data);
422 close(fd);
423 unlink(path2);
424 #endif
425 }
426
427 VkResult
radv_device_init_meta(struct radv_device * device)428 radv_device_init_meta(struct radv_device *device)
429 {
430 const struct radv_physical_device *pdev = radv_device_physical(device);
431 VkResult result;
432
433 memset(&device->meta_state, 0, sizeof(device->meta_state));
434
435 device->meta_state.alloc = (VkAllocationCallbacks){
436 .pUserData = device,
437 .pfnAllocation = meta_alloc,
438 .pfnReallocation = meta_realloc,
439 .pfnFree = meta_free,
440 };
441
442 radv_load_meta_pipeline(device);
443
444 result = vk_meta_device_init(&device->vk, &device->meta_state.device);
445 if (result != VK_SUCCESS)
446 return result;
447
448 device->meta_state.device.pipeline_cache = device->meta_state.cache;
449
450 mtx_init(&device->meta_state.mtx, mtx_plain);
451
452 if (pdev->emulate_etc2) {
453 device->meta_state.etc_decode.allocator = &device->meta_state.alloc;
454 device->meta_state.etc_decode.nir_options = &pdev->nir_options[MESA_SHADER_COMPUTE];
455 device->meta_state.etc_decode.pipeline_cache = device->meta_state.cache;
456
457 vk_texcompress_etc2_init(&device->vk, &device->meta_state.etc_decode);
458 }
459
460 if (pdev->emulate_astc) {
461 result = vk_texcompress_astc_init(&device->vk, &device->meta_state.alloc, device->meta_state.cache,
462 &device->meta_state.astc_decode);
463 if (result != VK_SUCCESS)
464 return result;
465 }
466
467 if (device->vk.enabled_features.nullDescriptor) {
468 result = radv_device_init_null_accel_struct(device);
469 if (result != VK_SUCCESS)
470 return result;
471 }
472
473 return VK_SUCCESS;
474 }
475
476 void
radv_device_finish_meta(struct radv_device * device)477 radv_device_finish_meta(struct radv_device *device)
478 {
479 const struct radv_physical_device *pdev = radv_device_physical(device);
480
481 if (pdev->emulate_etc2)
482 vk_texcompress_etc2_finish(&device->vk, &device->meta_state.etc_decode);
483
484 if (pdev->emulate_astc) {
485 if (device->meta_state.astc_decode)
486 vk_texcompress_astc_finish(&device->vk, &device->meta_state.alloc, device->meta_state.astc_decode);
487 }
488
489 radv_device_finish_accel_struct_build_state(device);
490
491 radv_store_meta_pipeline(device);
492 vk_common_DestroyPipelineCache(radv_device_to_handle(device), device->meta_state.cache, NULL);
493 mtx_destroy(&device->meta_state.mtx);
494
495 if (device->meta_state.device.cache)
496 vk_meta_device_finish(&device->vk, &device->meta_state.device);
497 }
498
499 nir_builder PRINTFLIKE(3, 4)
radv_meta_init_shader(struct radv_device * dev,gl_shader_stage stage,const char * name,...)500 radv_meta_init_shader(struct radv_device *dev, gl_shader_stage stage, const char *name, ...)
501 {
502 const struct radv_physical_device *pdev = radv_device_physical(dev);
503 nir_builder b = nir_builder_init_simple_shader(stage, NULL, NULL);
504 if (name) {
505 va_list args;
506 va_start(args, name);
507 b.shader->info.name = ralloc_vasprintf(b.shader, name, args);
508 va_end(args);
509 }
510
511 b.shader->options = &pdev->nir_options[stage];
512
513 radv_device_associate_nir(dev, b.shader);
514
515 return b;
516 }
517
518 /* vertex shader that generates vertices */
519 nir_shader *
radv_meta_build_nir_vs_generate_vertices(struct radv_device * dev)520 radv_meta_build_nir_vs_generate_vertices(struct radv_device *dev)
521 {
522 const struct glsl_type *vec4 = glsl_vec4_type();
523
524 nir_variable *v_position;
525
526 nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_VERTEX, "meta_vs_gen_verts");
527
528 nir_def *outvec = nir_gen_rect_vertices(&b, NULL, NULL);
529
530 v_position = nir_variable_create(b.shader, nir_var_shader_out, vec4, "gl_Position");
531 v_position->data.location = VARYING_SLOT_POS;
532
533 nir_store_var(&b, v_position, outvec, 0xf);
534
535 return b.shader;
536 }
537
538 nir_shader *
radv_meta_build_nir_fs_noop(struct radv_device * dev)539 radv_meta_build_nir_fs_noop(struct radv_device *dev)
540 {
541 return radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_noop_fs").shader;
542 }
543
544 void
radv_meta_build_resolve_shader_core(struct radv_device * device,nir_builder * b,bool is_integer,int samples,nir_variable * input_img,nir_variable * color,nir_def * img_coord)545 radv_meta_build_resolve_shader_core(struct radv_device *device, nir_builder *b, bool is_integer, int samples,
546 nir_variable *input_img, nir_variable *color, nir_def *img_coord)
547 {
548 const struct radv_physical_device *pdev = radv_device_physical(device);
549 nir_deref_instr *input_img_deref = nir_build_deref_var(b, input_img);
550 nir_def *sample0 = nir_txf_ms_deref(b, input_img_deref, img_coord, nir_imm_int(b, 0));
551
552 if (is_integer || samples <= 1) {
553 nir_store_var(b, color, sample0, 0xf);
554 return;
555 }
556
557 if (pdev->use_fmask) {
558 nir_def *all_same = nir_samples_identical_deref(b, input_img_deref, img_coord);
559 nir_push_if(b, nir_inot(b, all_same));
560 }
561
562 nir_def *accum = sample0;
563 for (int i = 1; i < samples; i++) {
564 nir_def *sample = nir_txf_ms_deref(b, input_img_deref, img_coord, nir_imm_int(b, i));
565 accum = nir_fadd(b, accum, sample);
566 }
567
568 accum = nir_fdiv_imm(b, accum, samples);
569 nir_store_var(b, color, accum, 0xf);
570
571 if (pdev->use_fmask) {
572 nir_push_else(b, NULL);
573 nir_store_var(b, color, sample0, 0xf);
574 nir_pop_if(b, NULL);
575 }
576 }
577
578 nir_def *
radv_meta_load_descriptor(nir_builder * b,unsigned desc_set,unsigned binding)579 radv_meta_load_descriptor(nir_builder *b, unsigned desc_set, unsigned binding)
580 {
581 nir_def *rsrc = nir_vulkan_resource_index(b, 3, 32, nir_imm_int(b, 0), .desc_set = desc_set, .binding = binding);
582 return nir_trim_vector(b, rsrc, 2);
583 }
584
585 nir_def *
get_global_ids(nir_builder * b,unsigned num_components)586 get_global_ids(nir_builder *b, unsigned num_components)
587 {
588 unsigned mask = BITFIELD_MASK(num_components);
589
590 nir_def *local_ids = nir_channels(b, nir_load_local_invocation_id(b), mask);
591 nir_def *block_ids = nir_channels(b, nir_load_workgroup_id(b), mask);
592 nir_def *block_size =
593 nir_channels(b,
594 nir_imm_ivec4(b, b->shader->info.workgroup_size[0], b->shader->info.workgroup_size[1],
595 b->shader->info.workgroup_size[2], 0),
596 mask);
597
598 return nir_iadd(b, nir_imul(b, block_ids, block_size), local_ids);
599 }
600
601 void
radv_break_on_count(nir_builder * b,nir_variable * var,nir_def * count)602 radv_break_on_count(nir_builder *b, nir_variable *var, nir_def *count)
603 {
604 nir_def *counter = nir_load_var(b, var);
605
606 nir_break_if(b, nir_uge(b, counter, count));
607
608 counter = nir_iadd_imm(b, counter, 1);
609 nir_store_var(b, var, counter, 0x1);
610 }
611
612 VkResult
radv_meta_get_noop_pipeline_layout(struct radv_device * device,VkPipelineLayout * layout_out)613 radv_meta_get_noop_pipeline_layout(struct radv_device *device, VkPipelineLayout *layout_out)
614 {
615 const char *key_data = "radv-noop";
616
617 return vk_meta_get_pipeline_layout(&device->vk, &device->meta_state.device, NULL, NULL, key_data, strlen(key_data),
618 layout_out);
619 }
620