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Searched defs:reg3 (Results 1 – 25 of 31) sorted by relevance

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/external/vixl/src/aarch64/
Dregisters-aarch64.cc176 const CPURegister& reg3, in AreAliased()
227 const CPURegister& reg3, in AreSameSizeAndType()
247 const CPURegister& reg3, in AreEven()
267 const CPURegister& reg3, in AreConsecutive()
297 const CPURegister& reg3, in AreSameFormat()
309 const CPURegister& reg3, in AreSameLaneSize()
Dmacro-assembler-aarch64.cc3007 const Register& reg3, in Include()
3021 const VRegister& reg3, in Include()
3031 const CPURegister& reg3, in Include()
3071 const Register& reg3, in Exclude()
3081 const VRegister& reg3, in Exclude()
3091 const CPURegister& reg3, in Exclude()
/external/libvpx/vpx_ports/
Dasmdefs_mmi.h21 #define MMI_ADDU(reg1, reg2, reg3) \ argument
30 #define MMI_SUBU(reg1, reg2, reg3) \ argument
50 #define MMI_ADDU(reg1, reg2, reg3) \ argument
59 #define MMI_SUBU(reg1, reg2, reg3) \ argument
/external/libvpx/vp8/encoder/loongarch/
Dencodeopt_lsx.c18 __m128i reg0, reg1, reg2, reg3, error; in vp8_block_error_lsx() local
43 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, error; in vp8_mbblock_error_lsx() local
/external/libvpx/vpx_dsp/loongarch/
Didct32x32_lsx.c93 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
185 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_odd_process_store() local
319 __m128i reg0, reg1, reg2, reg3; in idct_butterfly_transpose_store() local
450 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_even_process_store() local
545 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_odd_process_store() local
Dsubtract_lsx.c51 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in sub_blk_8x8_lsx() local
102 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in sub_blk_16x16_lsx() local
214 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in sub_blk_32x32_lsx() local
281 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in sub_blk_64x64_lsx() local
Dvpx_convolve8_vert_lsx.c24 __m128i reg0, reg1, reg2, reg3, reg4; in common_vt_8t_4w_lsx() local
83 __m128i reg0, reg1, reg2, reg3, reg4, reg5; in common_vt_8t_8w_lsx() local
154 __m128i reg0, reg1, reg2, reg3, reg4, reg5; in common_vt_8t_16w_lsx() local
249 __m128i reg0, reg1, reg2, reg3, reg4, reg5; in common_vt_8t_16w_mult_lsx() local
Dvpx_convolve8_avg_vert_lsx.c24 __m128i reg0, reg1, reg2, reg3, reg4; in common_vt_8t_and_aver_dst_4w_lsx() local
102 __m128i reg0, reg1, reg2, reg3, reg4, reg5; in common_vt_8t_and_aver_dst_8w_lsx() local
185 __m128i reg0, reg1, reg2, reg3, reg4, reg5; in common_vt_8t_and_aver_dst_16w_mult_lsx() local
/external/libvpx/vpx_dsp/mips/
Didct32x32_msa.c45 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
129 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_odd_process_store() local
355 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_even_process_store() local
435 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_odd_process_store() local
Didct16x16_msa.c17 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_rows_msa() local
111 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_columns_addblk_msa() local
/external/libvpx/third_party/libyuv/source/
Dcompare_msa.cc59 v4i32 reg0 = {0}, reg1 = {0}, reg2 = {0}, reg3 = {0}; in SumSquareError_MSA() local
Drotate_msa.cc85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
Dscale_msa.cc78 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local
141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
304 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
669 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_MSA() local
766 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_0_Box_MSA() local
860 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_1_Box_MSA() local
Drow_msa.cc481 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local
774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
1089 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; in ARGBToUV444Row_MSA() local
1163 v4u32 reg0, reg1, reg2, reg3; in ARGBMultiplyRow_MSA() local
1243 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
1379 v4u32 reg0, reg1, reg2, reg3, rgba_scale; in ARGBShadeRow_MSA() local
1512 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6; in ARGB1555ToARGBRow_MSA() local
1561 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in RGB565ToARGBRow_MSA() local
1660 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGB1555ToYRow_MSA() local
[all …]
/external/libyuv/source/
Dcompare_msa.cc59 v4i32 reg0 = {0}, reg1 = {0}, reg2 = {0}, reg3 = {0}; in SumSquareError_MSA() local
Dscale_lsx.cc83 __m128i reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_LSX() local
279 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, dst0; in ScaleRowDown4Box_LSX() local
347 __m128i reg0, reg1, reg2, reg3; in ScaleRowDown38_2_Box_LSX() local
387 __m128i reg0, reg1, reg2, reg3, dst0; in ScaleRowDown38_3_Box_LSX() local
454 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleFilterCols_LSX() local
545 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_LSX() local
Drotate_msa.cc85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
Dscale_msa.cc78 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local
141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
304 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
669 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_MSA() local
766 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_0_Box_MSA() local
860 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_1_Box_MSA() local
Drotate_lsx.cc103 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_LSX() local
179 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_LSX() local
Drow_msa.cc515 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local
803 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
855 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
1125 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; in ARGBToUV444Row_MSA() local
1199 v4u32 reg0, reg1, reg2, reg3; in ARGBMultiplyRow_MSA() local
1279 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
1415 v4u32 reg0, reg1, reg2, reg3, rgba_scale; in ARGBShadeRow_MSA() local
1548 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6; in ARGB1555ToARGBRow_MSA() local
1597 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in RGB565ToARGBRow_MSA() local
1797 v16u8 src0, src1, src2, reg0, reg1, reg2, reg3, dst0; in RGB24ToYRow_MSA() local
[all …]
Drow_lasx.cc1034 __m256i reg0, reg1, reg2, reg3, dst0, dst1; in ARGBToUV444Row_LASX() local
1147 __m256i reg0, reg1, reg2, reg3, reg4, reg5; in ARGBAttenuateRow_LASX() local
1344 __m256i reg0, reg1, reg2, reg3; in ARGB4444ToARGBRow_LASX() local
1376 __m256i reg0, reg1, reg2, reg3; in ARGB1555ToARGBRow_LASX() local
1426 __m256i reg0, reg1, reg2, reg3, dst0, dst1, dst2, dst3; in RGB565ToARGBRow_LASX() local
1473 __m256i reg0, reg1, reg2, reg3; in RGB24ToARGBRow_LASX() local
1511 __m256i tmp0, tmp1, tmp2, reg0, reg1, reg2, reg3; in RAWToARGBRow_LASX() local
1606 __m256i reg0, reg1, reg2, reg3, dst0; in ARGB1555ToUVRow_LASX() local
1723 __m256i reg0, reg1, reg2, reg3, dst0; in RGB565ToUVRow_LASX() local
Drow_lsx.cc988 __m128i reg0, reg1, reg2, reg3, dst0, dst1; in ARGBToUV444Row_LSX() local
1102 __m128i reg0, reg1, reg2, reg3, reg4, reg5; in ARGBAttenuateRow_LSX() local
1291 __m128i reg0, reg1, reg2, reg3; in ARGB4444ToARGBRow_LSX() local
1530 __m128i reg0, reg1, reg2, reg3, dst0; in ARGB1555ToUVRow_LSX() local
1639 __m128i reg0, reg1, reg2, reg3, dst0; in RGB565ToUVRow_LSX() local
2512 __m128i reg0, reg1, reg2, reg3; in ARGBBlendRow_LSX() local
2558 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBQuantizeRow_LSX() local
2738 __m128 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in HalfFloatRow_LSX() local
/external/tensorflow/tensorflow/lite/tools/serialization/
Dwriter_lib_test.cc221 const TfLiteRegistration* reg3 = resolver.FindOp(BuiltinOperator_RELU6, 1); in TEST_P() local
/external/pytorch/torch/csrc/jit/runtime/
Dregister_prim_ops_fulljit.cpp683 RegisterOperators reg3({ variable
/external/XNNPACK/src/xnnpack/
Daarch32-assembler.h241 DRegister reg3; member

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