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Searched defs:rs1 (Results 1 – 6 of 6) sorted by relevance

/art/compiler/utils/riscv64/
Dassembler_riscv64.cc99 void Riscv64Assembler::Jalr(XRegister rd, XRegister rs1, int32_t offset) { in Jalr()
115 void Riscv64Assembler::Beq(XRegister rs1, XRegister rs2, int32_t offset) { in Beq()
129 void Riscv64Assembler::Bne(XRegister rs1, XRegister rs2, int32_t offset) { in Bne()
143 void Riscv64Assembler::Blt(XRegister rs1, XRegister rs2, int32_t offset) { in Blt()
147 void Riscv64Assembler::Bge(XRegister rs1, XRegister rs2, int32_t offset) { in Bge()
151 void Riscv64Assembler::Bltu(XRegister rs1, XRegister rs2, int32_t offset) { in Bltu()
155 void Riscv64Assembler::Bgeu(XRegister rs1, XRegister rs2, int32_t offset) { in Bgeu()
161 void Riscv64Assembler::Lb(XRegister rd, XRegister rs1, int32_t offset) { in Lb()
166 void Riscv64Assembler::Lh(XRegister rd, XRegister rs1, int32_t offset) { in Lh()
179 void Riscv64Assembler::Lw(XRegister rd, XRegister rs1, int32_t offset) { in Lw()
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Dassembler_riscv64.h401 void FMAddS(FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3) { in FMAddS()
404 void FMAddD(FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3) { in FMAddD()
407 void FMSubS(FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3) { in FMSubS()
410 void FMSubD(FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3) { in FMSubD()
413 void FNMSubS(FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3) { in FNMSubS()
416 void FNMSubD(FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3) { in FNMSubD()
419 void FNMAddS(FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3) { in FNMAddS()
422 void FNMAddD(FRegister rd, FRegister rs1, FRegister rs2, FRegister rs3) { in FNMAddD()
451 void FAddS(FRegister rd, FRegister rs1, FRegister rs2) { in FAddS()
454 void FAddD(FRegister rd, FRegister rs1, FRegister rs2) { in FAddD()
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Dassembler_riscv64_test.cc986 for (XRegister rs1 : GetRegisters()) { in TestAddConst() local
1055 for (XRegister rs1 : GetRegisters()) { in RepeatLoadStoreArbitraryOffset() local
1113 auto get_temp = [&](XRegister rs1) { in TestLoadStoreArbitraryOffset()
1125 [&](XRegister rs1, int64_t offset) { (GetAssembler()->*fn)(rd, rs1, offset); }); in TestLoadStoreArbitraryOffset()
1137 [&](XRegister rs1) { return rs1 != TMP ? TMP : TMP2; }, in TestFPLoadStoreArbitraryOffset()
1138 [&](XRegister rs1, int64_t offset) { (GetAssembler()->*fn)(rd, rs1, offset); }); in TestFPLoadStoreArbitraryOffset()
8690 auto emit_op = [&](XRegister rd, XRegister rs1, int64_t value) { in TEST_F()
8698 auto emit_op = [&](XRegister rd, XRegister rs1, int64_t value) { in TEST_F()
/art/disassembler/
Ddisassembler_riscv64.cc359 void DisassemblerRiscv64::Printer::PrintLoadStoreAddress(uint32_t rs1, int32_t offset) { in PrintLoadStoreAddress()
412 uint32_t rs1 = GetRs1(insn32); in Print32Jalr() local
447 uint32_t rs1 = GetRs1(insn32); in Print32BCond() local
713 uint32_t rs1 = GetRs1(insn32); in Print32BinOpImm() local
784 uint32_t rs1 = GetRs1(insn32); in Print32BinOp() local
867 uint32_t rs1 = GetRs1(insn32); in Print32Atomic() local
885 uint32_t rs1 = GetRs1(insn32); in Print32FpOp() local
1029 /*inout*/ const char*& rs1, in MaybeSwapOperands()
1046 const char* rs1 = nullptr; in Print32RVVOp() local
/art/compiler/optimizing/
Dcode_generator_riscv64.cc788 Reg rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FpBinOp()
799 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FAdd()
804 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FSub()
809 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FDiv()
814 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FMul()
819 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FMin()
824 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FMax()
829 XRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FEq()
834 XRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FLt()
839 XRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FLe()
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Dintrinsics_riscv64.cc290 EmitMemoryPeek(invoke, [&](XRegister rd, XRegister rs1) { __ Lb(rd, rs1, 0); }); in VisitMemoryPeekByte()
299 EmitMemoryPeek(invoke, [&](XRegister rd, XRegister rs1) { __ Lw(rd, rs1, 0); }); in VisitMemoryPeekIntNative()
308 EmitMemoryPeek(invoke, [&](XRegister rd, XRegister rs1) { __ Ld(rd, rs1, 0); }); in VisitMemoryPeekLongNative()
317 EmitMemoryPeek(invoke, [&](XRegister rd, XRegister rs1) { __ Lh(rd, rs1, 0); }); in VisitMemoryPeekShortNative()
348 EmitMemoryPoke(invoke, [&](XRegister rs2, XRegister rs1) { __ Sb(rs2, rs1, 0); }); in VisitMemoryPokeByte()
357 EmitMemoryPoke(invoke, [&](XRegister rs2, XRegister rs1) { __ Sw(rs2, rs1, 0); }); in VisitMemoryPokeIntNative()
366 EmitMemoryPoke(invoke, [&](XRegister rs2, XRegister rs1) { __ Sd(rs2, rs1, 0); }); in VisitMemoryPokeLongNative()
375 EmitMemoryPoke(invoke, [&](XRegister rs2, XRegister rs1) { __ Sh(rs2, rs1, 0); }); in VisitMemoryPokeShortNative()
380 XRegister rs1, in GenerateReverseBytes()
523 EmitIntegralUnOp(invoke, [&](XRegister rd, XRegister rs1) { __ Cpopw(rd, rs1); }); in VisitIntegerBitCount()
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