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Searched defs:rt (Results 1 – 7 of 7) sorted by relevance

/art/test/800-smali/
Djni.cc31 Runtime* rt = Runtime::Current(); in Java_Main_isAotVerified() local
/art/runtime/
Dreference_table_test.cc89 ReferenceTable rt("test", 0, 11); in TEST_F() local
279 ReferenceTable rt("test", 0, 20); in TEST_F() local
/art/compiler/utils/riscv64/
Dassembler_riscv64.cc6274 void Riscv64Assembler::Blez(XRegister rt, int32_t offset) { in Blez()
6278 void Riscv64Assembler::Bgez(XRegister rt, int32_t offset) { in Bgez()
6282 void Riscv64Assembler::Bltz(XRegister rt, int32_t offset) { in Bltz()
6286 void Riscv64Assembler::Bgtz(XRegister rt, int32_t offset) { in Bgtz()
6290 void Riscv64Assembler::Bgt(XRegister rs, XRegister rt, int32_t offset) { in Bgt()
6294 void Riscv64Assembler::Ble(XRegister rs, XRegister rt, int32_t offset) { in Ble()
6298 void Riscv64Assembler::Bgtu(XRegister rs, XRegister rt, int32_t offset) { in Bgtu()
6302 void Riscv64Assembler::Bleu(XRegister rs, XRegister rt, int32_t offset) { in Bleu()
6515 void Riscv64Assembler::Beq(XRegister rs, XRegister rt, Riscv64Label* label, bool is_bare) { in Beq()
6519 void Riscv64Assembler::Bne(XRegister rs, XRegister rt, Riscv64Label* label, bool is_bare) { in Bne()
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Dassembler_riscv64_test.cc545 XRegister rt = A1; in EmitBcondForAllConditions() local
/art/compiler/optimizing/
Dloop_optimization.cc1313 HInstruction* rt = Insert( in VectorizePredicated() local
1462 HInstruction* rt = Insert( in VectorizeTraditional() local
Dcode_generator_arm_vixl.cc116 static inline bool CanEmitNarrowLdr(vixl32::Register rt, vixl32::Register rn, uint32_t offset) { in CanEmitNarrowLdr()
/art/openjdkjvmti/
Dti_method.cc671 const art::verifier::RegType& rt = line->GetRegisterType(verifier.get(), slot_); in InferSlotTypeFromVerifier() local