1 /**************************************************************************
2 *
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 **************************************************************************/
8
9 #include "pipe/p_video_codec.h"
10 #include "radeon_vcn_dec.h"
11 #include "radeon_video.h"
12 #include "radeonsi/si_pipe.h"
13 #include "util/u_memory.h"
14 #include "util/u_video.h"
15
16 #include "ac_vcn_dec.h"
17 #include "amd/addrlib/inc/addrtypes.h"
18
19 #include <assert.h>
20 #include <stdio.h>
21
radeon_jpeg_get_decode_param(struct radeon_decoder * dec,struct pipe_video_buffer * target,struct pipe_picture_desc * picture)22 static struct pb_buffer_lean *radeon_jpeg_get_decode_param(struct radeon_decoder *dec,
23 struct pipe_video_buffer *target,
24 struct pipe_picture_desc *picture)
25 {
26 struct si_context *sctx = (struct si_context *)dec->base.context;
27 struct si_texture *luma = (struct si_texture *)((struct vl_video_buffer *)target)->resources[0];
28 struct si_texture *chroma, *chromav;
29
30 dec->jpg.bsd_size = align(dec->bs_size, 128);
31 dec->jpg.dt_luma_top_offset = luma->surface.u.gfx9.surf_offset;
32 dec->jpg.dt_chroma_top_offset = 0;
33 dec->jpg.dt_chromav_top_offset = 0;
34 dec->jpg.dt_swizzle_mode = luma->surface.u.gfx9.swizzle_mode;
35
36 if (sctx->gfx_level >= GFX12) {
37 switch (dec->jpg.dt_swizzle_mode) {
38 case ADDR3_256B_2D:
39 case ADDR3_4KB_2D:
40 case ADDR3_64KB_2D:
41 case ADDR3_256KB_2D:
42 dec->jpg.dt_addr_mode = RDECODE_TILE_8X8;
43 break;
44 case ADDR3_LINEAR:
45 default:
46 dec->jpg.dt_addr_mode = RDECODE_TILE_LINEAR;
47 break;
48 }
49 } else {
50 switch (dec->jpg.dt_swizzle_mode) {
51 case ADDR_SW_256B_D:
52 case ADDR_SW_4KB_D:
53 case ADDR_SW_64KB_D:
54 case ADDR_SW_4KB_D_X:
55 case ADDR_SW_64KB_D_X:
56 case ADDR_SW_64KB_R_X:
57 case ADDR_SW_256KB_D_X:
58 case ADDR_SW_256KB_R_X:
59 dec->jpg.dt_addr_mode = RDECODE_TILE_8X8;
60 break;
61 case ADDR_SW_256B_S:
62 case ADDR_SW_4KB_S:
63 case ADDR_SW_64KB_S:
64 case ADDR_SW_4KB_S_X:
65 case ADDR_SW_64KB_S_X:
66 case ADDR_SW_256KB_S_X:
67 dec->jpg.dt_addr_mode = RDECODE_TILE_32AS8;
68 break;
69 case ADDR_SW_LINEAR:
70 default:
71 dec->jpg.dt_addr_mode = RDECODE_TILE_LINEAR;
72 break;
73 }
74 }
75
76 switch (target->buffer_format) {
77 case PIPE_FORMAT_Y8_U8_V8_444_UNORM:
78 case PIPE_FORMAT_Y8_U8_V8_440_UNORM:
79 case PIPE_FORMAT_R8_G8_B8_UNORM:
80 chromav = (struct si_texture *)((struct vl_video_buffer *)target)->resources[2];
81 dec->jpg.dt_chromav_top_offset = chromav->surface.u.gfx9.surf_offset;
82 chroma = (struct si_texture *)((struct vl_video_buffer*)target)->resources[1];
83 dec->jpg.dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset;
84 break;
85 case PIPE_FORMAT_NV12:
86 chroma = (struct si_texture *)((struct vl_video_buffer*)target)->resources[1];
87 dec->jpg.dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset;
88 break;
89 case PIPE_FORMAT_YUYV:
90 case PIPE_FORMAT_Y8_400_UNORM:
91 case PIPE_FORMAT_R8G8B8A8_UNORM:
92 case PIPE_FORMAT_A8R8G8B8_UNORM:
93 break;
94 default:
95 assert(0);
96 break;
97 }
98 dec->jpg.dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w;
99 dec->jpg.dt_uv_pitch = dec->jpg.dt_pitch / 2;
100
101 return luma->buffer.buf;
102 }
103
104 /* add a new set register command to the IB */
set_reg_jpeg(struct radeon_decoder * dec,unsigned reg,unsigned cond,unsigned type,uint32_t val)105 static void set_reg_jpeg(struct radeon_decoder *dec, unsigned reg, unsigned cond, unsigned type,
106 uint32_t val)
107 {
108 radeon_emit(&dec->jcs[dec->cb_idx], RDECODE_PKTJ(reg, cond, type));
109 radeon_emit(&dec->jcs[dec->cb_idx], val);
110 }
111
112 /* send a bitstream buffer command */
send_cmd_bitstream(struct radeon_decoder * dec,struct pb_buffer_lean * buf,uint32_t off,unsigned usage,enum radeon_bo_domain domain)113 static void send_cmd_bitstream(struct radeon_decoder *dec, struct pb_buffer_lean *buf, uint32_t off,
114 unsigned usage, enum radeon_bo_domain domain)
115 {
116 uint64_t addr;
117
118 // jpeg soft reset
119 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 1);
120
121 // ensuring the Reset is asserted in SCLK domain
122 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C2);
123 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0x01400200);
124 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
125 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 9));
126 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
127
128 // wait mem
129 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0);
130
131 // ensuring the Reset is de-asserted in SCLK domain
132 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
133 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9));
134 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
135
136 dec->ws->cs_add_buffer(&dec->jcs[dec->cb_idx], buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
137 addr = dec->ws->buffer_get_virtual_address(buf);
138 addr = addr + off;
139
140 // set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address
141 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH), COND0, TYPE0,
142 (addr >> 32));
143 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW), COND0, TYPE0, addr);
144
145 // set jpeg_rb_base
146 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_RB_BASE), COND0, TYPE0, 0);
147
148 // set jpeg_rb_base
149 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_RB_SIZE), COND0, TYPE0, 0xFFFFFFF0);
150
151 // set jpeg_rb_wptr
152 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_RB_WPTR), COND0, TYPE0, (dec->jpg.bsd_size >> 2));
153 }
154
155 /* send a target buffer command */
send_cmd_target(struct radeon_decoder * dec,struct pb_buffer_lean * buf,uint32_t off,unsigned usage,enum radeon_bo_domain domain)156 static void send_cmd_target(struct radeon_decoder *dec, struct pb_buffer_lean *buf, uint32_t off,
157 unsigned usage, enum radeon_bo_domain domain)
158 {
159 uint64_t addr;
160
161 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_PITCH), COND0, TYPE0, (dec->jpg.dt_pitch >> 4));
162 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_UV_PITCH), COND0, TYPE0,
163 ((dec->jpg.dt_uv_pitch * 2) >> 4));
164
165 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_TILING_CTRL), COND0, TYPE0,
166 dec->jpg.dt_addr_mode | (dec->jpg.dt_swizzle_mode << 3));
167 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_UV_TILING_CTRL), COND0, TYPE0,
168 dec->jpg.dt_addr_mode | (dec->jpg.dt_swizzle_mode << 3));
169
170 dec->ws->cs_add_buffer(&dec->jcs[dec->cb_idx], buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
171 addr = dec->ws->buffer_get_virtual_address(buf);
172 addr = addr + off;
173
174 // set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address
175 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH), COND0, TYPE0,
176 (addr >> 32));
177 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW), COND0, TYPE0, addr);
178
179 // set output buffer data address
180 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_INDEX), COND0, TYPE0, 0);
181 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_DATA), COND0, TYPE0, dec->jpg.dt_luma_top_offset);
182 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_INDEX), COND0, TYPE0, 1);
183 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_DATA), COND0, TYPE0, dec->jpg.dt_chroma_top_offset);
184 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_TIER_CNTL2), COND0, TYPE3, 0);
185
186 // set output buffer read pointer
187 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_OUTBUF_RPTR), COND0, TYPE0, 0);
188
189 // enable error interrupts
190 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_INT_EN), COND0, TYPE0, 0xFFFFFFFE);
191
192 // start engine command
193 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0x6);
194
195 // wait for job completion, wait for job JBSI fetch done
196 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
197 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (dec->jpg.bsd_size >> 2));
198 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C2);
199 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0x01400200);
200 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_RB_RPTR), COND0, TYPE3, 0xFFFFFFFF);
201
202 // wait for job jpeg outbuf idle
203 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
204 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0xFFFFFFFF);
205 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_OUTBUF_WPTR), COND0, TYPE3, 0x00000001);
206
207 // stop engine
208 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0x4);
209
210 // asserting jpeg lmi drop
211 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x0005);
212 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 23 | 1 << 0));
213 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE1, 0);
214
215 // asserting jpeg reset
216 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 1);
217
218 // ensure reset is asserted in sclk domain
219 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
220 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 9));
221 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
222
223 // de-assert jpeg reset
224 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0);
225
226 // ensure reset is de-asserted in sclk domain
227 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
228 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9));
229 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
230
231 // de-asserting jpeg lmi drop
232 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x0005);
233 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0);
234 }
235
236 /* send a bitstream buffer command */
send_cmd_bitstream_direct(struct radeon_decoder * dec,struct pb_buffer_lean * buf,uint32_t off,unsigned usage,enum radeon_bo_domain domain)237 static void send_cmd_bitstream_direct(struct radeon_decoder *dec, struct pb_buffer_lean *buf,
238 uint32_t off, unsigned usage,
239 enum radeon_bo_domain domain)
240 {
241 uint64_t addr;
242
243 // jpeg soft reset
244 set_reg_jpeg(dec, dec->jpg_reg.jpeg_dec_soft_rst, COND0, TYPE0, 1);
245
246 // ensuring the Reset is asserted in SCLK domain
247 set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_cond_rd_timer, COND0, TYPE0, 0x01400200);
248 set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_ref_data, COND0, TYPE0, (0x1 << 0x10));
249 set_reg_jpeg(dec, dec->jpg_reg.jpeg_dec_soft_rst, COND3, TYPE3, (0x1 << 0x10));
250
251 // wait mem
252 set_reg_jpeg(dec, dec->jpg_reg.jpeg_dec_soft_rst, COND0, TYPE0, 0);
253
254 // ensuring the Reset is de-asserted in SCLK domain
255 set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_ref_data, COND0, TYPE0, (0 << 0x10));
256 set_reg_jpeg(dec, dec->jpg_reg.jpeg_dec_soft_rst, COND3, TYPE3, (0x1 << 0x10));
257
258 dec->ws->cs_add_buffer(&dec->jcs[dec->cb_idx], buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
259 addr = dec->ws->buffer_get_virtual_address(buf);
260 addr = addr + off;
261
262 // set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address
263 set_reg_jpeg(dec, dec->jpg_reg.lmi_jpeg_read_64bit_bar_high, COND0, TYPE0, (addr >> 32));
264 set_reg_jpeg(dec, dec->jpg_reg.lmi_jpeg_read_64bit_bar_low, COND0, TYPE0, addr);
265
266 // set jpeg_rb_base
267 set_reg_jpeg(dec, dec->jpg_reg.jpeg_rb_base, COND0, TYPE0, 0);
268
269 // set jpeg_rb_base
270 set_reg_jpeg(dec, dec->jpg_reg.jpeg_rb_size, COND0, TYPE0, 0xFFFFFFF0);
271
272 // set jpeg_rb_wptr
273 set_reg_jpeg(dec, dec->jpg_reg.jpeg_rb_wptr, COND0, TYPE0, (dec->jpg.bsd_size >> 2));
274 }
275
276 /* send a target buffer command */
send_cmd_target_direct(struct radeon_decoder * dec,struct pb_buffer_lean * buf,uint32_t off,unsigned usage,enum radeon_bo_domain domain,enum pipe_format buffer_format)277 static void send_cmd_target_direct(struct radeon_decoder *dec, struct pb_buffer_lean *buf, uint32_t off,
278 unsigned usage, enum radeon_bo_domain domain,
279 enum pipe_format buffer_format)
280 {
281 uint64_t addr;
282 uint32_t val;
283 bool format_convert = false;
284 uint32_t fc_sps_info_val = 0;
285
286 switch (buffer_format) {
287 case PIPE_FORMAT_R8G8B8A8_UNORM:
288 format_convert = true;
289 fc_sps_info_val = 1 | (1 << 4) | (0xff << 8);
290 break;
291 case PIPE_FORMAT_A8R8G8B8_UNORM:
292 format_convert = true;
293 fc_sps_info_val = 1 | (1 << 4) | (1 << 5) | (0xff << 8);
294 break;
295 case PIPE_FORMAT_R8_G8_B8_UNORM:
296 format_convert = true;
297 fc_sps_info_val = 1 | (1 << 5) | (0xff << 8);
298 break;
299 default:
300 break;
301 }
302
303 if (dec->jpg_reg.version == RDECODE_JPEG_REG_VER_V3 && format_convert) {
304 set_reg_jpeg(dec, dec->jpg_reg.jpeg_pitch, COND0, TYPE0, dec->jpg.dt_pitch);
305 set_reg_jpeg(dec, dec->jpg_reg.jpeg_uv_pitch, COND0, TYPE0, (dec->jpg.dt_uv_pitch * 2));
306 } else {
307 set_reg_jpeg(dec, dec->jpg_reg.jpeg_pitch, COND0, TYPE0, (dec->jpg.dt_pitch >> 4));
308 set_reg_jpeg(dec, dec->jpg_reg.jpeg_uv_pitch, COND0, TYPE0, ((dec->jpg.dt_uv_pitch * 2) >> 4));
309 }
310
311 set_reg_jpeg(dec, dec->jpg_reg.dec_addr_mode, COND0, TYPE0,
312 dec->jpg.dt_addr_mode | (dec->jpg.dt_addr_mode << 2));
313 set_reg_jpeg(dec, dec->jpg_reg.dec_y_gfx10_tiling_surface, COND0, TYPE0, dec->jpg.dt_swizzle_mode);
314 set_reg_jpeg(dec, dec->jpg_reg.dec_uv_gfx10_tiling_surface, COND0, TYPE0, dec->jpg.dt_swizzle_mode);
315
316 dec->ws->cs_add_buffer(&dec->jcs[dec->cb_idx], buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
317 addr = dec->ws->buffer_get_virtual_address(buf);
318 addr = addr + off;
319
320 // set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address
321 set_reg_jpeg(dec, dec->jpg_reg.lmi_jpeg_write_64bit_bar_high, COND0, TYPE0, (addr >> 32));
322 set_reg_jpeg(dec, dec->jpg_reg.lmi_jpeg_write_64bit_bar_low, COND0, TYPE0, addr);
323
324 // set output buffer data address
325 if (dec->jpg_reg.version == RDECODE_JPEG_REG_VER_V2) {
326 set_reg_jpeg(dec, dec->jpg_reg.jpeg_index, COND0, TYPE0, 0);
327 set_reg_jpeg(dec, dec->jpg_reg.jpeg_data, COND0, TYPE0, dec->jpg.dt_luma_top_offset);
328 set_reg_jpeg(dec, dec->jpg_reg.jpeg_index, COND0, TYPE0, 1);
329 set_reg_jpeg(dec, dec->jpg_reg.jpeg_data, COND0, TYPE0, dec->jpg.dt_chroma_top_offset);
330 if (dec->jpg.dt_chromav_top_offset) {
331 set_reg_jpeg(dec, dec->jpg_reg.jpeg_index, COND0, TYPE0, 2);
332 set_reg_jpeg(dec, dec->jpg_reg.jpeg_data, COND0, TYPE0, dec->jpg.dt_chromav_top_offset);
333 }
334 } else {
335 set_reg_jpeg(dec, dec->jpg_reg.jpeg_luma_base0_0, COND0, TYPE0, dec->jpg.dt_luma_top_offset);
336 set_reg_jpeg(dec, dec->jpg_reg.jpeg_chroma_base0_0, COND0, TYPE0, dec->jpg.dt_chroma_top_offset);
337 set_reg_jpeg(dec, dec->jpg_reg.jpeg_chromav_base0_0, COND0, TYPE0, dec->jpg.dt_chromav_top_offset);
338 if (dec->jpg.crop_width && dec->jpg.crop_height) {
339 set_reg_jpeg(dec, vcnipUVD_JPEG_ROI_CROP_POS_START, COND0, TYPE0,
340 ((dec->jpg.crop_y << 16) | dec->jpg.crop_x));
341 set_reg_jpeg(dec, vcnipUVD_JPEG_ROI_CROP_POS_STRIDE, COND0, TYPE0,
342 ((dec->jpg.crop_height << 16) | dec->jpg.crop_width));
343 } else {
344 set_reg_jpeg(dec, vcnipUVD_JPEG_ROI_CROP_POS_START, COND0, TYPE0,
345 ((0 << 16) | 0));
346 set_reg_jpeg(dec, vcnipUVD_JPEG_ROI_CROP_POS_STRIDE, COND0, TYPE0,
347 ((1 << 16) | 1));
348 }
349 if (format_convert) {
350 /* set fc timeout control */
351 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_TMEOUT_CNT, COND0, TYPE0,(4244373504));
352 /* set alpha position and packed format */
353 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_SPS_INFO, COND0, TYPE0, fc_sps_info_val);
354 /* coefs */
355 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_R_COEF, COND0, TYPE0, 256 | (0 << 10) | (403 << 20));
356 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_G_COEF, COND0, TYPE0, 256 | (976 << 10) | (904 << 20));
357 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_B_COEF, COND0, TYPE0, 256 | (475 << 10) | (0 << 20));
358 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_VUP_COEF_CNTL0, COND0, TYPE0, 128 | (384 << 16));
359 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_VUP_COEF_CNTL1, COND0, TYPE0, 384 | (128 << 16));
360 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_VUP_COEF_CNTL2, COND0, TYPE0, 128 | (384 << 16));
361 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_VUP_COEF_CNTL3, COND0, TYPE0, 384 | (128 << 16));
362 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_HUP_COEF_CNTL0, COND0, TYPE0, 128 | (384 << 16));
363 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_HUP_COEF_CNTL1, COND0, TYPE0, 384 | (128 << 16));
364 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_HUP_COEF_CNTL2, COND0, TYPE0, 128 | (384 << 16));
365 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_HUP_COEF_CNTL3, COND0, TYPE0, 384 | (128 << 16));
366 } else
367 set_reg_jpeg(dec, vcnipUVD_JPEG_FC_SPS_INFO, COND0, TYPE0, 1 | (1 << 5) | (255 << 8));
368 }
369 set_reg_jpeg(dec, dec->jpg_reg.jpeg_tier_cntl2, COND0, 0, 0);
370
371 // set output buffer read pointer
372 set_reg_jpeg(dec, dec->jpg_reg.jpeg_outbuf_rptr, COND0, TYPE0, 0);
373 set_reg_jpeg(dec, dec->jpg_reg.jpeg_outbuf_cntl, COND0, TYPE0,
374 ((0x00001587 & (~0x00000180L)) | (0x1 << 0x7) | (0x1 << 0x6)));
375
376 // enable error interrupts
377 set_reg_jpeg(dec, dec->jpg_reg.jpeg_int_en, COND0, TYPE0, 0xFFFFFFFE);
378
379 // start engine command
380 val = 0x6;
381 if (dec->jpg_reg.version == RDECODE_JPEG_REG_VER_V3) {
382 if (dec->jpg.crop_width && dec->jpg.crop_height)
383 val = val | (0x1 << 24);
384 if (format_convert)
385 val = val | (1 << 16) | (1 << 18);
386 }
387 set_reg_jpeg(dec, dec->jpg_reg.jpeg_cntl, COND0, TYPE0, val);
388
389 // wait for job completion, wait for job JBSI fetch done
390 set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_ref_data, COND0, TYPE0, (dec->jpg.bsd_size >> 2));
391 set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_cond_rd_timer, COND0, TYPE0, 0x01400200);
392 set_reg_jpeg(dec, dec->jpg_reg.jpeg_rb_rptr, COND3, TYPE3, 0xFFFFFFFF);
393
394 // wait for job jpeg outbuf idle
395 set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_ref_data, COND0, TYPE0, 0xFFFFFFFF);
396 set_reg_jpeg(dec, dec->jpg_reg.jpeg_outbuf_wptr, COND3, TYPE3, 0x00000001);
397
398 if (dec->jpg_reg.version == RDECODE_JPEG_REG_VER_V3 && format_convert) {
399 val = val | (0x7 << 16);
400 set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_ref_data, COND0, TYPE0, 0);
401 set_reg_jpeg(dec, vcnipUVD_JPEG_INT_STAT, COND3, TYPE3, val);
402 }
403
404 // stop engine
405 set_reg_jpeg(dec, dec->jpg_reg.jpeg_cntl, COND0, TYPE0, 0x4);
406 }
407
408 /**
409 * send cmd for vcn jpeg
410 */
send_cmd_jpeg(struct radeon_decoder * dec,struct pipe_video_buffer * target,struct pipe_picture_desc * picture)411 bool send_cmd_jpeg(struct radeon_decoder *dec, struct pipe_video_buffer *target,
412 struct pipe_picture_desc *picture)
413 {
414 struct pb_buffer_lean *dt;
415 struct rvid_buffer *bs_buf;
416
417 bs_buf = &dec->bs_buffers[dec->cur_buffer];
418
419 memset(dec->bs_ptr, 0, align(dec->bs_size, 128) - dec->bs_size);
420 dec->ws->buffer_unmap(dec->ws, bs_buf->res->buf);
421 dec->bs_ptr = NULL;
422
423 dt = radeon_jpeg_get_decode_param(dec, target, picture);
424
425 if (dec->jpg_reg.version == RDECODE_JPEG_REG_VER_V1) {
426 send_cmd_bitstream(dec, bs_buf->res->buf, 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
427 send_cmd_target(dec, dt, 0, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
428 } else {
429 send_cmd_bitstream_direct(dec, bs_buf->res->buf, 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
430 send_cmd_target_direct(dec, dt, 0, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM, target->buffer_format);
431 }
432
433 return true;
434 }
435