1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 3 #ifndef _PI_API_H 4 #define _PI_API_H 5 6 #ifndef __ETT__ 7 #define __ETT__ 0 8 #endif 9 10 #define __FLASH_TOOL_DA__ 0 11 #define CFG_DRAM_LOG_TO_STORAGE 0 12 13 #define FORCE_FASTK 14 15 /***********************************************************************/ 16 /* Includes */ 17 /***********************************************************************/ 18 19 /***********************************************************************/ 20 /* Constant Define */ 21 /***********************************************************************/ 22 23 #define SW_CHANGE_FOR_SIMULATION 0 //calibration funciton for whole chip simulation. Code changed due to different compiler 24 #ifndef FOR_DV_SIMULATION_USED 25 #define FOR_DV_SIMULATION_USED (FALSE) ////calibration funciton for DV simulation. Code changed due to different compiler#define FT_DSIM_USED 0 26 #endif 27 #define DV_SIMULATION_LP4 1 28 #define BYPASS_CALIBRATION 0 29 //Bring Up Selection : Do Not open it when normal operation 30 //#define SLT 31 //#define FIRST_BRING_UP 32 //#define DUMP_INIT_RG_LOG_TO_DE //dump init RG settings to DE 33 34 #include "dramc_typedefs.h" 35 #include "dramc_reg_base_addr.h" 36 #include <soc/addressmap.h> 37 #include <soc/dramc_soc.h> 38 #include <soc/dramc_param.h> 39 40 #define CPU_RW_TEST_AFTER_K 0 41 #define TA2_RW_TEST_AFTER_K 0 42 43 #define ENABLE (1) 44 #define DISABLE (0) 45 #define ON (1) 46 #define OFF (0) 47 #define AUTOK_ON (1) 48 #define AUTOK_OFF (0) 49 #define DCM_ON (1) 50 #define DCM_OFF (0) 51 52 53 //Read Chip QT Tool 54 #ifndef QT_GUI_Tool 55 #define QT_GUI_Tool 0 //Setting 1 when using QT GUI Tool Compiler. 56 #define HAPS_FPFG_A60868 0 //Setting 1 when testing HAPS FPGA 57 #endif 58 59 //DRAMC Chip 60 #define fcA60868 1 61 #define fcPetrus 2 62 #define fcIPM 3 63 #define fcMargaux 4 64 #define fcFOR_CHIP_ID fcMargaux 65 66 #define __A60868_TO_BE_PORTING__ 0 67 #define __Petrus_TO_BE_PORTING__ 0 68 69 #define VENDOR_SAMSUNG 1 70 #define VENDOR_HYNIX 6 71 #define REVISION_ID_MAGIC 0x9501 72 73 74 #define __LP5_COMBO__ (FALSE) 75 #define FEATURE_RDDQC_K_DMI (FALSE) // This feature is not supported at A60868 test chip 76 77 78 #if __ETT__ 79 #define __FLASH_TOOL_DA__ 0 80 #endif 81 82 #if (FEATURE_RDDQC_K_DMI == TRUE) 83 #define RDDQC_ADD_DMI_NUM 2 84 #else 85 #define RDDQC_ADD_DMI_NUM 0 86 #endif 87 88 #define CHANNEL_NUM 2 // single chhanel for A60868. 1 single channel, 2 dual channel, 4 channel 89 #define DPM_CH_NUM 2 // CH0/1 is Master, CH2/3 is Slave 90 91 //ZQ calibration 92 #define ENABLE_LP4_ZQ_CAL 1 93 #if ENABLE_LP4_ZQ_CAL //choose one mode to do ZQ calibration 94 #define ZQ_SWCMD_MODE 1 //suggested SW CMD mode 95 #define ZQ_RTSWCMD_MODE 0 //run time SW mode 96 #define ZQ_SCSM_MODE 0 //old mode 97 #endif 98 99 #define CALIBRATION_SPEED_UP_DEBUG 0 100 #define VENDER_JV_LOG 0 101 102 //SW option 103 #define DUAL_FREQ_K 0 //If enable, need to define DDR_xxxx the same as DUAL_FREQ_HIGH 104 #define ENABLE_EYESCAN_GRAPH 0 //__ETT__ //draw eye diagram after calibration, if enable, need to fix code size problem. 105 #define EYESCAN_GRAPH_CATX_VREF_STEP 1 // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868 106 #define EYESCAN_GRAPH_RX_VREF_STEP 2 107 #define EYESCAN_RX_VREF_RANGE_END 128 //field is 6 bit, but can only use 0~63,7bit ->127 108 #if (fcFOR_CHIP_ID == fcA60868) 109 #define ENABLE_EYESCAN_CBT 0 //TO DO:Forece to draw CBT eye diagram after calibration 110 #define ENABLE_EYESCAN_RX 0 //TO DO:Forece to draw RX eye diagram after calibration 111 #define ENABLE_EYESCAN_TX 0 //TO DO:Forece to draw TX eye diagram after calibration 112 #define ENABLE_VREFSCAN 0 //TO DO:Forece to Vref Scan for calibration 113 #endif 114 115 #define CHECK_HQA_CRITERIA 0 116 #define REDUCE_LOG_FOR_PRELOADER 1 117 #define APPLY_LP4_POWER_INIT_SEQUENCE 1 118 #define ENABLE_READ_DBI 0 119 #define ENABLE_WRITE_DBI 1 120 #define ENABLE_WRITE_DBI_Protect 0 121 #define ENABLE_TX_WDQS 1 122 #define ENABLE_WDQS_MODE_2 0 123 #define ENABLE_DRS 0 124 #define ENABLE_TX_TRACKING 1 125 #define ENABLE_K_WITH_WORST_SI_UI_SHIFT 1 126 #define ETT_MINI_STRESS_USE_TA2_LOOP_MODE 1 127 #define DUMP_TA2_WINDOW_SIZE_RX_TX 0 128 #if ENABLE_TX_TRACKING 129 #define ENABLE_SW_TX_TRACKING 0 //if SW_TX_TRACKING is 0, using HW_TX_TRACKING 130 #endif 131 #define ENABLE_PA_IMPRO_FOR_TX_TRACKING 1 132 #define ENABLE_WRITE_POST_AMBLE_1_POINT_5_TCK 1 133 #define ENABLE_RX_TRACKING 0 134 #define ENABLE_RX_DCM_DPHY 1 //Set 0 will lead DCM on/off error 135 #define ENABLE_OPEN_LOOP_MODE_OPTION 1 136 #define ENABLE_TMRRI_NEW_MODE 1 137 #define ENABLE_8PHASE_CALIBRATION 1 138 #define ENABLE_DUTY_SCAN_V2 1 139 #define DUTY_SCAN_V2_ONLY_K_HIGHEST_FREQ 0 //0: K all Freq 1: K highest Freq 140 #define APPLY_DQDQM_DUTY_CALIBRATION 1 141 #define IMPEDANCE_TRACKING_ENABLE //Impendence tracking 142 #define IMPEDANCE_HW_SAVING //mask because function fail, it lets clk swing change larger before DVFS occurs 143 #define ENABLE_MIOCK_JMETER 144 #define ENABLE_RUNTIME_MRW_FOR_LP5 1 145 #define ENABLE_RODT_TRACKING 1 146 #define GATING_ADJUST_TXDLY_FOR_TRACKING 1 147 #define TDQSCK_PRECALCULATION_FOR_DVFS 1 148 #define HW_GATING 149 #define ENABLE_RX_FIFO_MISMATCH_DEBUG 1 150 #define VERIFY_CKE_PWR_DOWN_FLOW 0 //Lewis add for DVT 151 #define CBT_MOVE_CA_INSTEAD_OF_CLK 1 // need to check on LP5 152 #define MRW_CHECK_ONLY 0 153 #define MRW_BACKUP 0 154 #define ENABLE_SAMSUNG_NT_ODT 0 155 #define DRAMC_MODEREG_CHECK 0 156 #define DVT_READ_LATENCY_MONITOR 0 157 158 #define PINMUX_AUTO_TEST_PER_BIT_CA 0 159 #define PINMUX_AUTO_TEST_PER_BIT_RX 0 160 #define PINMUX_AUTO_TEST_PER_BIT_TX 0 161 162 #define CA_PER_BIT_DELAY_CELL 1//LP4 163 #if PINMUX_AUTO_TEST_PER_BIT_CA 164 #undef CA_PER_BIT_DELAY_CELL 165 #define CA_PER_BIT_DELAY_CELL 0 166 #endif 167 168 //Gating calibration 169 #define GATING_LEADLAG_LOW_LEVEL_CHECK 0 170 171 //#define ENABLE_POST_PACKAGE_REPAIR 172 173 #define DPM_CONTROL_AFTERK 174 #if __ETT__ 175 #define ENABLE_DBG_2_0_IRQ 176 #endif 177 178 //////////////////////////////////// FIXME start ///////////////////////// 179 #define CMD_CKE_WORKAROUND_FIX 0 180 #define DQS_DUTY_SLT_CONDITION_TEST 0 181 #define DV_SIMULATION_BEFORE_K 0 182 #define DV_SIMULATION_DATLAT 0 183 #define DV_SIMULATION_DBI_ON 0 184 #define DV_SIMULATION_DFS 0 185 #define DV_SIMULATION_GATING 0 186 #define ENABLE_APB_MASK_WRITE 0 187 #define ENABLE_DVFS_BYPASS_MR13_FSP 0 188 #define ENABLE_RODT_TRACKING_SAVE_MCK 0 189 #define ETT_NO_DRAM 0 190 #define EYESCAN_LOG 0 191 #define FSP1_CLKCA_TERM 1 192 #define MR_CBT_SWITCH_FREQ !FOR_DV_SIMULATION_USED //@Darren, Wait DFS ready 193 #define FT_DSIM_USED 0 194 #define GATING_ONLY_FOR_DEBUG 0 195 #define MEASURE_DRAM_POWER_INDEX 0 196 #define PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER 0 197 #define REG_ACCESS_PORTING_DGB 0 198 #define RX_PIPE_BYPASS_ENABLE 0 199 #define SAMSUNG_TEST_MODE_MRS_FOR_PRELOADER 0 200 #define SUPPORT_PICG_MONITOR 0 201 #define SUPPORT_REQ_QUEUE_BLOCK_ALE 0 202 #define SUPPORT_REQ_QUEUE_READ_LATERNCY_MONITOR 0 203 #define REFRESH_OVERHEAD_REDUCTION 1 204 #define TEST_LOW_POWER_WITH_1_SEC_DELAY 1 //Add 1 second dealy between suspend and resume to avoid APHY control PATH is not switched to SPM {SPM_CONTROL_AFTERK} 205 #define TEST_LOW_POWER_WITH_STRESS 0 206 #if TEST_LOW_POWER_WITH_STRESS 207 #undef TEST_LOW_POWER_WITH_1_SEC_DELAY 208 #define TEST_LOW_POWER_WITH_1_SEC_DELAY 0 209 #endif 210 #define XRTRTR_NEW_CROSS_RK_MODE 1 211 #define XRTWTW_NEW_CROSS_RK_MODE 1 212 #define APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST 0 213 #define SUPPORT_HYNIX_RX_DQS_WEAK_PULL 0 214 #define RX_DLY_TRACK_ONLY_FOR_DEBUG 0 215 //Run time config 216 #define TEMP_SENSOR_ENABLE // Enable rumtime HMR4 217 #define ENABLE_REFRESH_RATE_DEBOUNCE 1 218 #define ENABLE_PER_BANK_REFRESH 1 219 #define PER_BANK_REFRESH_USE_MODE 1 // 0: original mode, 1: hybrid mode, 2: always pb mode 220 #define IMP_TRACKING_PB_TO_AB_REFRESH_WA 1 221 #define DRAMC_MODIFIED_REFRESH_MODE 1 222 #define DRAMC_CKE_DEBOUNCE 1 223 #define XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY 224 225 #define SAMSUNG_LP4_NWR_WORKAROUND 0 226 #define AC_TIMING_DERATE_ENABLE 1 227 #define ENABLE_EARLY_BG_CMD 0 // 0: Disable 1: Enable, Reduce the CMD latency by CTO_EBG request 228 229 //////////////////////////////////// DVFS ////////////////////////////// 230 #define ENABLE_DVS 1 //DVS need tracking enable 231 #define DRAMC_DFS_MODE 1 // 0:Legacy, 1:MD32 RG, 2: PHY RG 232 #define ENABLE_SRAM_DMA_WA 0 // for Pexxxs/Maxxxx/xxx868 233 #define ENABLE_ECO_SRAM_DMA_MISS_REG 1 // for Maxxxx 234 #define ENABLE_TX_REBASE_ODT_WA 0 // for Pexxxs/xxx868 235 #if ENABLE_TX_WDQS 236 #define ENABLE_TX_REBASE_WDQS_DQS_PI_WA 0 237 #endif 238 #define ENABLE_DFS_DEBUG_MODE 0 239 #define DFS_NOQUEUE_FLUSH_WA 1 240 #define DFS_NOQUEUE_FLUSH_LATENCY_CNT 0 241 #define ENABLE_DFS_NOQUEUE_FLUSH_DBG 0 242 #define ENABLE_CONFIG_MCK_4TO1_MUX 0 243 #define ENABLE_TPBR2PBR_REFRESH_TIMING 1 244 #define ENABLE_DFS_TIMING_ENLARGE 0 245 #define ENABLE_DFS_208M_CLOCK 0 246 #define ENABLE_DFS_HW_SAVE_MASK 0 247 #define ENABLE_LP4Y_DFS 0 248 #if ENABLE_LP4Y_DFS 249 #define ENABLE_LP4Y_WA 1 250 #define ENABLE_DFS_RUNTIME_MRW 1 251 #else 252 #define ENABLE_LP4Y_WA 0 253 #define ENABLE_DFS_RUNTIME_MRW 0 // for LP4x 254 #endif 255 #define ENABLE_TIMING_TXSR_DFS_WA REFRESH_OVERHEAD_REDUCTION // Wait overhead refresh enable, @Darren, Entry SREF -> EXIT SREF -> PDE Command violates tXSR time 256 #define ENABLE_RANK_NUMBER_AUTO_DETECTION 0 257 #define DDR_HW_AUTOK_POLLING_CNT 100000 258 259 //////////////////////////////////// FIXME end///////////////////////// 260 261 #if (fcFOR_CHIP_ID == fcA60868) 262 #define WORKAROUND_LP5_HEFF 1 //High efficiency mode 263 #undef ENABLE_RUNTIME_MRW_FOR_LP5 264 #define ENABLE_RUNTIME_MRW_FOR_LP5 0 // DV fail in 868, use RTSWCMD_MRW 265 #endif 266 267 #if ENABLE_RODT_TRACKING 268 #define GATING_RODT_LATANCY_EN 0 269 #else 270 #define GATING_RODT_LATANCY_EN 1 271 #endif 272 273 #define CHECK_GOLDEN_SETTING (FALSE) 274 #define APPLY_LOWPOWER_GOLDEN_SETTINGS 1 // 0: DCM Off, 1: DCM On 275 #define LP5_GOLDEN_SETTING_CHECKER (FALSE) // FALSE: enable LP4 checker 276 277 #if APPLY_LOWPOWER_GOLDEN_SETTINGS 278 #define TX_PICG_NEW_MODE 1 279 #define RX_PICG_NEW_MODE 1 280 #else 281 #define TX_PICG_NEW_MODE 0 282 #define RX_PICG_NEW_MODE 0 283 #endif 284 #define CMD_PICG_NEW_MODE 0 285 286 #define DDR_RESERVE_NEW_MODE 1 //0: old mode 1: new mode 287 //============================================================================= 288 // for D Sim sumulation used 289 //============================================================================= 290 #if QT_GUI_Tool || !FOR_DV_SIMULATION_USED 291 #define DV_SIMULATION_INIT_C 1 292 #define SIMULATION_LP4_ZQ 1 293 #define SIMULATION_SW_IMPED 1 294 #define SIMULATION_MIOCK_JMETER 0 295 #define SIMULATION_8PHASE 0 296 #define SIMULATION_RX_INPUT_BUF 0 297 #define SIMUILATION_CBT 1 298 #define SIMULATION_WRITE_LEVELING 1 299 #define SIMULATION_DUTY_CYC_MONITOR 0 300 #define SIMULATION_GATING 1 301 #define SIMULATION_DATLAT 1 302 #define SIMULATION_RX_RDDQC 1 303 #define SIMULATION_RX_PERBIT 1 304 #define SIMULATION_TX_PERBIT 1 // Please enable with write leveling 305 #define SIMULATION_RX_DVS 0 306 #define SIMULATION_RUNTIME_CONFIG 0 307 #else 308 #define DV_SIMULATION_INIT_C 1 309 #define SIMULATION_LP4_ZQ 1 310 #define SIMULATION_SW_IMPED 1 311 #define SIMULATION_MIOCK_JMETER 0 312 #define SIMULATION_8PHASE 0 313 #define SIMULATION_RX_INPUT_BUF 0 314 #define SIMUILATION_CBT 1 315 #define SIMULATION_WRITE_LEVELING 1 316 #define SIMULATION_DUTY_CYC_MONITOR 0 317 #define SIMULATION_GATING 1 318 #define SIMULATION_DATLAT 1 319 #define SIMULATION_RX_RDDQC 1 320 #define SIMULATION_RX_PERBIT 1 321 #define SIMULATION_TX_PERBIT 1 // Please enable with write leveling 322 #define SIMULATION_RX_DVS 0 323 #define SIMULATION_RUNTIME_CONFIG 1 // @Darren for DV sim 324 #endif 325 //Used to keep original VREF when doing Rx calibration for RX DVS 326 #define DVS_CAL_KEEP_VREF 0xf 327 328 //#define DDR_INIT_TIME_PROFILING 329 #define DDR_INIT_TIME_PROFILING_TEST_CNT 1 330 #ifdef DDR_INIT_TIME_PROFILING 331 extern U16 u2TimeProfileCnt; 332 #endif 333 334 //============================================================================= 335 // common 336 #define DQS_NUMBER 4 337 #define DQ_DATA_WIDTH 32 // define max support bus width in the system (to allocate array size) 338 #define TIME_OUT_CNT 100 //100us 339 #define HW_REG_SHUFFLE_MAX 4 340 341 typedef enum 342 { 343 BYTE_0 = 0, 344 BYTE_1 = 1, 345 ALL_BYTES 346 } BYTES_T; 347 348 //Should be removed after A60868 349 #define LP5_DDR4266_RDBI_WORKAROUND 0 350 #define CBT_O1_PINMUX_WORKAROUND 0 351 #define WLEV_O1_PINMUX_WORKAROUND 0 352 #define WCK_LEVELING_FM_WORKAROUND 0 353 354 355 /* Gating window */ 356 #define DQS_GW_COARSE_STEP 1 357 #define DQS_GW_FINE_START 0 358 #define DQS_GW_FINE_END 32 359 #define DQS_GW_FINE_STEP 4 360 361 #define DQS_GW_UI_PER_MCK 16 362 #define DQS_GW_PI_PER_UI 32 363 364 // DATLAT 365 #define DATLAT_TAP_NUMBER 32 366 367 // RX DQ/DQS 368 #define MAX_RX_DQSDLY_TAPS 508 // 0x018, May set back to 64 if no need. 369 #define MAX_RX_DQDLY_TAPS 252 370 #define RX_VREF_NOT_SPECIFY 0xff 371 #define RX_VREF_DUAL_RANK_K_FREQ 1866 // if freq >=RX_VREF_DUAL_RANK_K_FREQ, Rank1 rx vref K will be enable. 372 #define RX_VREF_RANGE_BEGIN 0 373 #define RX_VREF_RANGE_BEGIN_ODT_OFF 32 374 #define RX_VREF_RANGE_BEGIN_ODT_ON 24 375 #define RX_VREF_RANGE_END 128 //field is 6 bit, but can only use 0~63 376 #define RX_VREF_RANGE_STEP 1 377 #define RX_PASS_WIN_CRITERIA 30 378 #define RDDQC_PINMUX_WORKAROUND 1 379 380 // TX DQ/DQS 381 #define TX_AUTO_K_ENABLE 1 382 #if TX_AUTO_K_ENABLE 383 #define TX_AUTO_K_DEBUG_ENABLE 0 384 #define TX_AUTO_K_WORKAROUND 1 385 #define ENABLE_PA_IMPRO_FOR_TX_AUTOK 1 386 #endif 387 #define MAX_TX_DQDLY_TAPS 31 // max DQ TAP number 388 #define MAX_TX_DQSDLY_TAPS 31 // max DQS TAP number 389 #define TX_OE_EXTEND 0 390 #define TX_DQ_OE_SHIFT_LP5 5 391 #if TX_OE_EXTEND 392 #define TX_DQ_OE_SHIFT_LP4 4 393 #else 394 #define TX_DQ_OE_SHIFT_LP4 3 395 #endif 396 #define TX_DQ_OE_SHIFT_LP3 2 397 #define TX_K_DQM_WITH_WDBI 1 398 #define TX_OE_CALIBATION (!TX_OE_EXTEND) 399 400 #define TX_RETRY_ENABLE 0 401 #if TX_RETRY_ENABLE 402 #define TX_RETRY_CONTROL_BY_SPM 1 403 #define SW_TX_RETRY_ENABLE 0 404 #else 405 #define TX_RETRY_CONTROL_BY_SPM 0 406 #endif 407 408 // Sw work around options. 409 #define CA_TRAIN_RESULT_DO_NOT_MOVE_CLK 1 // work around for clock multi phase problem(cannot move clk or the clk will be bad) 410 #define DramcHWDQSGatingTracking_JADE_TRACKING_MODE 1 411 #define DramcHWDQSGatingTracking_FIFO_MODE 1 412 #define DONT_MOVE_CLK_DELAY // don't move clk delay 413 /* If defined for gFreqTbl and fastK 414 */ 415 #define LP4_SHU0_FREQ (1866) 416 #define LP4_SHU8_FREQ (1600) 417 #define LP4_SHU9_FREQ (1600) 418 #define LP4_SHU6_FREQ (1200) 419 #define LP4_SHU5_FREQ (1200) 420 #define LP4_SHU4_FREQ (800) 421 #define LP4_SHU3_FREQ (800) 422 #define LP4_SHU2_FREQ (600) 423 #define LP4_SHU1_FREQ (600) 424 #define LP4_SHU7_FREQ (400) 425 #define LP4_HIGHEST_FREQ LP4_SHU0_FREQ 426 427 #define LP4_SHU0_FREQSEL (LP4_DDR3733) 428 #define LP4_SHU8_FREQSEL (LP4_DDR3200) 429 #define LP4_SHU9_FREQSEL (LP4_DDR3200) 430 #define LP4_SHU6_FREQSEL (LP4_DDR2400) 431 #define LP4_SHU5_FREQSEL (LP4_DDR2400) 432 #define LP4_SHU4_FREQSEL (LP4_DDR1600) 433 #define LP4_SHU3_FREQSEL (LP4_DDR1600) 434 #define LP4_SHU2_FREQSEL (LP4_DDR1200) 435 #define LP4_SHU1_FREQSEL (LP4_DDR1200) 436 #define LP4_SHU7_FREQSEL (LP4_DDR800) 437 438 #if FOR_DV_SIMULATION_USED 439 #define DEFAULT_TEST2_1_CAL 0x55000000 // pattern0 and base address for test engine when we do calibration 440 #define DEFAULT_TEST2_2_CAL 0xaa000020 // pattern1 and offset address for test engine when we do calibraion 441 #else 442 #define DEFAULT_TEST2_1_CAL 0x55000000 // pattern0 and base address for test engine when we do calibration 443 #define DEFAULT_TEST2_2_CAL 0xaa000100 // pattern1 and offset address for test engine when we do calibraion 444 #endif 445 446 //CBT/CA training 447 #define CATRAINING_NUM_LP4 6 448 #define CATRAINING_NUM_LP5 7 449 #define CATRAINING_NUM CATRAINING_NUM_LP5 450 #define LP4_MRFSP_TERM_FREQ 1333 451 #define LP5_MRFSP_TERM_FREQ 1866 452 453 //Calibration Summary 454 #define PRINT_CALIBRATION_SUMMARY (!SW_CHANGE_FOR_SIMULATION) 455 #define PRINT_CALIBRATION_SUMMARY_DETAIL 1 456 #define PRINT_CALIBRATION_SUMMARY_FASTK_CHECK 0 457 458 #if 1 //(FOR_DV_SIMULATION_USED==0) 459 #define ETT_PRINT_FORMAT // Apply for both preloader and ETT 460 #endif 461 462 //#define FOR_HQA_TEST_USED // HQA test used, to print result for easy report 463 //#define FOR_HQA_REPORT_USED 464 //Run Time Config 465 //#define DUMMY_READ_FOR_TRACKING 466 #define ZQCS_ENABLE_LP4 467 #ifndef ZQCS_ENABLE_LP4 468 #define ENABLE_SW_RUN_TIME_ZQ_WA 469 #endif 470 471 //============================ For Future DVT Definition ================================= 472 473 #define ENABLE_DVFS_CDC_SYNCHRONIZER_OPTION 1 474 #define ENABLE_BLOCK_APHY_CLOCK_DFS_OPTION 1 475 #define ENABLE_REMOVE_MCK8X_UNCERT_LOWPOWER_OPTION 1 476 #define ENABLE_REMOVE_MCK8X_UNCERT_DFS_OPTION 1 477 #define RDSEL_TRACKING_EN 0 // @Darren, for SHU0 only (DDR3733 or DDR4266) 478 #define ENABLE_DFS_SSC_WA 0 479 #define ENABLE_DDR800_OPEN_LOOP_MODE_OPTION 1 480 481 //============================================================================= 482 //#define DDR_BASE 0x40000000ULL //for DV sim and ett_test.c 483 /***********************************************************************/ 484 /* Defines */ 485 /***********************************************************************/ 486 #define CBT_LOW_FREQ 0 487 #define CBT_HIGH_FREQ 1 488 #define CBT_UNKNOWN_FREQ 0xFF 489 490 491 #if !__ETT__ 492 // Preloader: using config CFG_DRAM_CALIB_OPTIMIZATION to identify 493 #if (FOR_DV_SIMULATION_USED==0) && !defined(SLT) 494 // Preloader: using config CFG_DRAM_CALIB_OPTIMIZATION to identify 495 #define SUPPORT_SAVE_TIME_FOR_CALIBRATION 1 496 497 #if defined(FORCE_FASTK) && !SUPPORT_SAVE_TIME_FOR_CALIBRATION 498 #error "FORCE_FASTK needs enable SUPPORT_SAVE_TIME_FOR_CALIBRATION!" 499 #endif 500 501 #else 502 // DV simulation, use full calibration flow 503 #define SUPPORT_SAVE_TIME_FOR_CALIBRATION 0 504 #endif 505 #define EMMC_READY 1 506 #define BYPASS_VREF_CAL (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 507 #define BYPASS_CBT (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 508 #define BYPASS_DATLAT (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 509 #define BYPASS_WRITELEVELING (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 510 #define BYPASS_RDDQC (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 511 #define BYPASS_RXWINDOW (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 512 #define BYPASS_TXWINDOW (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 513 #define BYPASS_TXOE (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 514 #define BYPASS_GatingCal (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 515 #define BYPASS_CA_PER_BIT_DELAY_CELL (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 516 //#define BYPASS_TX_PER_BIT_DELAY_CELL (SUPPORT_SAVE_TIME_FOR_CALIBRATION & EMMC_READY) 517 #else 518 // ETT 519 #define SUPPORT_SAVE_TIME_FOR_CALIBRATION 0 520 #define EMMC_READY 0 521 #define BYPASS_VREF_CAL 1 522 #define BYPASS_CBT 1 523 #define BYPASS_DATLAT 1 524 #define BYPASS_WRITELEVELING 1 525 #define BYPASS_RDDQC 1 526 #define BYPASS_RXWINDOW 1 527 #define BYPASS_TXWINDOW 1 528 #define BYPASS_TXOE 1 529 #define BYPASS_GatingCal 1 530 #define BYPASS_CA_PER_BIT_DELAY_CELL CA_PER_BIT_DELAY_CELL 531 //#define BYPASS_TX_PER_BIT_DELAY_CELL 0 532 #endif 533 534 #define ENABLE_PINMUX_FOR_RANK_SWAP 0 535 536 //======================== FIRST_BRING_UP Init Definition ===================== 537 #ifdef FIRST_BRING_UP 538 539 //#define USE_CLK26M 540 541 #undef TDQSCK_PRECALCULATION_FOR_DVFS 542 #define TDQSCK_PRECALCULATION_FOR_DVFS 0//DQS pre-calculation 543 544 #undef CHANNEL_NUM 545 #define CHANNEL_NUM 2 546 547 #undef ENABLE_DUTY_SCAN_V2 548 #define ENABLE_DUTY_SCAN_V2 0 549 550 #undef ENABLE_DRS 551 #define ENABLE_DRS 0 552 553 #undef ENABLE_CA_TRAINING 554 #define ENABLE_CA_TRAINING 1 555 #undef ENABLE_WRITE_LEVELING 556 #define ENABLE_WRITE_LEVELING 1 557 #undef ENABLE_PHY_RX_INPUT_OFFSET 558 #define ENABLE_PHY_RX_INPUT_OFFSET 0 559 560 //#undef REDUCE_LOG_FOR_PRELOADER 561 //#define REDUCE_LOG_FOR_PRELOADER 0 562 563 #undef REDUCE_CALIBRATION_OLYMPUS_ONLY 564 #define REDUCE_CALIBRATION_OLYMPUS_ONLY 0 565 566 #undef APPLY_LOWPOWER_GOLDEN_SETTINGS 567 #define APPLY_LOWPOWER_GOLDEN_SETTINGS 0 //Should open APPLY_LOWPOWER_GOLDEN_SETTINGS before SB + 3 568 569 //#undef SPM_CONTROL_AFTERK //Should open SPM_CONTROL_AFTERK before SB + 3 570 571 #undef TX_K_DQM_WITH_WDBI 572 #define TX_K_DQM_WITH_WDBI 0 573 574 #undef ENABLE_EYESCAN_GRAPH 575 #define ENABLE_EYESCAN_GRAPH 0 576 577 #undef PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER 578 #define PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER 0 579 580 #undef ENABLE_TX_TRACKING 581 #undef ENABLE_SW_TX_TRACKING 582 #define ENABLE_TX_TRACKING 0 583 #define ENABLE_SW_TX_TRACKING 0 584 585 #undef ENABLE_RX_TRACKING 586 #define ENABLE_RX_TRACKING 0 587 588 #undef ENABLE_PER_BANK_REFRESH 589 #define ENABLE_PER_BANK_REFRESH 1 590 591 #undef CMD_PICG_NEW_MODE 592 #define CMD_PICG_NEW_MODE 0 593 594 #undef XRTWTW_NEW_CROSS_RK_MODE 595 #define XRTWTW_NEW_CROSS_RK_MODE 1 596 #undef XRTRTR_NEW_CROSS_RK_MODE 597 #define XRTRTR_NEW_CROSS_RK_MODE 1 598 599 #undef ENABLE_DVFS_BYPASS_MR13_FSP 600 #define ENABLE_DVFS_BYPASS_MR13_FSP 0 601 602 #undef HW_GATING 603 #undef DUMMY_READ_FOR_TRACKING 604 #undef ZQCS_ENABLE_LP4 605 //#define ZQCS_ENABLE_LP4 606 607 #undef TEMP_SENSOR_ENABLE 608 //#define TEMP_SENSOR_ENABLE 609 #undef IMPEDANCE_TRACKING_ENABLE 610 //#define IMPEDANCE_TRACKING_ENABLE 611 #undef ENABLE_SW_RUN_TIME_ZQ_WA 612 613 //#undef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY 614 615 #undef APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST 616 #define APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST 0 617 618 #undef DFS_NOQUEUE_FLUSH_WA 619 #define DFS_NOQUEUE_FLUSH_WA 0 620 621 622 #undef TX_PICG_NEW_MODE 623 #undef RX_PICG_NEW_MODE 624 #undef ENABLE_RX_DCM_DPHY 625 #define ENABLE_RX_DCM_DPHY 1 //Set 0 will lead DCM on/off error 626 #if APPLY_LOWPOWER_GOLDEN_SETTINGS 627 #define TX_PICG_NEW_MODE 1 628 #define RX_PICG_NEW_MODE 1 629 #else 630 #define TX_PICG_NEW_MODE 0 631 #define RX_PICG_NEW_MODE 0 632 #endif 633 634 635 #if 0 636 #undef XRTW2W_PERFORM_ENHANCE_TX 637 #undef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY 638 #ifdef XRTR2W_PERFORM_ENHANCE_RODTEN 639 #undef XRTR2W_PERFORM_ENHANCE_RODTEN //conflict with ENABLE_RODT_TRACKING, LP4 support only 640 #endif 641 #endif 642 #endif //FIRST_BRING_UP 643 644 #define CFG_DRAM_SAVE_FOR_RUNTIME_SHMOO 0 645 #define RUNTIME_SHMOO_RELEATED_FUNCTION CFG_DRAM_SAVE_FOR_RUNTIME_SHMOO 646 #define RUNTIME_SHMOO_RG_BACKUP_NUM (100) 647 #define RUNTIME_SHMOO_TX 0 //TX RX can't be opened simultaneously 648 #define RUNTIME_SHMOO_RX 0 649 #if RUNTIME_SHMOO_RELEATED_FUNCTION //if enable rshmoo, close TX OE calibration 650 #undef TX_OE_EXTEND 651 #define TX_OE_EXTEND 1 652 #undef TX_DQ_OE_SHIFT_LP4 653 #define TX_DQ_OE_SHIFT_LP4 4 654 #undef TX_OE_CALIBATION 655 #define TX_OE_CALIBATION (!TX_OE_EXTEND) 656 #undef ENABLE_RX_TRACKING_LP4 657 #define ENABLE_RX_TRACKING_LP4 0 658 #undef ENABLE_TX_TRACKING 659 #undef ENABLE_SW_TX_TRACKING 660 #define ENABLE_TX_TRACKING 0 661 #define ENABLE_SW_TX_TRACKING 0 662 #define RUNTIME_SHMOO_FAST_K 1 663 #define RUNTIME_SHMOO_TEST_CHANNEL 0 // 0: CHA, 1: CHB 664 #define RUNTIME_SHMOO_TEST_RANK 0 // 0: RK0, 1: RK1 665 #define RUNTIME_SHMOO_TEST_BYTE 0 // 0: Byte0, 1: Byte1 666 #define RUNTIME_SHMOO_TEST_PI_DELAY_START 0 // 0~63 667 #define RUNTIME_SHMOO_TEST_PI_DELAY_END 63 // 0~63 668 #define RUNTIME_SHMOO_TEST_PI_DELAY_STEP 1 669 #define RUNTIME_SHMOO_RX_VREF_RANGE_END 127 //La_fite: 63 670 #define RUNTIME_SHMOO_RX_TEST_MARGIN 2 //for RX Delay (start:first_pass-margin, end:last_pass +margin) 671 #define RUNTIME_SHMOO_TEST_VREF_START 0 // 0~81 : 0~50 is range 0, 51~81 is range 1 672 #define RUNTIME_SHMOO_TEST_VREF_END 81 // 0~81 : 0~50 is range 0, 51~81 is range 1 673 #define RUNTIME_SHMOO_TEST_VREF_STEP 1 674 #endif 675 typedef enum 676 { 677 CLK_MUX_208M = 0, 678 CLK_MUX_104M, 679 CLK_MUX_52M, 680 } CLK_MUX_T; 681 682 typedef enum 683 { 684 BEF_DFS_MODE = 0, 685 AFT_DFS_MODE, 686 CHG_CLK_MODE, 687 } DFS_DBG_T; 688 689 typedef enum 690 { 691 SHUFFLE_HW_MODE = 0, 692 SPM_DEBUG_MODE, 693 RG_DEBUG_MODE, 694 } DFS_IP_CLOCK_T; 695 696 typedef enum 697 { 698 DutyScan_Calibration_K_CLK= 0, 699 DutyScan_Calibration_K_DQS, 700 DutyScan_Calibration_K_DQ, 701 DutyScan_Calibration_K_DQM, 702 DutyScan_Calibration_K_WCK 703 } DUTYSCAN_CALIBRATION_FLOW_K_T; 704 705 typedef enum 706 { 707 DQS_8PH_DEGREE_0 = 0, 708 DQS_8PH_DEGREE_180, 709 DQS_8PH_DEGREE_45, 710 DQS_8PH_DEGREE_MAX, 711 } DQS_8_PHASE_T; 712 713 typedef enum 714 { 715 DRVP = 0, 716 DRVN, 717 ODTP, 718 ODTN, 719 IMP_DRV_MAX 720 } DRAM_IMP_DRV_T; 721 722 typedef enum 723 { 724 IMP_LOW_FREQ = 0, 725 IMP_HIGH_FREQ, 726 IMP_NT_ODTN, // Samsung support only for LP4X 727 IMP_VREF_MAX 728 } DRAMC_IMP_T; 729 730 typedef enum 731 { 732 GET_MDL_USED = 0, 733 NORMAL_USED, 734 SLT_USED 735 } DRAM_INIT_USED_T; 736 737 typedef enum 738 { 739 PATTERN_RDDQC, 740 PATTERN_TEST_ENGINE, 741 } RX_PATTERN_OPTION_T; 742 743 typedef enum 744 { 745 DRAM_OK = 0, // OK 746 DRAM_FAIL, // FAIL 747 DRAM_FAST_K, 748 DRAM_NO_K, 749 } DRAM_STATUS_T; // DRAM status type 750 751 typedef enum 752 { 753 VREF_RANGE_0= 0, 754 VREF_RANGE_1, 755 VREF_RANGE_MAX 756 }DRAM_VREF_RANGE_T; 757 #define VREF_VOLTAGE_TABLE_NUM_LP4 51 758 #define VREF_VOLTAGE_TABLE_NUM_LP5 128 759 760 typedef enum 761 { 762 CKE_FIXOFF = 0, 763 CKE_FIXON, 764 CKE_DYNAMIC //After CKE FIX on/off, CKE should be returned to dynamic (control by HW) 765 } CKE_FIX_OPTION; 766 767 typedef enum 768 { 769 CKE_WRITE_TO_ONE_CHANNEL = 0, //just need to write CKE FIX register to current channel 770 CKE_WRITE_TO_ALL_CHANNEL, //need to write CKE FIX register to all channel 771 CKE_WRITE_TO_ALL_RANK 772 } CKE_FIX_CHANNEL; 773 774 typedef enum 775 { 776 LP5_DDR6400 = 0, 777 LP5_DDR6000, 778 LP5_DDR5500, 779 LP5_DDR4800, 780 LP5_DDR4266, 781 LP5_DDR3733, 782 LP5_DDR3200, 783 LP5_DDR2400, 784 LP5_DDR1600, 785 LP5_DDR1200, 786 LP5_DDR800, 787 788 LP4_DDR4266, 789 LP4_DDR3733, 790 LP4_DDR3200, 791 LP4_DDR2667, 792 LP4_DDR2400, 793 LP4_DDR2280, 794 LP4_DDR1866, 795 LP4_DDR1600, 796 LP4_DDR1200, 797 LP4_DDR800, 798 LP4_DDR400, 799 800 PLL_FREQ_SEL_MAX 801 } DRAM_PLL_FREQ_SEL_T; // DRAM DFS type 802 803 typedef enum 804 { 805 MCK_TO_4UI_SHIFT = 2, 806 MCK_TO_8UI_SHIFT = 3, 807 MCK_TO_16UI_SHIFT = 4 808 } MCK_TO_UI_SHIFT_T; 809 810 typedef enum 811 { 812 AUTOK_CA, 813 AUTOK_CS, 814 AUTOK_DQS 815 } ATUOK_MODE_T; 816 817 typedef enum 818 { 819 AUTOK_RESPI_1 = 0, 820 AUTOK_RESPI_2 = 1, 821 AUTOK_RESPI_4 = 2, 822 AUTOK_RESPI_8 = 3 823 } AUTOK_PI_RESOLUTION; 824 825 typedef enum 826 { 827 DRAM_DFS_REG_SHU0 = 0, 828 DRAM_DFS_REG_SHU1, 829 DRAM_DFS_REG_MAX 830 } DRAM_DFS_REG_SHU_T; 831 832 typedef enum 833 { 834 SRAM_SHU0 = 0, 835 SRAM_SHU1, 836 SRAM_SHU2, 837 SRAM_SHU3, 838 SRAM_SHU4, 839 SRAM_SHU5, 840 SRAM_SHU6, 841 DRAM_DFS_SRAM_MAX 842 } DRAM_DFS_SRAM_SHU_T; // DRAM SRAM RG type 843 844 typedef enum 845 { 846 SHUFFLE_RG = 0, 847 NONSHUFFLE_RG, 848 BOTH_SHU_NONSHU_RG, 849 } RG_SHU_TYPE_T; // RG SHUFFLE type 850 typedef enum 851 { 852 DIV16_MODE = 0, 853 DIV8_MODE, 854 DIV4_MODE, 855 UNKNOWN_MODE, 856 } DIV_MODE_T; 857 858 typedef enum 859 { 860 DUTY_DEFAULT = 0, 861 DUTY_NEED_K, 862 DUTY_LAST_K 863 } DUTY_CALIBRATION_T; 864 865 866 typedef enum 867 { 868 VREF_CALI_OFF = 0, 869 VREF_CALI_ON, 870 } VREF_CALIBRATION_ENABLE_T; 871 872 typedef enum 873 { 874 DDR800_CLOSE_LOOP = 0, 875 OPEN_LOOP_MODE, 876 SEMI_OPEN_LOOP_MODE, 877 CLOSE_LOOP_MODE, 878 } DDR800_MODE_T; 879 880 typedef enum 881 { 882 DRAM_CALIBRATION_SW_IMPEDANCE= 0, 883 DRAM_CALIBRATION_DUTY_SCAN, 884 DRAM_CALIBRATION_ZQ, 885 DRAM_CALIBRATION_JITTER_METER, 886 DRAM_CALIBRATION_CA_TRAIN , 887 DRAM_CALIBRATION_WRITE_LEVEL, 888 DRAM_CALIBRATION_GATING, 889 DRAM_CALIBRATION_RX_RDDQC, 890 DRAM_CALIBRATION_TX_PERBIT, 891 DRAM_CALIBRATION_DATLAT, 892 DRAM_CALIBRATION_RX_PERBIT, 893 DRAM_CALIBRATION_TX_OE, 894 DRAM_CALIBRATION_MAX 895 } DRAM_CALIBRATION_STATUS_T; 896 897 typedef struct _DRAM_DFS_FREQUENCY_TABLE_T 898 { 899 DRAM_PLL_FREQ_SEL_T freq_sel; 900 DIV_MODE_T divmode; 901 DRAM_DFS_SRAM_SHU_T shuffleIdx; 902 DUTY_CALIBRATION_T duty_calibration_mode; 903 VREF_CALIBRATION_ENABLE_T vref_calibartion_enable; // CBT/RX/TX vref calibration enable or not 904 DDR800_MODE_T ddr_loop_mode; 905 } DRAM_DFS_FREQUENCY_TABLE_T; 906 907 typedef enum 908 { 909 CHANNEL_SINGLE = 1, 910 CHANNEL_DUAL, 911 #if (CHANNEL_NUM > 2) 912 CHANNEL_THIRD, 913 CHANNEL_FOURTH 914 #endif 915 } DRAM_CHANNEL_NUMBER_T; 916 917 918 typedef enum 919 { 920 RANK_SINGLE = 1, 921 RANK_DUAL 922 } DRAM_RANK_NUMBER_T; 923 924 925 typedef enum 926 { 927 TYPE_DDR1 = 1, 928 TYPE_LPDDR2, 929 TYPE_LPDDR3, 930 TYPE_PCDDR3, 931 TYPE_LPDDR4, 932 TYPE_LPDDR4X, 933 TYPE_LPDDR4P, 934 TYPE_LPDDR5 935 } DRAM_DRAM_TYPE_T; 936 937 typedef enum 938 { 939 PINMUX_DSC = 0, 940 PINMUX_LPBK, 941 PINMUX_EMCP, 942 PINMUX_MAX 943 } DRAM_PINMUX; 944 945 /* For faster switching between term and un-term operation 946 * FSP_0: For un-terminated freq. 947 * FSP_1: For terminated freq. 948 */ 949 typedef enum 950 { 951 FSP_0 = 0, 952 FSP_1, 953 FSP_2, 954 FSP_MAX 955 } DRAM_FAST_SWITH_POINT_T; 956 957 typedef struct 958 { 959 u8 pat_v[8]; 960 u8 pat_a[8]; 961 u8 pat_dmv; 962 u8 pat_dma; 963 u8 pat_cs0; 964 u8 pat_cs1; 965 u8 ca_golden_sel; 966 u8 invert_num; 967 } new_cbt_pat_cfg_t; 968 969 typedef enum 970 { 971 TRAINING_MODE1 = 0, 972 TRAINING_MODE2 973 } lp5_training_mode_t; 974 975 typedef enum 976 { 977 CBT_PHASE_RISING = 0, 978 CBT_PHASE_FALLING 979 } lp5_cbt_phase_t; 980 981 /* 982 * External CBT mode enum 983 * Due to MDL structure compatibility (single field for dram CBT mode), 984 * the below enum is used in preloader to differentiate between dram cbt modes 985 */ 986 typedef enum 987 { 988 CBT_R0_R1_NORMAL = 0, // Normal mode 989 CBT_R0_R1_BYTE, // Byte mode 990 CBT_R0_NORMAL_R1_BYTE, // Mixed mode R0: Normal R1: Byte 991 CBT_R0_BYTE_R1_NORMAL // Mixed mode R0: Byte R1: Normal 992 } DRAM_CBT_MODE_EXTERN_T; 993 994 typedef enum 995 { 996 ODT_OFF = 0, 997 ODT_ON 998 } DRAM_ODT_MODE_T; 999 1000 typedef enum 1001 { 1002 DBI_OFF = 0, 1003 DBI_ON 1004 } DRAM_DBI_MODE_T; 1005 1006 typedef enum 1007 { 1008 DATA_WIDTH_16BIT = 16, 1009 DATA_WIDTH_32BIT = 32 1010 } DRAM_DATA_WIDTH_T; 1011 1012 typedef enum 1013 { 1014 TE_OP_WRITE_READ_CHECK = 0, 1015 TE_OP_READ_CHECK 1016 } DRAM_TE_OP_T; 1017 1018 typedef enum 1019 { 1020 TEST_ISI_PATTERN = 0, //don't change 1021 TEST_AUDIO_PATTERN = 1, //don't change 1022 TEST_XTALK_PATTERN = 2, //don't change 1023 TEST_WORST_SI_PATTERN, 1024 TEST_TA1_SIMPLE, 1025 TEST_TESTPAT4, 1026 TEST_TESTPAT4_3, 1027 TEST_MIX_PATTERN, 1028 TEST_DMA, 1029 TEST_SSOXTALK_PATTERN, 1030 } DRAM_TEST_PATTERN_T; 1031 1032 typedef enum 1033 { 1034 TE_NO_UI_SHIFT = 0, 1035 TE_UI_SHIFT 1036 } DRAM_TE_UI_SHIFT_T; 1037 1038 typedef enum 1039 { 1040 TX_DQ_DQS_MOVE_DQ_ONLY = 0, 1041 TX_DQ_DQS_MOVE_DQM_ONLY, 1042 TX_DQ_DQS_MOVE_DQ_DQM 1043 } DRAM_TX_PER_BIT_CALIBRATION_TYTE_T; 1044 1045 typedef enum 1046 { 1047 TX_DQM_WINDOW_SPEC_IN = 0xfe, 1048 TX_DQM_WINDOW_SPEC_OUT = 0xff 1049 } DRAM_TX_PER_BIT_DQM_WINDOW_RESULT_TYPE_T; 1050 1051 // enum for CKE toggle mode (toggle both ranks 1. at the same time (CKE_RANK_DEPENDENT) 2. individually (CKE_RANK_INDEPENDENT)) 1052 typedef enum 1053 { 1054 CKE_RANK_INDEPENDENT = 0, 1055 CKE_RANK_DEPENDENT 1056 } CKE_CTRL_MODE_T; 1057 1058 typedef enum 1059 { 1060 TA2_RKSEL_XRT = 3, 1061 TA2_RKSEL_HW = 4, 1062 } TA2_RKSEL_TYPE_T; 1063 1064 typedef enum 1065 { 1066 TA2_PAT_SWITCH_OFF = 0, 1067 TA2_PAT_SWITCH_ON, 1068 } TA2_PAT_SWITCH_TYPE_T; 1069 1070 typedef enum 1071 { 1072 PHYPLL_MODE = 0, 1073 CLRPLL_MODE, 1074 } PLL_MODE_T; 1075 1076 typedef enum 1077 { 1078 RUNTIME_SWCMD_CAS_FS = 0, 1079 RUNTIME_SWCMD_CAS_OFF, 1080 RUNTIME_SWCMD_WCK2DQI_START, 1081 RUNTIME_SWCMD_WCK2DQO_START, 1082 RUNTIME_SWCMD_MRW, 1083 RUNTIME_SWCMD_ZQCAL_START, 1084 RUNTIME_SWCMD_ZQCAL_LATCH 1085 } RUNTIME_SWCMD_SEL_T; 1086 1087 typedef enum 1088 { 1089 PI_BASED, 1090 DLY_BASED 1091 } WLEV_DELAY_BASED_T; 1092 1093 enum lpddr5_rpre_mode { 1094 LPDDR5_RPRE_4S_0T = 0, 1095 LPDDR5_RPRE_2S_2T, 1096 LPDDR5_RPRE_0S_4T, 1097 LPDDR5_RPRE_XS_4T, /* X = 2~4tWCK */ 1098 }; 1099 1100 enum rxdqs_autok_burst_len { 1101 RXDQS_BURST_LEN_8 = 0, 1102 RXDQS_BURST_LEN_16, 1103 RXDQS_BURST_LEN_32, 1104 }; 1105 1106 typedef enum 1107 { 1108 EYESCAN_FLAG_DISABLE= 0, 1109 EYESCAN_FLAG_ENABLE, 1110 EYESCAN_FLAG_ENABLE_BUT_NORMAL_K, 1111 } EYESCAN_FLAG_TYPE_T; 1112 1113 #ifdef FOR_HQA_REPORT_USED 1114 typedef enum 1115 { 1116 HQA_REPORT_FORMAT0 = 0, 1117 HQA_REPORT_FORMAT0_1, 1118 HQA_REPORT_FORMAT0_2, 1119 HQA_REPORT_FORMAT1, 1120 HQA_REPORT_FORMAT2, 1121 HQA_REPORT_FORMAT2_1, 1122 HQA_REPORT_FORMAT3, 1123 HQA_REPORT_FORMAT4, 1124 HQA_REPORT_FORMAT5, 1125 HQA_REPORT_FORMAT6 1126 } HQA_REPORT_FORMAT_T; 1127 #endif 1128 1129 #if SUPPORT_SAVE_TIME_FOR_CALIBRATION 1130 #if RUNTIME_SHMOO_RELEATED_FUNCTION 1131 typedef struct _RUNTIME_SHMOO_SAVE_PARAMETER_T 1132 { 1133 U8 flag; 1134 U16 TX_PI_delay; 1135 U16 TX_Original_PI_delay; 1136 U16 TX_DQM_PI_delay; 1137 U16 TX_Original_DQM_PI_delay; 1138 S16 RX_delay[8]; 1139 S16 RX_Original_delay; 1140 U8 TX_Vref_Range; 1141 U8 TX_Vref_Value; 1142 U8 TX_Channel; 1143 U8 TX_Rank; 1144 U8 TX_Byte; 1145 U8 Scan_Direction; 1146 } RUNTIME_SHMOO_SAVE_PARAMETER_T; 1147 #endif 1148 1149 typedef struct _SAVE_TIME_FOR_CALIBRATION_T 1150 { 1151 //U8 femmc_Ready; 1152 1153 DRAM_RANK_NUMBER_T support_rank_num; 1154 1155 U16 u2num_dlycell_perT; 1156 U16 u2DelayCellTimex100; 1157 1158 // CLK & DQS duty 1159 S8 s1ClockDuty_clk_delay_cell[CHANNEL_NUM][RANK_MAX]; 1160 S8 s1DQSDuty_clk_delay_cell[CHANNEL_NUM][DQS_NUMBER_LP4]; 1161 S8 s1WCKDuty_clk_delay_cell[CHANNEL_NUM][DQS_NUMBER_LP4]; 1162 #if APPLY_DQDQM_DUTY_CALIBRATION 1163 S8 s1DQDuty_clk_delay_cell[CHANNEL_NUM][DQS_NUMBER_LP4]; 1164 S8 s1DQMDuty_clk_delay_cell[CHANNEL_NUM][DQS_NUMBER_LP4]; 1165 #endif 1166 // CBT 1167 U8 u1CBTVref_Save[CHANNEL_NUM][RANK_MAX]; 1168 S8 s1CBTCmdDelay_Save[CHANNEL_NUM][RANK_MAX]; 1169 U8 u1CBTCsDelay_Save[CHANNEL_NUM][RANK_MAX]; 1170 #if CA_PER_BIT_DELAY_CELL 1171 U8 u1CBTCA_PerBit_DelayLine_Save[CHANNEL_NUM][RANK_MAX][DQS_BIT_NUMBER]; 1172 #endif 1173 1174 // Write leveling 1175 U8 u1WriteLeveling_bypass_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; //for bypass writeleveling 1176 1177 // Gating 1178 U8 u1Gating_MCK_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; 1179 U8 u1Gating_UI_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; 1180 U8 u1Gating_PI_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; 1181 U8 u1Gating_pass_count_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; 1182 1183 // TX perbit 1184 U8 u1TxWindowPerbitVref_Save[CHANNEL_NUM][RANK_MAX]; 1185 U16 u1TxCenter_min_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; 1186 U16 u1TxCenter_max_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; 1187 U16 u1Txwin_center_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4]; 1188 1189 // Datlat 1190 U8 u1RxDatlat_Save[CHANNEL_NUM][RANK_MAX]; 1191 1192 // RX perbit 1193 U8 u1RxWinPerbitVref_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; 1194 U16 u1RxWinPerbit_DQS[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; 1195 U16 u1RxWinPerbit_DQM[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; 1196 U16 u1RxWinPerbit_DQ[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4]; 1197 1198 //TX OE 1199 U8 u1TX_OE_DQ_MCK[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; 1200 U8 u1TX_OE_DQ_UI[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4]; 1201 1202 1203 #if RUNTIME_SHMOO_RELEATED_FUNCTION 1204 S16 u1RxWinPerbitDQ_firsbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4]; //for bypass rxwindow 1205 U8 u1RxWinPerbitDQ_lastbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4]; //for bypass rxwindow 1206 U8 u1SwImpedanceResule[2][4]; 1207 U32 u4RG_Backup[CHANNEL_NUM][RUNTIME_SHMOO_RG_BACKUP_NUM]; 1208 1209 RUNTIME_SHMOO_SAVE_PARAMETER_T Runtime_Shmoo_para; 1210 #endif 1211 }SAVE_TIME_FOR_CALIBRATION_T; 1212 #endif // SUPPORT_SAVE_TIME_FOR_CALIBRATION 1213 1214 #if MRW_CHECK_ONLY 1215 #define MR_NUM 64 1216 extern U16 u2MRRecord[CHANNEL_NUM][RANK_MAX][FSP_MAX][MR_NUM]; 1217 #endif 1218 1219 //////////////////////////// 1220 typedef struct _DRAMC_CTX_T 1221 { 1222 DRAM_CHANNEL_NUMBER_T support_channel_num; 1223 DRAM_CHANNEL_T channel; 1224 DRAM_RANK_NUMBER_T support_rank_num; 1225 DRAM_RANK_T rank; 1226 DRAM_PLL_FREQ_SEL_T freq_sel; 1227 DRAM_DFS_SHUFFLE_TYPE_T shu_type; 1228 DRAM_DRAM_TYPE_T dram_type; 1229 DRAM_FAST_SWITH_POINT_T dram_fsp; // only for LP4, uesless in LP3 1230 DRAM_ODT_MODE_T odt_onoff;/// only for LP4, uesless in LP3 1231 DRAM_CBT_MODE_T dram_cbt_mode[RANK_MAX]; //only for LP4, useless in LP3 1232 DRAM_DBI_MODE_T DBI_R_onoff[FSP_MAX]; // only for LP4, uesless in LP3 1233 DRAM_DBI_MODE_T DBI_W_onoff[FSP_MAX]; // only for LP4, uesless in LP3 1234 DRAM_DATA_WIDTH_T data_width; 1235 U32 test2_1; 1236 U32 test2_2; 1237 DRAM_TEST_PATTERN_T test_pattern; 1238 U16 frequency; 1239 U16 freqGroup; /* Used to support freq's that are not in ACTimingTable */ 1240 U16 vendor_id; 1241 U16 revision_id; 1242 U16 density; 1243 U64 ranksize[RANK_MAX]; 1244 U16 u2num_dlycell_perT; 1245 U16 u2DelayCellTimex100; 1246 //U8 enable_cbt_scan_vref; 1247 //U8 enable_rx_scan_vref; 1248 //U8 enable_tx_scan_vref; 1249 1250 #if PRINT_CALIBRATION_SUMMARY 1251 U32 aru4CalResultFlag[CHANNEL_NUM][RANK_MAX];// record the calibration is fail or success, 0:success, 1: fail 1252 U32 aru4CalExecuteFlag[CHANNEL_NUM][RANK_MAX]; // record the calibration is execute or not, 0:no operate, 1: done 1253 U32 SWImpCalResult; 1254 U32 SWImpCalExecute; 1255 #if PRINT_CALIBRATION_SUMMARY_FASTK_CHECK 1256 U32 FastKResultFlag[2][RANK_MAX];// record the calibration is fail or success, 0:success, 1: fail 1257 U32 FastKExecuteFlag[2][RANK_MAX]; // record the calibration is execute or not, 0:no operate, 1: done 1258 #endif 1259 #endif 1260 1261 bool isWLevInitShift[CHANNEL_NUM]; 1262 1263 #if SUPPORT_SAVE_TIME_FOR_CALIBRATION 1264 U8 femmc_Ready; 1265 // Calibration or not 1266 U8 Bypass_TXWINDOW; 1267 U8 Bypass_RXWINDOW; 1268 U8 Bypass_RDDQC; 1269 SAVE_TIME_FOR_CALIBRATION_T *pSavetimeData; 1270 #endif 1271 DRAM_DFS_FREQUENCY_TABLE_T *pDFSTable; 1272 DRAM_DFS_REG_SHU_T ShuRGAccessIdx; 1273 lp5_training_mode_t lp5_training_mode; //only for LP5 1274 lp5_cbt_phase_t lp5_cbt_phase; //only for LP5 1275 u8 new_cbt_mode; 1276 U8 u1PLLMode; 1277 DRAM_DBI_MODE_T curDBIState; 1278 DRAM_FAST_SWITH_POINT_T support_fsp_num; 1279 DRAM_PINMUX DRAMPinmux; 1280 U8 u110GBEn[RANK_MAX]; 1281 bool isMaxFreq4266; 1282 } DRAMC_CTX_T; 1283 1284 typedef struct _DRAM_DVFS_TABLE_T 1285 { 1286 DRAM_PLL_FREQ_SEL_T freq_sel; 1287 DIV_MODE_T divmode; 1288 DRAM_DFS_SRAM_SHU_T shuffleIdx; 1289 U32 u4Vcore; 1290 } DRAM_DVFS_TABLE_T; 1291 1292 typedef struct _PASS_WIN_DATA_T 1293 { 1294 S16 first_pass; 1295 S16 last_pass; 1296 S16 win_center; 1297 U16 win_size; 1298 U16 best_dqdly; 1299 } PASS_WIN_DATA_T; 1300 1301 typedef struct _FINAL_WIN_DATA_T { 1302 unsigned char final_vref; 1303 signed int final_ca_clk; 1304 unsigned char final_range; 1305 } FINAL_WIN_DATA_T; 1306 1307 typedef struct _REG_TRANSFER 1308 { 1309 U32 u4Addr; 1310 U32 u4Fld; 1311 } REG_TRANSFER_T; 1312 1313 typedef struct _DRAM_INFO_BY_MRR_T 1314 { 1315 U16 u2MR5VendorID; 1316 U16 u2MR6RevisionID; 1317 U64 u8MR8RankSize[RANK_MAX]; 1318 } DRAM_INFO_BY_MRR_T; 1319 1320 #if __FLASH_TOOL_DA__ 1321 typedef struct _DEBUG_PIN_INF_FOR_FLASHTOOL_T 1322 { 1323 U16 TOTAL_ERR;//DQ,CA 1324 U16 IMP_ERR_FLAG; 1325 U8 WL_ERR_FLAG;//DQS 1326 U8 CA_ERR_FLAG[CHANNEL_MAX][RANK_MAX]; 1327 U8 CA_WIN_SIZE[CHANNEL_MAX][RANK_MAX][CATRAINING_NUM_LP4]; 1328 U8 DRAM_PIN_RX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; 1329 U8 DRAM_PIN_TX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; 1330 U8 DQ_RX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; 1331 U8 DQ_TX_ERR_FLAG[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; 1332 U16 DQ_RX_WIN_SIZE[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; 1333 U8 DQ_TX_WIN_SIZE[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; 1334 } DEBUG_PIN_INF_FOR_FLASHTOOL_T; 1335 #endif 1336 typedef struct _VCORE_DELAYCELL_T 1337 { 1338 U32 u2Vcore; 1339 U16 u2DelayCell; 1340 } VCORE_DELAYCELL_T; 1341 1342 typedef enum 1343 { 1344 DMA_PREPARE_DATA_ONLY, 1345 DMA_CHECK_DATA_ACCESS_ONLY_AND_NO_WAIT, 1346 DMA_CHECK_COMAPRE_RESULT_ONLY, 1347 DMA_CHECK_DATA_ACCESS_AND_COMPARE, 1348 } DRAM_DMA_CHECK_RESULT_T; 1349 1350 1351 //For new register access 1352 #define SHIFT_TO_CHB_ADDR ((U32)CHANNEL_B << POS_BANK_NUM) 1353 #if (CHANNEL_NUM > 2) 1354 #define SHIFT_TO_CHC_ADDR ((U32)CHANNEL_C << POS_BANK_NUM) 1355 #define SHIFT_TO_CHD_ADDR ((U32)CHANNEL_D << POS_BANK_NUM) 1356 #endif 1357 #define DRAMC_REG_ADDR(offset) ((p->channel << POS_BANK_NUM) + (offset)) 1358 #define SYS_REG_ADDR(offset) (offset) 1359 1360 // Different from Pi_calibration.c due to Base address 1361 //#define mcSET_DRAMC_REG_ADDR(offset) (DRAMC_BASE_ADDRESS | (p->channel << POS_BANK_NUM) | (offset)) 1362 #define mcSET_SYS_REG_ADDR(offset) (DRAMC_BASE_ADDRESS | (offset)) 1363 #define mcSET_DRAMC_NAO_REG_ADDR(offset) (DRAMC_NAO_BASE_ADDRESS | (offset)) 1364 #define mcSET_DRAMC_AO_REG_ADDR(offset) (DRAMC_AO_BASE_ADDRESS | (offset)) 1365 //#define mcSET_DRAMC_AO_REG_ADDR_CHC(offset) ((DRAMC_AO_BASE_ADDRESS + ((U32)CHANNEL_C << POS_BANK_NUM)) | (offset)) 1366 #define mcSET_DDRPHY_REG_ADDR(offset) (DDRPHY_BASE_ADDR | (offset)) 1367 #define mcSET_DDRPHY_REG_ADDR_CHA(offset) ((DDRPHY_BASE_ADDR + ((U32) CHANNEL_A << POS_BANK_NUM)) | (offset)) 1368 #define mcSET_DDRPHY_REG_ADDR_CHB(offset) ((DDRPHY_BASE_ADDR + SHIFT_TO_CHB_ADDR) | (offset)) 1369 //#define mcSET_DDRPHY_REG_ADDR_CHC(offset) ((DDRPHY_BASE_ADDR + ((U32) CHANNEL_C << POS_BANK_NUM)) | (offset)) 1370 //#define mcSET_DDRPHY_REG_ADDR_CHD(offset) ((DDRPHY_BASE_ADDR + ((U32) CHANNEL_D << POS_BANK_NUM)) | (offset)) 1371 1372 //-------------------------------------------------------------------------- 1373 // Dram Mode Registers Operation 1374 //-------------------------------------------------------------------------- 1375 #define MRWriteFldMulti(p, mr_idx, list, UpdateMode) \ 1376 { \ 1377 UINT16 upk = 1; \ 1378 U8 msk = (U8)(list); \ 1379 { \ 1380 upk = 0; \ 1381 DramcMRWriteFldMsk(p, mr_idx, (U8)(list), msk, UpdateMode); \ 1382 } \ 1383 } 1384 1385 #define JUST_TO_GLOBAL_VALUE (0) 1386 #define TO_MR (1) 1387 1388 // LP5 MR30 1389 #define MR30_DCAU (Fld(4, 4)) // DCA for upper byte 1390 #define MR30_DCAL (Fld(4, 0)) // DCA for lower byte 1391 1392 // LP5 MR26 1393 #define MR26_DCMU1 (Fld(1, 5)) 1394 #define MR26_DCMU0 (Fld(1, 4)) 1395 #define MR26_DCML1 (Fld(1, 3)) 1396 #define MR26_DCML0 (Fld(1, 2)) 1397 #define MR26_DCM_FLIP (Fld(1, 1)) 1398 #define MR26_DCM_START_STOP (Fld(1, 0)) 1399 1400 // LP4 MR13 1401 #define MR13_FSP_OP (Fld(1, 7)) 1402 #define MR13_FSP_WR (Fld(1, 6)) 1403 #define MR13_DMD (Fld(1, 5)) 1404 #define MR13_PRO (Fld(1, 4)) 1405 #define MR13_VRCG (Fld(1, 3)) 1406 #define MR13_CBT (Fld(1, 0)) 1407 1408 #define MR16_FSP_WR_SHIFT (0) 1409 #define MR16_FSP_OP_SHIFT (2) 1410 #define MR16_FSP_CBT (4) 1411 #define MR16_VRCG (6) 1412 #define MR16_CBT_PHASE (7) 1413 1414 /***********************************************************************/ 1415 /* External declarations */ 1416 /***********************************************************************/ 1417 EXTERN DRAMC_CTX_T *psCurrDramCtx; 1418 #if QT_GUI_Tool 1419 EXTERN FILE *fp_A60868; 1420 EXTERN FILE *fp_A60868_RGDump; 1421 #endif 1422 /***********************************************************************/ 1423 /* Public Functions */ 1424 /***********************************************************************/ 1425 // basic function 1426 EXTERN U8 u1IsLP4Family(DRAM_DRAM_TYPE_T dram_type); 1427 EXTERN int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_extern, DRAM_INFO_BY_MRR_T *DramInfo, U8 get_mdl_used); 1428 EXTERN void Dramc_DDR_Reserved_Mode_setting(void); 1429 EXTERN void Dramc_DDR_Reserved_Mode_AfterSR(void); 1430 EXTERN void Before_Init_DRAM_While_Reserve_Mode_fail(DRAM_DRAM_TYPE_T dram_type); 1431 EXTERN void ShuffleDfsToFSP1(DRAMC_CTX_T *p); 1432 1433 void vSetVcoreByFreq(DRAMC_CTX_T *p); 1434 U32 Get_WL_by_MR_LP4(U8 Version, U8 MR_WL_field_value); 1435 U8 u1MCK2UI_DivShift(DRAMC_CTX_T *p); 1436 void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, U8 shu_level); 1437 void UpdateDFSTbltoDDR3200(DRAMC_CTX_T *p); 1438 void DFSInitForCalibration(DRAMC_CTX_T *p); 1439 void mdl_setting(DRAMC_CTX_T *p); 1440 void MPLLInit(void); 1441 void DramcCKEDebounce(DRAMC_CTX_T *p); 1442 void DramcModifiedRefreshMode(DRAMC_CTX_T *p); 1443 void XRTRTR_SHU_Setting(DRAMC_CTX_T * p); 1444 void TXPICGSetting(DRAMC_CTX_T * p); 1445 void XRTWTW_SHU_Setting(DRAMC_CTX_T * p); 1446 DRAM_STATUS_T DramcDualRankRxdatlatCal(DRAMC_CTX_T *p); 1447 void vSwitchWriteDBISettings(DRAMC_CTX_T *p, U8 u1OnOff); 1448 void Get_RX_DelayCell(DRAMC_CTX_T *p); 1449 void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p); 1450 void EnableDFSNoQueueFlush(DRAMC_CTX_T *p); 1451 void EnableDramcPhyDCMNonShuffle(DRAMC_CTX_T *p, bool bEn); 1452 void Enable_TxWDQS(DRAMC_CTX_T *p, U32 u4DDRPhyShuOffset, U16 u2Freq); 1453 void Enable_ClkTxRxLatchEn(DRAMC_CTX_T *p, U32 u4DDRPhyShuOffset); 1454 void EnableRxDcmDPhy(DRAMC_CTX_T *p, U32 u4DDRPhyShuOffset, U16 u2Freq); 1455 void DramcRxdqsGatingPreProcess(DRAMC_CTX_T *p); 1456 void LP4_single_end_DRAMC_post_config(DRAMC_CTX_T *p, U8 LP4Y_EN); 1457 void vResetDelayChainBeforeCalibration(DRAMC_CTX_T *p); 1458 1459 unsigned int dramc_set_vcore_voltage(unsigned int vcore); 1460 unsigned int dramc_get_vcore_voltage(void); 1461 unsigned int dramc_set_vdram_voltage(unsigned int ddr_type, unsigned int vdram); 1462 unsigned int dramc_get_vdram_voltage(unsigned int ddr_type); 1463 unsigned int dramc_set_vddq_voltage(unsigned int ddr_type, unsigned int vddq); 1464 unsigned int dramc_get_vddq_voltage(unsigned int ddr_type); 1465 unsigned int dramc_set_vmddr_voltage(unsigned int vmddr); 1466 unsigned int dramc_get_vmddr_voltage(void); 1467 unsigned int dramc_set_vio18_voltage(unsigned int vio18); 1468 unsigned int dramc_get_vio18_voltage(void); 1469 1470 void sv_algorithm_assistance_LP4_4266(DRAMC_CTX_T *p); 1471 1472 void DramcNewDutyCalibration(DRAMC_CTX_T *p); 1473 unsigned int mt_get_dram_type_from_hw_trap(void); 1474 U8 Get_MDL_Used_Flag(void); 1475 void Set_MDL_Used_Flag(U8 value); 1476 void SetMr13VrcgToNormalOperation(DRAMC_CTX_T *p); 1477 void cbt_dfs_mr13_global(DRAMC_CTX_T *p, U8 freq); 1478 void TX_Path_Algorithm(DRAMC_CTX_T *p); 1479 DRAM_PLL_FREQ_SEL_T GetSelByFreq(DRAMC_CTX_T *p, U16 u2freq); 1480 U32 Get_RL_by_MR_LP4(U8 BYTE_MODE_EN,U8 DBI_EN, U8 MR_RL_field_value); 1481 1482 #endif // _PI_API_H 1483