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1 /*
2  * Copyright 2013 Advanced Micro Devices, Inc.
3  *
4  * SPDX-License-Identifier: MIT
5  */
6 
7 #include "si_pipe.h"
8 #include "util/u_memory.h"
9 #include "util/u_transfer.h"
10 #include "util/u_upload_mgr.h"
11 
12 #include <inttypes.h>
13 #include <stdio.h>
14 
si_cs_is_buffer_referenced(struct si_context * sctx,struct pb_buffer_lean * buf,unsigned usage)15 bool si_cs_is_buffer_referenced(struct si_context *sctx, struct pb_buffer_lean *buf,
16                                 unsigned usage)
17 {
18    return sctx->ws->cs_is_buffer_referenced(&sctx->gfx_cs, buf, usage);
19 }
20 
si_buffer_map(struct si_context * sctx,struct si_resource * resource,unsigned usage)21 void *si_buffer_map(struct si_context *sctx, struct si_resource *resource,
22                     unsigned usage)
23 {
24    return sctx->ws->buffer_map(sctx->ws, resource->buf, &sctx->gfx_cs, usage);
25 }
26 
si_init_resource_fields(struct si_screen * sscreen,struct si_resource * res,uint64_t size,unsigned alignment)27 void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, uint64_t size,
28                              unsigned alignment)
29 {
30    struct si_texture *tex = (struct si_texture *)res;
31 
32    res->bo_size = size;
33    res->bo_alignment_log2 = util_logbase2(alignment);
34    res->flags = 0;
35    res->texture_handle_allocated = false;
36    res->image_handle_allocated = false;
37 
38    switch (res->b.b.usage) {
39    case PIPE_USAGE_STREAM:
40       res->flags |= RADEON_FLAG_GTT_WC;
41       res->domains = RADEON_DOMAIN_GTT;
42       break;
43    case PIPE_USAGE_STAGING:
44       /* Transfers are likely to occur more often with these
45        * resources. */
46       res->domains = RADEON_DOMAIN_GTT;
47       break;
48    case PIPE_USAGE_DYNAMIC:
49    case PIPE_USAGE_DEFAULT:
50    case PIPE_USAGE_IMMUTABLE:
51    default:
52       /* Not listing GTT here improves performance in some
53        * apps. */
54       res->domains = RADEON_DOMAIN_VRAM;
55       res->flags |= RADEON_FLAG_GTT_WC;
56       break;
57    }
58 
59    if (res->b.b.target == PIPE_BUFFER && res->b.b.flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) {
60       /* Use GTT for all persistent mappings with older
61        * kernels, because they didn't always flush the HDP
62        * cache before CS execution.
63        *
64        * Write-combined CPU mappings are fine, the kernel
65        * ensures all CPU writes finish before the GPU
66        * executes a command stream.
67        *
68        * radeon doesn't have good BO move throttling, so put all
69        * persistent buffers into GTT to prevent VRAM CPU page faults.
70        */
71       if (!sscreen->info.is_amdgpu)
72          res->domains = RADEON_DOMAIN_GTT;
73    }
74 
75    /* Tiled textures are unmappable. Always put them in VRAM. */
76    if ((res->b.b.target != PIPE_BUFFER && !tex->surface.is_linear) ||
77        res->b.b.flags & PIPE_RESOURCE_FLAG_UNMAPPABLE) {
78       res->domains = RADEON_DOMAIN_VRAM;
79       res->flags |= RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_GTT_WC;
80    }
81 
82    /* Displayable and shareable surfaces are not suballocated. */
83    if (res->b.b.bind & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT))
84       res->flags |= RADEON_FLAG_NO_SUBALLOC; /* shareable */
85    else
86       res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
87 
88    /* PIPE_BIND_CUSTOM is used by si_vid_create_buffer which wants
89     * non-suballocated buffers.
90     */
91    if (res->b.b.bind & PIPE_BIND_CUSTOM)
92       res->flags |= RADEON_FLAG_NO_SUBALLOC;
93 
94    if (res->b.b.bind & PIPE_BIND_PROTECTED ||
95        /* Force scanout/depth/stencil buffer allocation to be encrypted */
96        (sscreen->debug_flags & DBG(TMZ) &&
97         res->b.b.bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)))
98       res->flags |= RADEON_FLAG_ENCRYPTED;
99 
100    if (res->b.b.flags & PIPE_RESOURCE_FLAG_ENCRYPTED)
101       res->flags |= RADEON_FLAG_ENCRYPTED;
102 
103    if (sscreen->debug_flags & DBG(NO_WC))
104       res->flags &= ~RADEON_FLAG_GTT_WC;
105 
106    if (res->b.b.flags & SI_RESOURCE_FLAG_32BIT)
107       res->flags |= RADEON_FLAG_32BIT;
108 
109    if (res->b.b.flags & SI_RESOURCE_FLAG_DRIVER_INTERNAL)
110       res->flags |= RADEON_FLAG_DRIVER_INTERNAL;
111 
112    if (res->b.b.flags & PIPE_RESOURCE_FLAG_SPARSE)
113       res->flags |= RADEON_FLAG_SPARSE;
114 
115    /* For bypassing GL2 for performance reasons (not being slowed down by GL2, and not slowing down
116     * parallel GL2 traffic) such as asynchronous DRI prime blits, or when coherency with non-GL2
117     * clients is required, such as with GFX12. GFX8 and older don't support RADEON_FLAG_GL2_BYPASS.
118     */
119    if (sscreen->info.gfx_level >= GFX9 &&
120        res->b.b.flags & SI_RESOURCE_FLAG_GL2_BYPASS)
121       res->flags |= RADEON_FLAG_GL2_BYPASS;
122 
123    if (res->b.b.flags & SI_RESOURCE_FLAG_DISCARDABLE &&
124        sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 47) {
125       /* Assume VRAM, so that we can use BIG_PAGE. */
126       assert(res->domains == RADEON_DOMAIN_VRAM);
127       res->flags |= RADEON_FLAG_DISCARDABLE;
128    }
129 
130    if (res->domains & RADEON_DOMAIN_VRAM) {
131       /* We don't want to evict buffers from VRAM by mapping them for CPU access,
132        * because they might never be moved back again. If a buffer is large enough,
133        * upload data by copying from a temporary GTT buffer.
134        */
135       if (sscreen->info.has_dedicated_vram && !sscreen->info.all_vram_visible &&
136           !res->b.cpu_storage && /* TODO: The CPU storage breaks this. */
137           size >= sscreen->options.max_vram_map_size)
138          res->b.b.flags |= PIPE_RESOURCE_FLAG_DONT_MAP_DIRECTLY;
139    }
140 }
141 
si_alloc_resource(struct si_screen * sscreen,struct si_resource * res)142 bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res)
143 {
144    struct pb_buffer_lean *old_buf, *new_buf;
145 
146    /* Allocate a new resource. */
147    new_buf = sscreen->ws->buffer_create(sscreen->ws, res->bo_size, 1 << res->bo_alignment_log2,
148                                         res->domains, res->flags);
149    if (!new_buf) {
150       return false;
151    }
152 
153    /* Replace the pointer such that if res->buf wasn't NULL, it won't be
154     * NULL. This should prevent crashes with multiple contexts using
155     * the same buffer where one of the contexts invalidates it while
156     * the others are using it. */
157    old_buf = res->buf;
158    res->buf = new_buf; /* should be atomic */
159    res->gpu_address = sscreen->ws->buffer_get_virtual_address(res->buf);
160 
161    if (res->flags & RADEON_FLAG_32BIT) {
162       uint64_t start = res->gpu_address;
163       uint64_t last = start + res->bo_size - 1;
164       (void)start;
165       (void)last;
166 
167       assert((start >> 32) == sscreen->info.address32_hi);
168       assert((last >> 32) == sscreen->info.address32_hi);
169    }
170 
171    radeon_bo_reference(sscreen->ws, &old_buf, NULL);
172 
173    util_range_set_empty(&res->valid_buffer_range);
174    res->L2_cache_dirty = false;
175 
176    if (res->b.b.target != PIPE_BUFFER && !(res->b.b.flags & SI_RESOURCE_AUX_PLANE)) {
177       /* The buffer is shared with other planes. */
178       struct si_resource *plane = (struct si_resource *)res->b.b.next;
179       for (; plane; plane = (struct si_resource *)plane->b.b.next) {
180          radeon_bo_reference(sscreen->ws, &plane->buf, res->buf);
181          plane->gpu_address = res->gpu_address;
182       }
183    }
184 
185    /* Print debug information. */
186    if (sscreen->debug_flags & DBG(VM) && res->b.b.target == PIPE_BUFFER) {
187       fprintf(stderr, "VM start=0x%" PRIX64 "  end=0x%" PRIX64 " | Buffer %" PRIu64 " bytes | Flags: ",
188               res->gpu_address, res->gpu_address + res->buf->size, res->buf->size);
189       si_res_print_flags(res->flags);
190       fprintf(stderr, "\n");
191    }
192 
193    if (res->b.b.flags & SI_RESOURCE_FLAG_CLEAR) {
194       struct si_context *ctx = si_get_aux_context(&sscreen->aux_context.compute_resource_init);
195       uint32_t value = 0;
196 
197       si_clear_buffer(ctx, &res->b.b, 0, res->bo_size, &value, 4, SI_AUTO_SELECT_CLEAR_METHOD,
198                       false);
199       si_put_aux_context_flush(&sscreen->aux_context.compute_resource_init);
200    }
201 
202    return true;
203 }
204 
si_resource_destroy(struct pipe_screen * screen,struct pipe_resource * buf)205 static void si_resource_destroy(struct pipe_screen *screen, struct pipe_resource *buf)
206 {
207    if (buf->target == PIPE_BUFFER) {
208       struct si_screen *sscreen = (struct si_screen *)screen;
209       struct si_resource *buffer = si_resource(buf);
210 
211       threaded_resource_deinit(buf);
212       util_range_destroy(&buffer->valid_buffer_range);
213       radeon_bo_reference(((struct si_screen*)screen)->ws, &buffer->buf, NULL);
214       util_idalloc_mt_free(&sscreen->buffer_ids, buffer->b.buffer_id_unique);
215       FREE_CL(buffer);
216    } else if (buf->flags & SI_RESOURCE_AUX_PLANE) {
217       struct si_auxiliary_texture *tex = (struct si_auxiliary_texture *)buf;
218 
219       radeon_bo_reference(((struct si_screen*)screen)->ws, &tex->buffer, NULL);
220       FREE_CL(tex);
221    } else {
222       struct si_texture *tex = (struct si_texture *)buf;
223       struct si_resource *resource = &tex->buffer;
224 
225       si_texture_reference(&tex->flushed_depth_texture, NULL);
226 
227       if (tex->cmask_buffer != &tex->buffer) {
228          si_resource_reference(&tex->cmask_buffer, NULL);
229       }
230       radeon_bo_reference(((struct si_screen*)screen)->ws, &resource->buf, NULL);
231       FREE_CL(tex);
232    }
233 }
234 
235 /* Reallocate the buffer a update all resource bindings where the buffer is
236  * bound.
237  *
238  * This is used to avoid CPU-GPU synchronizations, because it makes the buffer
239  * idle by discarding its contents.
240  */
si_invalidate_buffer(struct si_context * sctx,struct si_resource * buf)241 static bool si_invalidate_buffer(struct si_context *sctx, struct si_resource *buf)
242 {
243    /* Shared buffers can't be reallocated. */
244    if (buf->b.is_shared)
245       return false;
246 
247    /* Sparse buffers can't be reallocated. */
248    if (buf->flags & RADEON_FLAG_SPARSE)
249       return false;
250 
251    /* In AMD_pinned_memory, the user pointer association only gets
252     * broken when the buffer is explicitly re-allocated.
253     */
254    if (buf->b.is_user_ptr)
255       return false;
256 
257    /* Check if mapping this buffer would cause waiting for the GPU. */
258    if (si_cs_is_buffer_referenced(sctx, buf->buf, RADEON_USAGE_READWRITE) ||
259        !sctx->ws->buffer_wait(sctx->ws, buf->buf, 0,
260                               RADEON_USAGE_READWRITE | RADEON_USAGE_DISALLOW_SLOW_REPLY)) {
261       /* Reallocate the buffer in the same pipe_resource. */
262       si_alloc_resource(sctx->screen, buf);
263       si_rebind_buffer(sctx, &buf->b.b);
264    } else {
265       util_range_set_empty(&buf->valid_buffer_range);
266    }
267 
268    return true;
269 }
270 
271 /* Replace the storage of dst with src. */
si_replace_buffer_storage(struct pipe_context * ctx,struct pipe_resource * dst,struct pipe_resource * src,unsigned num_rebinds,uint32_t rebind_mask,uint32_t delete_buffer_id)272 void si_replace_buffer_storage(struct pipe_context *ctx, struct pipe_resource *dst,
273                                struct pipe_resource *src, unsigned num_rebinds, uint32_t rebind_mask,
274                                uint32_t delete_buffer_id)
275 {
276    struct si_context *sctx = (struct si_context *)ctx;
277    struct si_resource *sdst = si_resource(dst);
278    struct si_resource *ssrc = si_resource(src);
279 
280    radeon_bo_reference(sctx->screen->ws, &sdst->buf, ssrc->buf);
281    sdst->gpu_address = ssrc->gpu_address;
282    sdst->b.b.bind = ssrc->b.b.bind;
283    sdst->flags = ssrc->flags;
284 
285    assert(sdst->bo_size == ssrc->bo_size);
286    assert(sdst->bo_alignment_log2 == ssrc->bo_alignment_log2);
287    assert(sdst->domains == ssrc->domains);
288 
289    si_rebind_buffer(sctx, dst);
290 
291    util_idalloc_mt_free(&sctx->screen->buffer_ids, delete_buffer_id);
292 }
293 
si_invalidate_resource(struct pipe_context * ctx,struct pipe_resource * resource)294 static void si_invalidate_resource(struct pipe_context *ctx, struct pipe_resource *resource)
295 {
296    struct si_context *sctx = (struct si_context *)ctx;
297    struct si_resource *buf = si_resource(resource);
298 
299    /* We currently only do anything here for buffers */
300    if (resource->target == PIPE_BUFFER)
301       (void)si_invalidate_buffer(sctx, buf);
302 }
303 
si_buffer_get_transfer(struct pipe_context * ctx,struct pipe_resource * resource,unsigned usage,const struct pipe_box * box,struct pipe_transfer ** ptransfer,void * data,struct si_resource * staging,unsigned offset)304 static void *si_buffer_get_transfer(struct pipe_context *ctx, struct pipe_resource *resource,
305                                     unsigned usage, const struct pipe_box *box,
306                                     struct pipe_transfer **ptransfer, void *data,
307                                     struct si_resource *staging, unsigned offset)
308 {
309    struct si_context *sctx = (struct si_context *)ctx;
310    struct si_transfer *transfer;
311 
312    if (usage & PIPE_MAP_THREAD_SAFE)
313       transfer = calloc(1, sizeof(*transfer));
314    else if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
315       transfer = slab_zalloc(&sctx->pool_transfers_unsync);
316    else
317       transfer = slab_zalloc(&sctx->pool_transfers);
318 
319    pipe_resource_reference(&transfer->b.b.resource, resource);
320    transfer->b.b.usage = usage;
321    transfer->b.b.box = *box;
322    transfer->b.b.offset = offset;
323    transfer->staging = staging;
324    *ptransfer = &transfer->b.b;
325    return data;
326 }
327 
si_buffer_transfer_map(struct pipe_context * ctx,struct pipe_resource * resource,unsigned level,unsigned usage,const struct pipe_box * box,struct pipe_transfer ** ptransfer)328 static void *si_buffer_transfer_map(struct pipe_context *ctx, struct pipe_resource *resource,
329                                     unsigned level, unsigned usage, const struct pipe_box *box,
330                                     struct pipe_transfer **ptransfer)
331 {
332    struct si_context *sctx = (struct si_context *)ctx;
333    struct si_resource *buf = si_resource(resource);
334    uint8_t *data;
335 
336    assert(resource->target == PIPE_BUFFER);
337    assert(box->x + box->width <= resource->width0);
338 
339    /* From GL_AMD_pinned_memory issues:
340     *
341     *     4) Is glMapBuffer on a shared buffer guaranteed to return the
342     *        same system address which was specified at creation time?
343     *
344     *        RESOLVED: NO. The GL implementation might return a different
345     *        virtual mapping of that memory, although the same physical
346     *        page will be used.
347     *
348     * So don't ever use staging buffers.
349     */
350    if (buf->b.is_user_ptr)
351       usage |= PIPE_MAP_PERSISTENT;
352    if (usage & PIPE_MAP_ONCE)
353       usage |= RADEON_MAP_TEMPORARY;
354 
355    /* See if the buffer range being mapped has never been initialized,
356     * in which case it can be mapped unsynchronized. */
357    if (!(usage & (PIPE_MAP_UNSYNCHRONIZED | TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED)) &&
358        usage & PIPE_MAP_WRITE && !buf->b.is_shared &&
359        !util_ranges_intersect(&buf->valid_buffer_range, box->x, box->x + box->width)) {
360       usage |= PIPE_MAP_UNSYNCHRONIZED;
361    }
362 
363    /* If discarding the entire range, discard the whole resource instead. */
364    if (usage & PIPE_MAP_DISCARD_RANGE && box->x == 0 && box->width == resource->width0) {
365       usage |= PIPE_MAP_DISCARD_WHOLE_RESOURCE;
366    }
367 
368    /* If a buffer in VRAM is too large and the range is discarded, don't
369     * map it directly. This makes sure that the buffer stays in VRAM.
370     */
371    bool force_discard_range = false;
372    if (usage & (PIPE_MAP_DISCARD_WHOLE_RESOURCE | PIPE_MAP_DISCARD_RANGE) &&
373        !(usage & PIPE_MAP_PERSISTENT) &&
374        buf->b.b.flags & PIPE_RESOURCE_FLAG_DONT_MAP_DIRECTLY) {
375       usage &= ~(PIPE_MAP_DISCARD_WHOLE_RESOURCE | PIPE_MAP_UNSYNCHRONIZED);
376       usage |= PIPE_MAP_DISCARD_RANGE;
377       force_discard_range = true;
378    }
379 
380    if (usage & PIPE_MAP_DISCARD_WHOLE_RESOURCE &&
381        !(usage & (PIPE_MAP_UNSYNCHRONIZED | TC_TRANSFER_MAP_NO_INVALIDATE))) {
382       assert(usage & PIPE_MAP_WRITE);
383 
384       if (si_invalidate_buffer(sctx, buf)) {
385          /* At this point, the buffer is always idle. */
386          usage |= PIPE_MAP_UNSYNCHRONIZED;
387       } else {
388          /* Fall back to a temporary buffer. */
389          usage |= PIPE_MAP_DISCARD_RANGE;
390       }
391    }
392 
393    if (usage & PIPE_MAP_DISCARD_RANGE &&
394        ((!(usage & (PIPE_MAP_UNSYNCHRONIZED | PIPE_MAP_PERSISTENT))) ||
395         (buf->flags & RADEON_FLAG_SPARSE))) {
396       assert(usage & PIPE_MAP_WRITE);
397 
398       /* Check if mapping this buffer would cause waiting for the GPU.
399        */
400       if (buf->flags & (RADEON_FLAG_SPARSE | RADEON_FLAG_NO_CPU_ACCESS) ||
401           force_discard_range ||
402           si_cs_is_buffer_referenced(sctx, buf->buf, RADEON_USAGE_READWRITE) ||
403           !sctx->ws->buffer_wait(sctx->ws, buf->buf, 0,
404                                  RADEON_USAGE_READWRITE | RADEON_USAGE_DISALLOW_SLOW_REPLY)) {
405          /* Do a wait-free write-only transfer using a temporary buffer. */
406          struct u_upload_mgr *uploader;
407          struct si_resource *staging = NULL;
408          unsigned offset;
409 
410          /* If we are not called from the driver thread, we have
411           * to use the uploader from u_threaded_context, which is
412           * local to the calling thread.
413           */
414          if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
415             uploader = sctx->tc->base.stream_uploader;
416          else
417             uploader = sctx->b.stream_uploader;
418 
419          u_upload_alloc(uploader, 0, box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT),
420                         sctx->screen->info.tcc_cache_line_size, &offset,
421                         (struct pipe_resource **)&staging, (void **)&data);
422 
423          if (staging) {
424             data += box->x % SI_MAP_BUFFER_ALIGNMENT;
425             return si_buffer_get_transfer(ctx, resource, usage, box, ptransfer, data, staging,
426                                           offset);
427          } else if (buf->flags & RADEON_FLAG_SPARSE) {
428             return NULL;
429          }
430       } else {
431          /* At this point, the buffer is always idle (we checked it above). */
432          usage |= PIPE_MAP_UNSYNCHRONIZED;
433       }
434    }
435    /* Use a staging buffer in cached GTT for reads. */
436    else if (((usage & PIPE_MAP_READ) && !(usage & PIPE_MAP_PERSISTENT) &&
437              (buf->domains & RADEON_DOMAIN_VRAM || buf->flags & RADEON_FLAG_GTT_WC)) ||
438             (buf->flags & (RADEON_FLAG_SPARSE | RADEON_FLAG_NO_CPU_ACCESS))) {
439       struct si_resource *staging;
440 
441       assert(!(usage & (TC_TRANSFER_MAP_THREADED_UNSYNC | PIPE_MAP_THREAD_SAFE)));
442       staging = si_aligned_buffer_create(ctx->screen,
443                                          SI_RESOURCE_FLAG_GL2_BYPASS | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
444                                          PIPE_USAGE_STAGING,
445                                          box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT), 256);
446       if (staging) {
447          /* Copy the VRAM buffer to the staging buffer. */
448          si_barrier_before_simple_buffer_op(sctx, 0, &staging->b.b, resource);
449          si_copy_buffer(sctx, &staging->b.b, resource, box->x % SI_MAP_BUFFER_ALIGNMENT,
450                         box->x, box->width);
451          /* Since the CPU will wait for the copy to finish, we don't have to insert any GPU barrier
452           * after the copy because there is no GPU reader.
453           */
454 
455          data = si_buffer_map(sctx, staging, usage & ~PIPE_MAP_UNSYNCHRONIZED);
456          if (!data) {
457             si_resource_reference(&staging, NULL);
458             return NULL;
459          }
460          data += box->x % SI_MAP_BUFFER_ALIGNMENT;
461 
462          return si_buffer_get_transfer(ctx, resource, usage, box, ptransfer, data, staging, 0);
463       } else if (buf->flags & RADEON_FLAG_SPARSE) {
464          return NULL;
465       }
466    }
467 
468    data = si_buffer_map(sctx, buf, usage);
469    if (!data) {
470       return NULL;
471    }
472    data += box->x;
473 
474    return si_buffer_get_transfer(ctx, resource, usage, box, ptransfer, data, NULL, 0);
475 }
476 
si_buffer_do_flush_region(struct pipe_context * ctx,struct pipe_transfer * transfer,const struct pipe_box * box)477 static void si_buffer_do_flush_region(struct pipe_context *ctx, struct pipe_transfer *transfer,
478                                       const struct pipe_box *box)
479 {
480    struct si_context *sctx = (struct si_context *)ctx;
481    struct si_transfer *stransfer = (struct si_transfer *)transfer;
482    struct si_resource *buf = si_resource(transfer->resource);
483 
484    if (stransfer->staging) {
485       unsigned src_offset =
486          stransfer->b.b.offset + transfer->box.x % SI_MAP_BUFFER_ALIGNMENT + (box->x - transfer->box.x);
487 
488       /* Copy the staging buffer into the original one. */
489       si_barrier_before_simple_buffer_op(sctx, 0, transfer->resource, &stransfer->staging->b.b);
490       si_copy_buffer(sctx, transfer->resource, &stransfer->staging->b.b, box->x, src_offset,
491                      box->width);
492       si_barrier_after_simple_buffer_op(sctx, 0, transfer->resource, &stransfer->staging->b.b);
493    }
494 
495    util_range_add(&buf->b.b, &buf->valid_buffer_range, box->x, box->x + box->width);
496 }
497 
si_buffer_flush_region(struct pipe_context * ctx,struct pipe_transfer * transfer,const struct pipe_box * rel_box)498 static void si_buffer_flush_region(struct pipe_context *ctx, struct pipe_transfer *transfer,
499                                    const struct pipe_box *rel_box)
500 {
501    unsigned required_usage = PIPE_MAP_WRITE | PIPE_MAP_FLUSH_EXPLICIT;
502 
503    if ((transfer->usage & required_usage) == required_usage) {
504       struct pipe_box box;
505 
506       u_box_1d(transfer->box.x + rel_box->x, rel_box->width, &box);
507       si_buffer_do_flush_region(ctx, transfer, &box);
508    }
509 }
510 
si_buffer_transfer_unmap(struct pipe_context * ctx,struct pipe_transfer * transfer)511 static void si_buffer_transfer_unmap(struct pipe_context *ctx, struct pipe_transfer *transfer)
512 {
513    struct si_context *sctx = (struct si_context *)ctx;
514    struct si_transfer *stransfer = (struct si_transfer *)transfer;
515 
516    if (transfer->usage & PIPE_MAP_WRITE && !(transfer->usage & PIPE_MAP_FLUSH_EXPLICIT))
517       si_buffer_do_flush_region(ctx, transfer, &transfer->box);
518 
519    if (transfer->usage & (PIPE_MAP_ONCE | RADEON_MAP_TEMPORARY) &&
520        !stransfer->staging)
521       sctx->ws->buffer_unmap(sctx->ws, si_resource(stransfer->b.b.resource)->buf);
522 
523    si_resource_reference(&stransfer->staging, NULL);
524    assert(stransfer->b.staging == NULL); /* for threaded context only */
525    pipe_resource_reference(&transfer->resource, NULL);
526 
527    if (transfer->usage & PIPE_MAP_THREAD_SAFE) {
528       free(transfer);
529    } else {
530       /* Don't use pool_transfers_unsync. We are always in the driver
531        * thread. Freeing an object into a different pool is allowed.
532        */
533       slab_free(&sctx->pool_transfers, transfer);
534    }
535 }
536 
si_buffer_subdata(struct pipe_context * ctx,struct pipe_resource * buffer,unsigned usage,unsigned offset,unsigned size,const void * data)537 static void si_buffer_subdata(struct pipe_context *ctx, struct pipe_resource *buffer,
538                               unsigned usage, unsigned offset, unsigned size, const void *data)
539 {
540    struct pipe_transfer *transfer = NULL;
541    struct pipe_box box;
542    uint8_t *map = NULL;
543 
544    usage |= PIPE_MAP_WRITE;
545 
546    if (!(usage & PIPE_MAP_DIRECTLY))
547       usage |= PIPE_MAP_DISCARD_RANGE;
548 
549    u_box_1d(offset, size, &box);
550    map = si_buffer_transfer_map(ctx, buffer, 0, usage, &box, &transfer);
551    if (!map)
552       return;
553 
554    memcpy(map, data, size);
555    si_buffer_transfer_unmap(ctx, transfer);
556 }
557 
si_alloc_buffer_struct(struct pipe_screen * screen,const struct pipe_resource * templ,bool allow_cpu_storage)558 static struct si_resource *si_alloc_buffer_struct(struct pipe_screen *screen,
559                                                   const struct pipe_resource *templ,
560                                                   bool allow_cpu_storage)
561 {
562    struct si_resource *buf = MALLOC_STRUCT_CL(si_resource);
563 
564    buf->b.b = *templ;
565    buf->b.b.next = NULL;
566    pipe_reference_init(&buf->b.b.reference, 1);
567    buf->b.b.screen = screen;
568 
569    threaded_resource_init(&buf->b.b, allow_cpu_storage);
570 
571    buf->buf = NULL;
572    buf->bind_history = 0;
573    buf->L2_cache_dirty = false;
574    util_range_init(&buf->valid_buffer_range);
575    return buf;
576 }
577 
si_buffer_create(struct pipe_screen * screen,const struct pipe_resource * templ,unsigned alignment)578 static struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
579                                               const struct pipe_resource *templ, unsigned alignment)
580 {
581    struct si_screen *sscreen = (struct si_screen *)screen;
582    struct si_resource *buf =
583       si_alloc_buffer_struct(screen, templ,
584                              templ->width0 <= sscreen->options.tc_max_cpu_storage_size);
585 
586    if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
587       buf->b.b.flags |= PIPE_RESOURCE_FLAG_UNMAPPABLE;
588 
589    si_init_resource_fields(sscreen, buf, templ->width0, alignment);
590 
591    buf->b.buffer_id_unique = util_idalloc_mt_alloc(&sscreen->buffer_ids);
592 
593    if (!si_alloc_resource(sscreen, buf)) {
594       si_resource_destroy(screen, &buf->b.b);
595       return NULL;
596    }
597 
598    return &buf->b.b;
599 }
600 
pipe_aligned_buffer_create(struct pipe_screen * screen,unsigned flags,unsigned usage,unsigned size,unsigned alignment)601 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen, unsigned flags,
602                                                  unsigned usage, unsigned size, unsigned alignment)
603 {
604    struct pipe_resource buffer;
605 
606    memset(&buffer, 0, sizeof buffer);
607    buffer.target = PIPE_BUFFER;
608    buffer.format = PIPE_FORMAT_R8_UNORM;
609    buffer.bind = 0;
610    buffer.usage = usage;
611    buffer.flags = flags;
612    buffer.width0 = size;
613    buffer.height0 = 1;
614    buffer.depth0 = 1;
615    buffer.array_size = 1;
616    return si_buffer_create(screen, &buffer, alignment);
617 }
618 
si_aligned_buffer_create(struct pipe_screen * screen,unsigned flags,unsigned usage,unsigned size,unsigned alignment)619 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen, unsigned flags,
620                                              unsigned usage, unsigned size, unsigned alignment)
621 {
622    return si_resource(pipe_aligned_buffer_create(screen, flags, usage, size, alignment));
623 }
624 
si_buffer_from_user_memory(struct pipe_screen * screen,const struct pipe_resource * templ,void * user_memory)625 static struct pipe_resource *si_buffer_from_user_memory(struct pipe_screen *screen,
626                                                         const struct pipe_resource *templ,
627                                                         void *user_memory)
628 {
629    if (templ->target != PIPE_BUFFER)
630       return NULL;
631 
632    struct si_screen *sscreen = (struct si_screen *)screen;
633    struct radeon_winsys *ws = sscreen->ws;
634    struct si_resource *buf = si_alloc_buffer_struct(screen, templ, false);
635 
636    buf->domains = RADEON_DOMAIN_GTT;
637    buf->flags = 0;
638    buf->b.is_user_ptr = true;
639    util_range_add(&buf->b.b, &buf->valid_buffer_range, 0, templ->width0);
640    util_range_add(&buf->b.b, &buf->b.valid_buffer_range, 0, templ->width0);
641 
642    buf->b.buffer_id_unique = util_idalloc_mt_alloc(&sscreen->buffer_ids);
643 
644    /* Convert a user pointer to a buffer. */
645    buf->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0, 0);
646    if (!buf->buf) {
647       si_resource_destroy(screen, &buf->b.b);
648       return NULL;
649    }
650 
651    buf->gpu_address = ws->buffer_get_virtual_address(buf->buf);
652    buf->bo_size = templ->width0;
653    return &buf->b.b;
654 }
655 
si_buffer_from_winsys_buffer(struct pipe_screen * screen,const struct pipe_resource * templ,struct pb_buffer_lean * imported_buf,uint64_t offset)656 struct pipe_resource *si_buffer_from_winsys_buffer(struct pipe_screen *screen,
657                                                    const struct pipe_resource *templ,
658                                                    struct pb_buffer_lean *imported_buf,
659                                                    uint64_t offset)
660 {
661    if (offset + templ->width0 > imported_buf->size)
662       return NULL;
663 
664    struct si_screen *sscreen = (struct si_screen *)screen;
665    struct si_resource *res = si_alloc_buffer_struct(screen, templ, false);
666 
667    if (!res)
668       return NULL;
669 
670    enum radeon_bo_domain domains = sscreen->ws->buffer_get_initial_domain(imported_buf);
671 
672    /* Get or guess the BO flags. */
673    unsigned flags = RADEON_FLAG_NO_SUBALLOC;
674 
675    if (sscreen->ws->buffer_get_flags)
676       res->flags |= sscreen->ws->buffer_get_flags(imported_buf);
677    else
678       flags |= RADEON_FLAG_GTT_WC; /* unknown flags, guess them */
679 
680    /* Deduce the usage. */
681    switch (domains) {
682    case RADEON_DOMAIN_VRAM:
683    case RADEON_DOMAIN_VRAM_GTT:
684       res->b.b.usage = PIPE_USAGE_DEFAULT;
685       break;
686 
687    default:
688       /* Other values are interpreted as GTT. */
689       domains = RADEON_DOMAIN_GTT;
690 
691       if (flags & RADEON_FLAG_GTT_WC)
692          res->b.b.usage = PIPE_USAGE_STREAM;
693       else
694          res->b.b.usage = PIPE_USAGE_STAGING;
695    }
696 
697    si_init_resource_fields(sscreen, res, imported_buf->size,
698                            1 << imported_buf->alignment_log2);
699 
700    res->b.is_shared = true;
701    res->b.buffer_id_unique = util_idalloc_mt_alloc(&sscreen->buffer_ids);
702    res->buf = imported_buf;
703    res->gpu_address = sscreen->ws->buffer_get_virtual_address(res->buf) + offset;
704    res->domains = domains;
705    res->flags = flags;
706 
707    if (res->flags & RADEON_FLAG_NO_CPU_ACCESS)
708       res->b.b.flags |= PIPE_RESOURCE_FLAG_UNMAPPABLE;
709 
710    util_range_add(&res->b.b, &res->valid_buffer_range, 0, templ->width0);
711    util_range_add(&res->b.b, &res->b.valid_buffer_range, 0, templ->width0);
712 
713    return &res->b.b;
714 }
715 
si_resource_create(struct pipe_screen * screen,const struct pipe_resource * templ)716 static struct pipe_resource *si_resource_create(struct pipe_screen *screen,
717                                                 const struct pipe_resource *templ)
718 {
719    if (templ->target == PIPE_BUFFER) {
720       return si_buffer_create(screen, templ, 256);
721    } else {
722       return si_texture_create(screen, templ);
723    }
724 }
725 
si_buffer_commit(struct si_context * ctx,struct si_resource * res,struct pipe_box * box,bool commit)726 static bool si_buffer_commit(struct si_context *ctx, struct si_resource *res,
727                              struct pipe_box *box, bool commit)
728 {
729    return ctx->ws->buffer_commit(ctx->ws, res->buf, box->x, box->width, commit);
730 }
731 
si_resource_commit(struct pipe_context * pctx,struct pipe_resource * resource,unsigned level,struct pipe_box * box,bool commit)732 static bool si_resource_commit(struct pipe_context *pctx, struct pipe_resource *resource,
733                                unsigned level, struct pipe_box *box, bool commit)
734 {
735    struct si_context *ctx = (struct si_context *)pctx;
736    struct si_resource *res = si_resource(resource);
737 
738    /*
739     * Since buffer commitment changes cannot be pipelined, we need to
740     * (a) flush any pending commands that refer to the buffer we're about
741     *     to change, and
742     * (b) wait for threaded submit to finish, including those that were
743     *     triggered by some other, earlier operation.
744     */
745    if (radeon_emitted(&ctx->gfx_cs, ctx->initial_gfx_cs_size) &&
746        ctx->ws->cs_is_buffer_referenced(&ctx->gfx_cs, res->buf, RADEON_USAGE_READWRITE)) {
747       si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
748    }
749    ctx->ws->cs_sync_flush(&ctx->gfx_cs);
750 
751    if (resource->target == PIPE_BUFFER)
752       return si_buffer_commit(ctx, res, box, commit);
753    else
754       return si_texture_commit(ctx, res, level, box, commit);
755 }
756 
si_init_screen_buffer_functions(struct si_screen * sscreen)757 void si_init_screen_buffer_functions(struct si_screen *sscreen)
758 {
759    sscreen->b.resource_create = si_resource_create;
760    sscreen->b.resource_destroy = si_resource_destroy;
761    sscreen->b.resource_from_user_memory = si_buffer_from_user_memory;
762 }
763 
si_init_buffer_functions(struct si_context * sctx)764 void si_init_buffer_functions(struct si_context *sctx)
765 {
766    sctx->b.invalidate_resource = si_invalidate_resource;
767    sctx->b.buffer_map = si_buffer_transfer_map;
768    sctx->b.transfer_flush_region = si_buffer_flush_region;
769    sctx->b.buffer_unmap = si_buffer_transfer_unmap;
770    sctx->b.texture_subdata = u_default_texture_subdata;
771    sctx->b.buffer_subdata = si_buffer_subdata;
772    sctx->b.resource_commit = si_resource_commit;
773 }
774