1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
7 #include "ac_rtld.h"
8 #include "amd_kernel_code_t.h"
9 #include "nir/tgsi_to_nir.h"
10 #include "si_build_pm4.h"
11 #include "si_shader_internal.h"
12 #include "util/u_async_debug.h"
13 #include "util/u_memory.h"
14 #include "util/u_upload_mgr.h"
15 #include "si_tracepoints.h"
16
17 #define COMPUTE_DBG(sscreen, fmt, args...) \
18 do { \
19 if ((sscreen->debug_flags & DBG(COMPUTE))) \
20 fprintf(stderr, fmt, ##args); \
21 } while (0);
22
23 struct dispatch_packet {
24 uint16_t header;
25 uint16_t setup;
26 uint16_t workgroup_size_x;
27 uint16_t workgroup_size_y;
28 uint16_t workgroup_size_z;
29 uint16_t reserved0;
30 uint32_t grid_size_x;
31 uint32_t grid_size_y;
32 uint32_t grid_size_z;
33 uint32_t group_segment_size;
34 uint64_t kernel_object;
35 uint64_t kernarg_address;
36 uint64_t reserved2;
37 };
38
si_compute_get_code_object(const struct si_compute * program,uint64_t symbol_offset)39 static const amd_kernel_code_t *si_compute_get_code_object(const struct si_compute *program,
40 uint64_t symbol_offset)
41 {
42 const struct si_shader_selector *sel = &program->sel;
43
44 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
45 return NULL;
46
47 struct ac_rtld_binary rtld;
48 if (!ac_rtld_open(&rtld,
49 (struct ac_rtld_open_info){.info = &sel->screen->info,
50 .shader_type = MESA_SHADER_COMPUTE,
51 .num_parts = 1,
52 .elf_ptrs = &program->shader.binary.code_buffer,
53 .elf_sizes = &program->shader.binary.code_size}))
54 return NULL;
55
56 const amd_kernel_code_t *result = NULL;
57 const char *text;
58 size_t size;
59 if (!ac_rtld_get_section_by_name(&rtld, ".text", &text, &size))
60 goto out;
61
62 if (symbol_offset + sizeof(amd_kernel_code_t) > size)
63 goto out;
64
65 result = (const amd_kernel_code_t *)(text + symbol_offset);
66
67 out:
68 ac_rtld_close(&rtld);
69 return result;
70 }
71
code_object_to_config(const amd_kernel_code_t * code_object,struct ac_shader_config * out_config)72 static void code_object_to_config(const amd_kernel_code_t *code_object,
73 struct ac_shader_config *out_config)
74 {
75
76 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
77 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
78 out_config->num_sgprs = code_object->wavefront_sgpr_count;
79 out_config->num_vgprs = code_object->workitem_vgpr_count;
80 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
81 out_config->rsrc1 = rsrc1;
82 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
83 out_config->rsrc2 = rsrc2;
84 out_config->scratch_bytes_per_wave =
85 align(code_object->workitem_private_segment_byte_size * 64, 1024);
86 }
87
88 /* Asynchronous compute shader compilation. */
si_create_compute_state_async(void * job,void * gdata,int thread_index)89 static void si_create_compute_state_async(void *job, void *gdata, int thread_index)
90 {
91 struct si_compute *program = (struct si_compute *)job;
92 struct si_shader_selector *sel = &program->sel;
93 struct si_shader *shader = &program->shader;
94 struct ac_llvm_compiler **compiler;
95 struct util_debug_callback *debug = &sel->compiler_ctx_state.debug;
96 struct si_screen *sscreen = sel->screen;
97
98 assert(!debug->debug_message || debug->async);
99 assert(thread_index >= 0);
100 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
101 compiler = &sscreen->compiler[thread_index];
102
103 assert(program->ir_type == PIPE_SHADER_IR_NIR);
104 si_nir_scan_shader(sscreen, sel->nir, &sel->info);
105
106 if (!sel->nir->info.use_aco_amd && !*compiler)
107 *compiler = si_create_llvm_compiler(sscreen);
108
109 si_get_active_slot_masks(sscreen, &sel->info, &sel->active_const_and_shader_buffers,
110 &sel->active_samplers_and_images);
111
112 program->shader.is_monolithic = true;
113 program->shader.wave_size = si_determine_wave_size(sscreen, &program->shader);
114
115 /* Variable block sizes need 10 bits (1 + log2(SI_MAX_VARIABLE_THREADS_PER_BLOCK)) per dim.
116 * We pack them into a single user SGPR.
117 */
118 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS + (sel->info.uses_grid_size ? 3 : 0) +
119 (sel->info.uses_variable_block_size ? 1 : 0) +
120 sel->nir->info.cs.user_data_components_amd;
121
122 /* Fast path for compute shaders - some descriptors passed via user SGPRs. */
123 /* Shader buffers in user SGPRs. */
124 for (unsigned i = 0; i < MIN2(3, sel->nir->info.num_ssbos) && user_sgprs <= 12; i++) {
125 user_sgprs = align(user_sgprs, 4);
126 if (i == 0)
127 sel->cs_shaderbufs_sgpr_index = user_sgprs;
128 user_sgprs += 4;
129 sel->cs_num_shaderbufs_in_user_sgprs++;
130 }
131
132 /* Images in user SGPRs. */
133 unsigned non_fmask_images = u_bit_consecutive(0, sel->nir->info.num_images);
134
135 /* Remove images with FMASK from the bitmask. We only care about the first
136 * 3 anyway, so we can take msaa_images[0] and ignore the rest.
137 */
138 if (sscreen->info.gfx_level < GFX11)
139 non_fmask_images &= ~sel->nir->info.msaa_images[0];
140
141 for (unsigned i = 0; i < 3 && non_fmask_images & (1 << i); i++) {
142 unsigned num_sgprs = BITSET_TEST(sel->nir->info.image_buffers, i) ? 4 : 8;
143
144 if (align(user_sgprs, num_sgprs) + num_sgprs > 16)
145 break;
146
147 user_sgprs = align(user_sgprs, num_sgprs);
148 if (i == 0)
149 sel->cs_images_sgpr_index = user_sgprs;
150 user_sgprs += num_sgprs;
151 sel->cs_num_images_in_user_sgprs++;
152 }
153 sel->cs_images_num_sgprs = user_sgprs - sel->cs_images_sgpr_index;
154 assert(user_sgprs <= 16);
155
156 unsigned char ir_sha1_cache_key[20];
157 si_get_ir_cache_key(sel, false, false, shader->wave_size, ir_sha1_cache_key);
158
159 /* Try to load the shader from the shader cache. */
160 simple_mtx_lock(&sscreen->shader_cache_mutex);
161
162 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
163 simple_mtx_unlock(&sscreen->shader_cache_mutex);
164
165 shader->complete_shader_binary_size = si_get_shader_binary_size(sscreen, shader);
166
167 if (!si_shader_binary_upload(sscreen, shader, 0))
168 program->shader.compilation_failed = true;
169
170 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
171 si_shader_dump(sscreen, shader, debug, stderr, true);
172 } else {
173 simple_mtx_unlock(&sscreen->shader_cache_mutex);
174
175 if (!si_create_shader_variant(sscreen, *compiler, &program->shader, debug)) {
176 program->shader.compilation_failed = true;
177 return;
178 }
179
180 shader->config.rsrc1 = S_00B848_VGPRS((shader->config.num_vgprs - 1) /
181 ((shader->wave_size == 32 ||
182 sscreen->info.wave64_vgpr_alloc_granularity == 8) ? 8 : 4)) |
183 S_00B848_DX10_CLAMP(sscreen->info.gfx_level < GFX12) |
184 S_00B848_MEM_ORDERED(si_shader_mem_ordered(shader)) |
185 S_00B848_FLOAT_MODE(shader->config.float_mode) |
186 /* This is needed for CWSR, but it causes halts to work differently. */
187 S_00B848_PRIV(sscreen->info.gfx_level == GFX11);
188
189 if (sscreen->info.gfx_level < GFX10) {
190 shader->config.rsrc1 |= S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8);
191 }
192
193 shader->config.rsrc2 = S_00B84C_USER_SGPR(user_sgprs) |
194 S_00B84C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
195 S_00B84C_TGID_X_EN(sel->info.uses_block_id[0]) |
196 S_00B84C_TGID_Y_EN(sel->info.uses_block_id[1]) |
197 S_00B84C_TGID_Z_EN(sel->info.uses_block_id[2]) |
198 S_00B84C_TG_SIZE_EN(sel->info.uses_tg_size) |
199 S_00B84C_TIDIG_COMP_CNT(sel->info.uses_thread_id[2]
200 ? 2
201 : sel->info.uses_thread_id[1] ? 1 : 0) |
202 S_00B84C_LDS_SIZE(shader->config.lds_size);
203
204 simple_mtx_lock(&sscreen->shader_cache_mutex);
205 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, true);
206 simple_mtx_unlock(&sscreen->shader_cache_mutex);
207 }
208
209 ralloc_free(sel->nir);
210 sel->nir = NULL;
211 }
212
si_create_compute_state(struct pipe_context * ctx,const struct pipe_compute_state * cso)213 static void *si_create_compute_state(struct pipe_context *ctx, const struct pipe_compute_state *cso)
214 {
215 struct si_context *sctx = (struct si_context *)ctx;
216 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
217 struct si_compute *program = CALLOC_STRUCT(si_compute);
218 struct si_shader_selector *sel = &program->sel;
219
220 pipe_reference_init(&sel->base.reference, 1);
221 sel->stage = MESA_SHADER_COMPUTE;
222 sel->screen = sscreen;
223 simple_mtx_init(&sel->mutex, mtx_plain);
224 sel->const_and_shader_buf_descriptors_index =
225 si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_COMPUTE);
226 sel->sampler_and_images_descriptors_index =
227 si_sampler_and_image_descriptors_idx(PIPE_SHADER_COMPUTE);
228 sel->info.base.shared_size = cso->static_shared_mem;
229 program->shader.selector = &program->sel;
230 program->ir_type = cso->ir_type;
231 program->input_size = cso->req_input_mem;
232
233 if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
234 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
235 program->ir_type = PIPE_SHADER_IR_NIR;
236 sel->nir = tgsi_to_nir(cso->prog, ctx->screen, true);
237 } else {
238 assert(cso->ir_type == PIPE_SHADER_IR_NIR);
239 sel->nir = (struct nir_shader *)cso->prog;
240 }
241
242 sel->nir->info.shared_size = cso->static_shared_mem;
243
244 if (si_can_dump_shader(sscreen, sel->stage, SI_DUMP_INIT_NIR))
245 nir_print_shader(sel->nir, stderr);
246
247 sel->compiler_ctx_state.debug = sctx->debug;
248 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
249 p_atomic_inc(&sscreen->num_shaders_created);
250
251 si_schedule_initial_compile(sctx, MESA_SHADER_COMPUTE, &sel->ready, &sel->compiler_ctx_state,
252 program, si_create_compute_state_async);
253 } else {
254 const struct pipe_binary_program_header *header;
255 header = cso->prog;
256
257 program->shader.binary.type = SI_SHADER_BINARY_ELF;
258 program->shader.binary.code_size = header->num_bytes;
259 program->shader.binary.code_buffer = malloc(header->num_bytes);
260 if (!program->shader.binary.code_buffer) {
261 FREE(program);
262 return NULL;
263 }
264 memcpy((void *)program->shader.binary.code_buffer, header->blob, header->num_bytes);
265
266 const amd_kernel_code_t *code_object = si_compute_get_code_object(program, 0);
267 code_object_to_config(code_object, &program->shader.config);
268
269 if (AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32))
270 program->shader.wave_size = 32;
271 else
272 program->shader.wave_size = 64;
273
274 bool ok = si_shader_binary_upload(sctx->screen, &program->shader, 0);
275 si_shader_dump(sctx->screen, &program->shader, &sctx->debug, stderr, true);
276
277 if (!ok) {
278 fprintf(stderr, "LLVM failed to upload shader\n");
279 free((void *)program->shader.binary.code_buffer);
280 FREE(program);
281 return NULL;
282 }
283 }
284
285 return program;
286 }
287
si_get_compute_state_info(struct pipe_context * ctx,void * state,struct pipe_compute_state_object_info * info)288 static void si_get_compute_state_info(struct pipe_context *ctx, void *state,
289 struct pipe_compute_state_object_info *info)
290 {
291 struct si_compute *program = (struct si_compute *)state;
292 struct si_shader_selector *sel = &program->sel;
293
294 assert(program->ir_type != PIPE_SHADER_IR_NATIVE);
295
296 /* Wait because we need the compilation to finish first */
297 util_queue_fence_wait(&sel->ready);
298
299 uint8_t wave_size = program->shader.wave_size;
300 info->private_memory = DIV_ROUND_UP(program->shader.config.scratch_bytes_per_wave, wave_size);
301 info->preferred_simd_size = wave_size;
302 info->simd_sizes = wave_size;
303 info->max_threads = si_get_max_workgroup_size(&program->shader);
304 }
305
si_bind_compute_state(struct pipe_context * ctx,void * state)306 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
307 {
308 struct si_context *sctx = (struct si_context *)ctx;
309 struct si_compute *program = (struct si_compute *)state;
310 struct si_shader_selector *sel = &program->sel;
311
312 sctx->cs_shader_state.program = program;
313 if (!program)
314 return;
315
316 /* Wait because we need active slot usage masks. */
317 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
318 util_queue_fence_wait(&sel->ready);
319
320 si_set_active_descriptors(sctx,
321 SI_DESCS_FIRST_COMPUTE + SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
322 sel->active_const_and_shader_buffers);
323 si_set_active_descriptors(sctx, SI_DESCS_FIRST_COMPUTE + SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
324 sel->active_samplers_and_images);
325
326 sctx->compute_shaderbuf_sgprs_dirty = true;
327 sctx->compute_image_sgprs_dirty = true;
328
329 if (unlikely((sctx->screen->debug_flags & DBG(SQTT)) && sctx->sqtt)) {
330 uint32_t pipeline_code_hash = _mesa_hash_data_with_seed(
331 program->shader.binary.code_buffer,
332 program->shader.binary.code_size,
333 0);
334
335 if (!si_sqtt_pipeline_is_registered(sctx->sqtt, pipeline_code_hash)) {
336 /* Short lived fake pipeline: we don't need to reupload the compute shaders,
337 * as we do for the gfx ones so just create a temp pipeline to be able to
338 * call si_sqtt_register_pipeline, and then drop it.
339 */
340 struct si_sqtt_fake_pipeline pipeline = { 0 };
341 pipeline.code_hash = pipeline_code_hash;
342 pipeline.bo = program->shader.bo;
343
344 si_sqtt_register_pipeline(sctx, &pipeline, NULL);
345 }
346
347 si_sqtt_describe_pipeline_bind(sctx, pipeline_code_hash, 1);
348 }
349 }
350
si_set_global_binding(struct pipe_context * ctx,unsigned first,unsigned n,struct pipe_resource ** resources,uint32_t ** handles)351 static void si_set_global_binding(struct pipe_context *ctx, unsigned first, unsigned n,
352 struct pipe_resource **resources, uint32_t **handles)
353 {
354 unsigned i;
355 struct si_context *sctx = (struct si_context *)ctx;
356
357 if (first + n > sctx->max_global_buffers) {
358 unsigned old_max = sctx->max_global_buffers;
359 sctx->max_global_buffers = first + n;
360 sctx->global_buffers = realloc(
361 sctx->global_buffers, sctx->max_global_buffers * sizeof(sctx->global_buffers[0]));
362 if (!sctx->global_buffers) {
363 fprintf(stderr, "radeonsi: failed to allocate compute global_buffers\n");
364 return;
365 }
366
367 memset(&sctx->global_buffers[old_max], 0,
368 (sctx->max_global_buffers - old_max) * sizeof(sctx->global_buffers[0]));
369 }
370
371 if (!resources) {
372 for (i = 0; i < n; i++) {
373 pipe_resource_reference(&sctx->global_buffers[first + i], NULL);
374 }
375 return;
376 }
377
378 for (i = 0; i < n; i++) {
379 uint64_t va;
380 uint32_t offset;
381 pipe_resource_reference(&sctx->global_buffers[first + i], resources[i]);
382 va = si_resource(resources[i])->gpu_address;
383 offset = util_le32_to_cpu(*handles[i]);
384 va += offset;
385 va = util_cpu_to_le64(va);
386 memcpy(handles[i], &va, sizeof(va));
387 }
388 }
389
si_setup_compute_scratch_buffer(struct si_context * sctx,struct si_shader * shader)390 static bool si_setup_compute_scratch_buffer(struct si_context *sctx, struct si_shader *shader)
391 {
392 uint64_t scratch_bo_size =
393 sctx->compute_scratch_buffer ? sctx->compute_scratch_buffer->b.b.width0 : 0;
394 uint64_t scratch_needed = sctx->max_seen_compute_scratch_bytes_per_wave *
395 sctx->screen->info.max_scratch_waves;
396 assert(scratch_needed);
397
398 if (scratch_bo_size < scratch_needed) {
399 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
400
401 sctx->compute_scratch_buffer =
402 si_aligned_buffer_create(&sctx->screen->b,
403 PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL |
404 SI_RESOURCE_FLAG_DISCARDABLE,
405 PIPE_USAGE_DEFAULT,
406 scratch_needed, sctx->screen->info.pte_fragment_size);
407
408 if (!sctx->compute_scratch_buffer)
409 return false;
410 }
411
412 /* Set the scratch address in the shader binary. */
413 if (!sctx->screen->info.has_scratch_base_registers) {
414 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
415
416 if (shader->scratch_va != scratch_va) {
417 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
418 return false;
419
420 shader->scratch_va = scratch_va;
421 }
422 }
423
424 return true;
425 }
426
si_switch_compute_shader(struct si_context * sctx,struct si_compute * program,struct si_shader * shader,const amd_kernel_code_t * code_object,unsigned offset,bool * prefetch,unsigned variable_shared_size)427 static bool si_switch_compute_shader(struct si_context *sctx, struct si_compute *program,
428 struct si_shader *shader, const amd_kernel_code_t *code_object,
429 unsigned offset, bool *prefetch, unsigned variable_shared_size)
430 {
431 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
432 struct ac_shader_config inline_config = {0};
433 const struct ac_shader_config *config;
434 unsigned rsrc2;
435 uint64_t shader_va;
436 unsigned stage = shader->selector->info.base.stage;
437
438 *prefetch = false;
439
440 assert(variable_shared_size == 0 || stage == MESA_SHADER_KERNEL || program->ir_type == PIPE_SHADER_IR_NATIVE);
441 if (sctx->cs_shader_state.emitted_program == program && sctx->cs_shader_state.offset == offset &&
442 sctx->cs_shader_state.variable_shared_size == variable_shared_size)
443 return true;
444
445 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
446 config = &shader->config;
447 } else {
448 code_object_to_config(code_object, &inline_config);
449 config = &inline_config;
450 }
451 /* copy rsrc2 so we don't have to change it inside the si_shader object */
452 rsrc2 = config->rsrc2;
453
454 /* only do this for OpenCL */
455 if (program->ir_type == PIPE_SHADER_IR_NATIVE || stage == MESA_SHADER_KERNEL) {
456 unsigned shared_size = program->sel.info.base.shared_size + variable_shared_size;
457 unsigned lds_blocks;
458
459 /* Clover uses the compute API differently than other frontends and expects drivers to parse
460 * the shared_size out of the shader headers.
461 */
462 if (program->ir_type == PIPE_SHADER_IR_NATIVE) {
463 lds_blocks = config->lds_size;
464 } else {
465 lds_blocks = 0;
466 }
467
468 /* XXX: We are over allocating LDS. For GFX6, the shader reports
469 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
470 * allocated in the shader and 4 bytes allocated by the state
471 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
472 */
473 if (sctx->gfx_level <= GFX6) {
474 lds_blocks += align(shared_size, 256) >> 8;
475 } else {
476 lds_blocks += align(shared_size, 512) >> 9;
477 }
478
479 /* TODO: use si_multiwave_lds_size_workaround */
480 assert(lds_blocks <= 0xFF);
481
482 rsrc2 &= C_00B84C_LDS_SIZE;
483 rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
484 }
485
486 if (config->scratch_bytes_per_wave) {
487 /* Prevent race conditions for accesses to shader->scratch_va and shader->bo, which
488 * can change when scratch_va is updated. Any accesses to shader->bo must also be inside
489 * the lock.
490 *
491 * TODO: This lock could be removed if the scratch address was passed via user SGPRs instead
492 * of the shader binary.
493 */
494 if (!sctx->screen->info.has_scratch_base_registers)
495 simple_mtx_lock(&shader->selector->mutex);
496
497 /* Update max_seen_compute_scratch_bytes_per_wave and compute_tmpring_size. */
498 ac_get_scratch_tmpring_size(&sctx->screen->info,
499 config->scratch_bytes_per_wave,
500 &sctx->max_seen_compute_scratch_bytes_per_wave,
501 &sctx->compute_tmpring_size);
502
503 if (!si_setup_compute_scratch_buffer(sctx, shader))
504 return false;
505
506 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->compute_scratch_buffer,
507 RADEON_USAGE_READWRITE | RADEON_PRIO_SCRATCH_BUFFER);
508 }
509
510 shader_va = shader->bo->gpu_address + offset;
511 if (program->ir_type == PIPE_SHADER_IR_NATIVE) {
512 /* Shader code is placed after the amd_kernel_code_t
513 * struct. */
514 shader_va += sizeof(amd_kernel_code_t);
515 }
516
517 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, shader->bo,
518 RADEON_USAGE_READ | RADEON_PRIO_SHADER_BINARY);
519
520 /* shader->bo can't be used after this if the scratch address is inserted into the shader
521 * binary.
522 */
523 if (config->scratch_bytes_per_wave && !sctx->screen->info.has_scratch_base_registers)
524 simple_mtx_unlock(&shader->selector->mutex);
525
526 if (sctx->gfx_level >= GFX12) {
527 unsigned rsrc3 = S_00B8A0_INST_PREF_SIZE_GFX12(si_get_shader_prefetch_size(shader));
528
529 gfx12_push_compute_sh_reg(R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
530 gfx12_opt_push_compute_sh_reg(R_00B848_COMPUTE_PGM_RSRC1,
531 SI_TRACKED_COMPUTE_PGM_RSRC1, config->rsrc1);
532 gfx12_opt_push_compute_sh_reg(R_00B84C_COMPUTE_PGM_RSRC2,
533 SI_TRACKED_COMPUTE_PGM_RSRC2, rsrc2);
534 gfx12_opt_push_compute_sh_reg(R_00B8A0_COMPUTE_PGM_RSRC3,
535 SI_TRACKED_COMPUTE_PGM_RSRC3, rsrc3);
536 gfx12_opt_push_compute_sh_reg(R_00B860_COMPUTE_TMPRING_SIZE,
537 SI_TRACKED_COMPUTE_TMPRING_SIZE, sctx->compute_tmpring_size);
538 if (config->scratch_bytes_per_wave) {
539 gfx12_opt_push_compute_sh_reg(R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
540 SI_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
541 sctx->compute_scratch_buffer->gpu_address >> 8);
542 gfx12_opt_push_compute_sh_reg(R_00B844_COMPUTE_DISPATCH_SCRATCH_BASE_HI,
543 SI_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_HI,
544 sctx->compute_scratch_buffer->gpu_address >> 40);
545 }
546 } else if (sctx->screen->info.has_set_sh_pairs_packed) {
547 unsigned rsrc3 = S_00B8A0_INST_PREF_SIZE_GFX11(si_get_shader_prefetch_size(shader));
548
549 gfx11_push_compute_sh_reg(R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
550 gfx11_opt_push_compute_sh_reg(R_00B848_COMPUTE_PGM_RSRC1,
551 SI_TRACKED_COMPUTE_PGM_RSRC1, config->rsrc1);
552 gfx11_opt_push_compute_sh_reg(R_00B84C_COMPUTE_PGM_RSRC2,
553 SI_TRACKED_COMPUTE_PGM_RSRC2, rsrc2);
554 gfx11_opt_push_compute_sh_reg(R_00B8A0_COMPUTE_PGM_RSRC3,
555 SI_TRACKED_COMPUTE_PGM_RSRC3, rsrc3);
556 gfx11_opt_push_compute_sh_reg(R_00B860_COMPUTE_TMPRING_SIZE,
557 SI_TRACKED_COMPUTE_TMPRING_SIZE, sctx->compute_tmpring_size);
558 if (config->scratch_bytes_per_wave) {
559 gfx11_opt_push_compute_sh_reg(R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
560 SI_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
561 sctx->compute_scratch_buffer->gpu_address >> 8);
562 gfx11_opt_push_compute_sh_reg(R_00B844_COMPUTE_DISPATCH_SCRATCH_BASE_HI,
563 SI_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_HI,
564 sctx->compute_scratch_buffer->gpu_address >> 40);
565 }
566 } else {
567 radeon_begin(cs);
568 radeon_set_sh_reg(R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
569 radeon_opt_set_sh_reg2(R_00B848_COMPUTE_PGM_RSRC1,
570 SI_TRACKED_COMPUTE_PGM_RSRC1,
571 config->rsrc1, rsrc2);
572 radeon_opt_set_sh_reg(R_00B860_COMPUTE_TMPRING_SIZE,
573 SI_TRACKED_COMPUTE_TMPRING_SIZE, sctx->compute_tmpring_size);
574
575 if (config->scratch_bytes_per_wave && sctx->screen->info.has_scratch_base_registers) {
576 radeon_opt_set_sh_reg2(R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
577 SI_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
578 sctx->compute_scratch_buffer->gpu_address >> 8,
579 sctx->compute_scratch_buffer->gpu_address >> 40);
580 }
581
582 if (sctx->gfx_level >= GFX11) {
583 radeon_opt_set_sh_reg(R_00B8A0_COMPUTE_PGM_RSRC3,
584 SI_TRACKED_COMPUTE_PGM_RSRC3,
585 S_00B8A0_INST_PREF_SIZE_GFX11(si_get_shader_prefetch_size(shader)));
586 }
587 radeon_end();
588 }
589
590 COMPUTE_DBG(sctx->screen,
591 "COMPUTE_PGM_RSRC1: 0x%08x "
592 "COMPUTE_PGM_RSRC2: 0x%08x\n",
593 config->rsrc1, config->rsrc2);
594
595 sctx->cs_shader_state.emitted_program = program;
596 sctx->cs_shader_state.offset = offset;
597 sctx->cs_shader_state.variable_shared_size = variable_shared_size;
598
599 *prefetch = true;
600 return true;
601 }
602
setup_scratch_rsrc_user_sgprs(struct si_context * sctx,const amd_kernel_code_t * code_object,unsigned user_sgpr)603 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
604 const amd_kernel_code_t *code_object, unsigned user_sgpr)
605 {
606 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
607 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
608
609 unsigned max_private_element_size =
610 AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
611
612 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
613 uint32_t scratch_dword1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
614
615 if (sctx->gfx_level >= GFX11)
616 scratch_dword1 |= S_008F04_SWIZZLE_ENABLE_GFX11(1);
617 else
618 scratch_dword1 |= S_008F04_SWIZZLE_ENABLE_GFX6(1);
619
620 /* Disable address clamping */
621 uint32_t scratch_dword2 = 0xffffffff;
622 uint32_t index_stride = sctx->cs_shader_state.program->shader.wave_size == 32 ? 2 : 3;
623 uint32_t scratch_dword3 = S_008F0C_INDEX_STRIDE(index_stride) | S_008F0C_ADD_TID_ENABLE(1);
624
625 if (sctx->gfx_level >= GFX9) {
626 assert(max_private_element_size == 1); /* only 4 bytes on GFX9 */
627 } else {
628 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
629
630 if (sctx->gfx_level < GFX8) {
631 /* BUF_DATA_FORMAT is ignored, but it cannot be
632 * BUF_DATA_FORMAT_INVALID. */
633 scratch_dword3 |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
634 }
635 }
636
637 radeon_begin(cs);
638 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 4);
639 radeon_emit(scratch_dword0);
640 radeon_emit(scratch_dword1);
641 radeon_emit(scratch_dword2);
642 radeon_emit(scratch_dword3);
643 radeon_end();
644 }
645
si_setup_user_sgprs_co_v2(struct si_context * sctx,const amd_kernel_code_t * code_object,const struct pipe_grid_info * info,uint64_t kernel_args_va)646 static void si_setup_user_sgprs_co_v2(struct si_context *sctx, const amd_kernel_code_t *code_object,
647 const struct pipe_grid_info *info, uint64_t kernel_args_va)
648 {
649 struct si_compute *program = sctx->cs_shader_state.program;
650 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
651
652 static const enum amd_code_property_mask_t workgroup_count_masks[] = {
653 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
654 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
655 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z};
656
657 unsigned i, user_sgpr = 0;
658 if (AMD_HSA_BITS_GET(code_object->code_properties,
659 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
660 if (code_object->workitem_private_segment_byte_size > 0) {
661 setup_scratch_rsrc_user_sgprs(sctx, code_object, user_sgpr);
662 }
663 user_sgpr += 4;
664 }
665
666 radeon_begin(cs);
667
668 if (AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
669 struct dispatch_packet dispatch;
670 unsigned dispatch_offset;
671 struct si_resource *dispatch_buf = NULL;
672 uint64_t dispatch_va;
673
674 /* Upload dispatch ptr */
675 memset(&dispatch, 0, sizeof(dispatch));
676
677 dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
678 dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
679 dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
680
681 dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
682 dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
683 dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
684
685 dispatch.group_segment_size =
686 util_cpu_to_le32(program->sel.info.base.shared_size + info->variable_shared_mem);
687
688 dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
689
690 u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch), 256, &dispatch, &dispatch_offset,
691 (struct pipe_resource **)&dispatch_buf);
692
693 if (!dispatch_buf) {
694 fprintf(stderr, "Error: Failed to allocate dispatch "
695 "packet.");
696 }
697 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, dispatch_buf,
698 RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER);
699
700 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
701
702 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 2);
703 radeon_emit(dispatch_va);
704 radeon_emit(S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) | S_008F04_STRIDE(0));
705
706 si_resource_reference(&dispatch_buf, NULL);
707 user_sgpr += 2;
708 }
709
710 if (AMD_HSA_BITS_GET(code_object->code_properties,
711 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
712 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 2);
713 radeon_emit(kernel_args_va);
714 radeon_emit(S_008F04_BASE_ADDRESS_HI(kernel_args_va >> 32) | S_008F04_STRIDE(0));
715 user_sgpr += 2;
716 }
717
718 for (i = 0; i < 3 && user_sgpr < 16; i++) {
719 if (code_object->code_properties & workgroup_count_masks[i]) {
720 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 1);
721 radeon_emit(info->grid[i]);
722 user_sgpr += 1;
723 }
724 }
725 radeon_end();
726 }
727
si_upload_compute_input(struct si_context * sctx,const amd_kernel_code_t * code_object,const struct pipe_grid_info * info)728 static bool si_upload_compute_input(struct si_context *sctx, const amd_kernel_code_t *code_object,
729 const struct pipe_grid_info *info)
730 {
731 struct si_compute *program = sctx->cs_shader_state.program;
732 struct si_resource *input_buffer = NULL;
733 uint32_t kernel_args_offset = 0;
734 uint32_t *kernel_args;
735 void *kernel_args_ptr;
736 uint64_t kernel_args_va;
737
738 u_upload_alloc(sctx->b.const_uploader, 0, program->input_size,
739 sctx->screen->info.tcc_cache_line_size, &kernel_args_offset,
740 (struct pipe_resource **)&input_buffer, &kernel_args_ptr);
741
742 if (unlikely(!kernel_args_ptr))
743 return false;
744
745 kernel_args = (uint32_t *)kernel_args_ptr;
746 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
747
748 memcpy(kernel_args, info->input, program->input_size);
749
750 for (unsigned i = 0; i < program->input_size / 4; i++) {
751 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i, kernel_args[i]);
752 }
753
754 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, input_buffer,
755 RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER);
756
757 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
758 si_resource_reference(&input_buffer, NULL);
759 return true;
760 }
761
si_setup_nir_user_data(struct si_context * sctx,const struct pipe_grid_info * info)762 static void si_setup_nir_user_data(struct si_context *sctx, const struct pipe_grid_info *info)
763 {
764 struct si_compute *program = sctx->cs_shader_state.program;
765 struct si_shader_selector *sel = &program->sel;
766 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
767 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 + 4 * SI_NUM_RESOURCE_SGPRS;
768 unsigned block_size_reg = grid_size_reg +
769 /* 12 bytes = 3 dwords. */
770 12 * sel->info.uses_grid_size;
771 unsigned cs_user_data_reg = block_size_reg + 4 * program->sel.info.uses_variable_block_size;
772
773 if (sel->info.uses_grid_size && info->indirect) {
774 for (unsigned i = 0; i < 3; ++i) {
775 si_cp_copy_data(sctx, &sctx->gfx_cs, COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i,
776 COPY_DATA_SRC_MEM, si_resource(info->indirect),
777 info->indirect_offset + 4 * i);
778 }
779 }
780
781 if (sctx->gfx_level >= GFX12) {
782 if (sel->info.uses_grid_size && !info->indirect) {
783 gfx12_push_compute_sh_reg(grid_size_reg, info->grid[0]);
784 gfx12_push_compute_sh_reg(grid_size_reg + 4, info->grid[1]);
785 gfx12_push_compute_sh_reg(grid_size_reg + 8, info->grid[2]);
786 }
787
788 if (sel->info.uses_variable_block_size) {
789 uint32_t value = info->block[0] | (info->block[1] << 10) | (info->block[2] << 20);
790 gfx12_push_compute_sh_reg(block_size_reg, value);
791 }
792
793 if (sel->info.base.cs.user_data_components_amd) {
794 unsigned num = sel->info.base.cs.user_data_components_amd;
795 for (unsigned i = 0; i < num; i++)
796 gfx12_push_compute_sh_reg(cs_user_data_reg + i * 4, sctx->cs_user_data[i]);
797 }
798 } else if (sctx->screen->info.has_set_sh_pairs_packed) {
799 if (sel->info.uses_grid_size && !info->indirect) {
800 gfx11_push_compute_sh_reg(grid_size_reg, info->grid[0]);
801 gfx11_push_compute_sh_reg(grid_size_reg + 4, info->grid[1]);
802 gfx11_push_compute_sh_reg(grid_size_reg + 8, info->grid[2]);
803 }
804
805 if (sel->info.uses_variable_block_size) {
806 uint32_t value = info->block[0] | (info->block[1] << 10) | (info->block[2] << 20);
807 gfx11_push_compute_sh_reg(block_size_reg, value);
808 }
809
810 if (sel->info.base.cs.user_data_components_amd) {
811 unsigned num = sel->info.base.cs.user_data_components_amd;
812 for (unsigned i = 0; i < num; i++)
813 gfx11_push_compute_sh_reg(cs_user_data_reg + i * 4, sctx->cs_user_data[i]);
814 }
815 } else {
816 radeon_begin(cs);
817
818 if (sel->info.uses_grid_size && !info->indirect) {
819 radeon_set_sh_reg_seq(grid_size_reg, 3);
820 radeon_emit(info->grid[0]);
821 radeon_emit(info->grid[1]);
822 radeon_emit(info->grid[2]);
823 }
824
825 if (sel->info.uses_variable_block_size) {
826 uint32_t value = info->block[0] | (info->block[1] << 10) | (info->block[2] << 20);
827 radeon_set_sh_reg(block_size_reg, value);
828 }
829
830 if (sel->info.base.cs.user_data_components_amd) {
831 unsigned num = sel->info.base.cs.user_data_components_amd;
832 radeon_set_sh_reg_seq(cs_user_data_reg, num);
833 radeon_emit_array(sctx->cs_user_data, num);
834 }
835 radeon_end();
836 }
837 }
838
si_get_2d_interleave_size(const struct pipe_grid_info * info,unsigned * log_x,unsigned * log_y)839 static bool si_get_2d_interleave_size(const struct pipe_grid_info *info,
840 unsigned *log_x, unsigned *log_y)
841 {
842 /* The following code produces this behavior:
843 *
844 * WG size | WG block/SE | Thread block/SE
845 * ( 1, 32) = 32 | (16, 1) = 16 | ( 16, 32) = 512
846 * ( 2, 16) = 32 | ( 8, 2) = 16 | ( 16, 32) = 512
847 * ( 2, 32) = 64 | (16, 1) = 16 | ( 32, 32) = 1024
848 * ( 4, 8) = 32 | ( 4, 4) = 16 | ( 16, 32) = 512
849 * ( 4, 16) = 64 | ( 8, 2) = 16 | ( 32, 32) = 1024
850 * ( 4, 32) = 128 | ( 8, 1) = 8 | ( 32, 32) = 1024
851 * ( 8, 4) = 32 | ( 2, 8) = 16 | ( 16, 32) = 512
852 * ( 8, 8) = 64 | ( 4, 4) = 16 | ( 32, 32) = 1024
853 * ( 8, 16) = 128 | ( 4, 2) = 8 | ( 32, 32) = 1024
854 * ( 8, 32) = 256 | ( 4, 1) = 4 | ( 32, 32) = 1024
855 * (16, 2) = 32 | ( 1, 16) = 16 | ( 16, 32) = 512
856 * (16, 4) = 64 | ( 2, 8) = 16 | ( 32, 32) = 1024
857 * (16, 8) = 128 | ( 2, 4) = 8 | ( 32, 32) = 1024
858 * (16, 16) = 256 | ( 2, 2) = 4 | ( 32, 32) = 1024
859 * (16, 32) = 512 | ( 2, 1) = 2 | ( 32, 32) = 1024
860 * (32, 1) = 32 | ( 1, 16) = 16 | ( 32, 16) = 512
861 * (32, 2) = 64 | ( 1, 16) = 16 | ( 32, 32) = 1024
862 * (32, 4) = 128 | ( 1, 8) = 8 | ( 32, 32) = 1024
863 * (32, 8) = 256 | ( 1, 4) = 4 | ( 32, 32) = 1024
864 * (32, 16) = 512 | ( 1, 2) = 2 | ( 32, 32) = 1024
865 *
866 * For 3D workgroups, the total 2D thread count is divided by Z.
867 * Example with Z=8, showing only a 2D slice of the grid:
868 *
869 * WG size | WG block/SE | Thread block/SE
870 * ( 1, 32) = 32 | ( 4, 1) = 4 | ( 4, 32) = 128
871 * ( 2, 16) = 32 | ( 4, 1) = 4 | ( 8, 16) = 128
872 * ( 2, 32) = 64 | ( 2, 1) = 2 | ( 4, 32) = 128
873 * ( 4, 8) = 32 | ( 2, 2) = 4 | ( 8, 16) = 128
874 * ( 4, 16) = 64 | ( 2, 1) = 2 | ( 8, 16) = 128
875 * ( 8, 4) = 32 | ( 1, 4) = 4 | ( 8, 16) = 128
876 * ( 8, 8) = 64 | ( 1, 2) = 2 | ( 8, 16) = 128
877 * (16, 2) = 32 | ( 1, 4) = 4 | ( 16, 8) = 128
878 * (16, 4) = 64 | ( 1, 2) = 2 | ( 16, 8) = 128
879 * (32, 1) = 32 | ( 1, 4) = 4 | ( 32, 4) = 128
880 * (32, 2) = 64 | ( 1, 2) = 2 | ( 32, 4) = 128
881 *
882 * It tries to find a WG block size that corresponds to (N, N) or (N, 2*N) threads,
883 * but it's limited by the maximum WGs/SE, which is 16, and the number of threads/SE,
884 * which we set to 1024.
885 */
886 unsigned max_threads_per_se = 1024;
887 unsigned threads_per_threadgroup = info->block[0] * info->block[1] * info->block[2];
888 unsigned workgroups_per_se = MIN2(max_threads_per_se / threads_per_threadgroup, 16);
889 unsigned log_workgroups_per_se = util_logbase2(workgroups_per_se);
890
891 if (!log_workgroups_per_se)
892 return false;
893
894 assert(log_workgroups_per_se <= 4);
895
896 *log_x = MIN2(log_workgroups_per_se, 4);
897 *log_y = log_workgroups_per_se - *log_x;
898
899 while (*log_x > 0 && *log_y < 4 &&
900 info->block[0] * (1 << *log_x) > info->block[1] * (1 << *log_y)) {
901 (*log_x)--;
902 (*log_y)++;
903 }
904
905 assert(*log_x + *log_y <= 4);
906 return true;
907 }
908
si_emit_dispatch_packets(struct si_context * sctx,const struct pipe_grid_info * info)909 static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_grid_info *info)
910 {
911 struct si_screen *sscreen = sctx->screen;
912 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
913 bool render_cond_bit = sctx->render_cond_enabled;
914 unsigned threads_per_threadgroup = info->block[0] * info->block[1] * info->block[2];
915 unsigned waves_per_threadgroup =
916 DIV_ROUND_UP(threads_per_threadgroup, sctx->cs_shader_state.program->shader.wave_size);
917 unsigned threadgroups_per_cu = 1;
918
919 if (sctx->gfx_level >= GFX10 && waves_per_threadgroup == 1)
920 threadgroups_per_cu = 2;
921
922 if (unlikely(sctx->sqtt_enabled)) {
923 if (info->indirect) {
924 si_sqtt_write_event_marker(sctx, &sctx->gfx_cs,
925 EventCmdDispatchIndirect,
926 UINT_MAX, UINT_MAX, UINT_MAX);
927 } else {
928 si_write_event_with_dims_marker(sctx, &sctx->gfx_cs,
929 EventCmdDispatch,
930 info->grid[0], info->grid[1], info->grid[2]);
931 }
932 }
933
934 radeon_begin(cs);
935 unsigned compute_resource_limits =
936 ac_get_compute_resource_limits(&sscreen->info, waves_per_threadgroup,
937 sctx->cs_max_waves_per_sh,
938 threadgroups_per_cu);
939
940 if (sctx->gfx_level >= GFX12) {
941 gfx12_opt_push_compute_sh_reg(R_00B854_COMPUTE_RESOURCE_LIMITS,
942 SI_TRACKED_COMPUTE_RESOURCE_LIMITS,
943 compute_resource_limits);
944 } else if (sctx->screen->info.has_set_sh_pairs_packed) {
945 gfx11_opt_push_compute_sh_reg(R_00B854_COMPUTE_RESOURCE_LIMITS,
946 SI_TRACKED_COMPUTE_RESOURCE_LIMITS,
947 compute_resource_limits);
948 } else {
949 radeon_opt_set_sh_reg(R_00B854_COMPUTE_RESOURCE_LIMITS,
950 SI_TRACKED_COMPUTE_RESOURCE_LIMITS,
951 compute_resource_limits);
952 }
953
954 unsigned dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) | S_00B800_FORCE_START_AT_000(1) |
955 /* If the KMD allows it (there is a KMD hw register for it),
956 * allow launching waves out-of-order. (same as Vulkan)
957 * Not available in gfx940.
958 */
959 S_00B800_ORDER_MODE(!sctx->cs_shader_state.program->sel.info.uses_atomic_ordered_add &&
960 sctx->gfx_level >= GFX7 &&
961 (sctx->family < CHIP_GFX940 || sctx->screen->info.has_graphics)) |
962 S_00B800_CS_W32_EN(sctx->cs_shader_state.program->shader.wave_size == 32);
963
964 const uint *last_block = info->last_block;
965 bool partial_block_en = last_block[0] || last_block[1] || last_block[2];
966 uint32_t num_threads[3];
967
968 if (sctx->gfx_level >= GFX12) {
969 num_threads[0] = S_00B81C_NUM_THREAD_FULL_GFX12(info->block[0]);
970 num_threads[1] = S_00B820_NUM_THREAD_FULL_GFX12(info->block[1]);
971 } else {
972 num_threads[0] = S_00B81C_NUM_THREAD_FULL_GFX6(info->block[0]);
973 num_threads[1] = S_00B820_NUM_THREAD_FULL_GFX6(info->block[1]);
974 }
975 num_threads[2] = S_00B824_NUM_THREAD_FULL(info->block[2]);
976
977 if (partial_block_en) {
978 unsigned partial[3];
979
980 /* If no partial_block, these should be an entire block size, not 0. */
981 partial[0] = last_block[0] ? last_block[0] : info->block[0];
982 partial[1] = last_block[1] ? last_block[1] : info->block[1];
983 partial[2] = last_block[2] ? last_block[2] : info->block[2];
984
985 num_threads[0] |= S_00B81C_NUM_THREAD_PARTIAL(partial[0]);
986 num_threads[1] |= S_00B820_NUM_THREAD_PARTIAL(partial[1]);
987 num_threads[2] |= S_00B824_NUM_THREAD_PARTIAL(partial[2]);
988
989 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
990 }
991
992 if (sctx->gfx_level >= GFX12) {
993 /* Set PING_PONG_EN for every other dispatch.
994 * Only allowed on a gfx queue, and PARTIAL_TG_EN and USE_THREAD_DIMENSIONS must be 0.
995 */
996 if (sctx->has_graphics && !partial_block_en &&
997 !sctx->cs_shader_state.program->sel.info.uses_atomic_ordered_add) {
998 dispatch_initiator |= S_00B800_PING_PONG_EN(sctx->compute_ping_pong_launch);
999 sctx->compute_ping_pong_launch ^= 1;
1000 }
1001
1002 /* Thread tiling within a workgroup. */
1003 switch (sctx->cs_shader_state.program->shader.selector->info.base.derivative_group) {
1004 case DERIVATIVE_GROUP_LINEAR:
1005 break;
1006 case DERIVATIVE_GROUP_QUADS:
1007 num_threads[0] |= S_00B81C_INTERLEAVE_BITS_X(1); /* 2x2 */
1008 num_threads[1] |= S_00B820_INTERLEAVE_BITS_Y(1);
1009 break;
1010 case DERIVATIVE_GROUP_NONE:
1011 /* These are the only legal combinations. */
1012 if (info->block[0] % 8 == 0 && info->block[1] % 8 == 0) {
1013 num_threads[0] |= S_00B81C_INTERLEAVE_BITS_X(3); /* 8x8 */
1014 num_threads[1] |= S_00B820_INTERLEAVE_BITS_Y(3);
1015 } else if (info->block[0] % 4 == 0 && info->block[1] % 8 == 0) {
1016 num_threads[0] |= S_00B81C_INTERLEAVE_BITS_X(2); /* 4x8 */
1017 num_threads[1] |= S_00B820_INTERLEAVE_BITS_Y(3);
1018 } else if (info->block[0] % 4 == 0 && info->block[1] % 4 == 0) {
1019 num_threads[0] |= S_00B81C_INTERLEAVE_BITS_X(2); /* 4x4 */
1020 num_threads[1] |= S_00B820_INTERLEAVE_BITS_Y(2);
1021 } else if (info->block[0] % 2 == 0 && info->block[1] % 2 == 0) {
1022 num_threads[0] |= S_00B81C_INTERLEAVE_BITS_X(1); /* 2x2 */
1023 num_threads[1] |= S_00B820_INTERLEAVE_BITS_Y(1);
1024 }
1025 break;
1026 }
1027
1028 /* How many threads should go to 1 SE before moving onto the next if INTERLEAVE_2D_EN == 0.
1029 * Only these values are valid: 0 (disabled), 64, 128, 256, 512
1030 * 64 = RT, 256 = non-RT (run benchmarks to be sure)
1031 */
1032 unsigned dispatch_interleave = S_00B8BC_INTERLEAVE_1D(256);
1033 unsigned log_x, log_y;
1034
1035 /* Launch a 2D subgrid on each SE instead of a 1D subgrid. If enabled, INTERLEAVE_1D is
1036 * ignored and each SE gets 1 subgrid up to a certain number of threads.
1037 *
1038 * Constraints:
1039 * - Only supported by the gfx queue.
1040 * - Max 16 workgroups per SE can be launched, max 4 in each dimension.
1041 * - PARTIAL_TG_EN, USE_THREAD_DIMENSIONS, and ORDERED_APPEND_ENBL must be 0.
1042 * - COMPUTE_START_X/Y are in units of 2D subgrids, not workgroups
1043 * (program COMPUTE_START_X to start_x >> log_x, COMPUTE_START_Y to start_y >> log_y).
1044 */
1045 if (sctx->has_graphics && !partial_block_en &&
1046 (info->indirect || info->grid[1] >= 4) && MIN2(info->block[0], info->block[1]) >= 4 &&
1047 si_get_2d_interleave_size(info, &log_x, &log_y)) {
1048 dispatch_interleave = S_00B8BC_INTERLEAVE_1D(1) || /* 1D is disabled */
1049 S_00B8BC_INTERLEAVE_2D_X_SIZE(log_x) |
1050 S_00B8BC_INTERLEAVE_2D_Y_SIZE(log_y);
1051 dispatch_initiator |= S_00B800_INTERLEAVE_2D_EN(1);
1052 }
1053
1054 if (sctx->has_graphics) {
1055 radeon_opt_set_sh_reg_idx(R_00B8BC_COMPUTE_DISPATCH_INTERLEAVE,
1056 SI_TRACKED_COMPUTE_DISPATCH_INTERLEAVE, 2, dispatch_interleave);
1057 } else {
1058 gfx12_opt_push_compute_sh_reg(R_00B8BC_COMPUTE_DISPATCH_INTERLEAVE,
1059 SI_TRACKED_COMPUTE_DISPATCH_INTERLEAVE, dispatch_interleave);
1060 }
1061 }
1062
1063 if (sctx->gfx_level >= GFX12) {
1064 gfx12_opt_push_compute_sh_reg(R_00B81C_COMPUTE_NUM_THREAD_X,
1065 SI_TRACKED_COMPUTE_NUM_THREAD_X, num_threads[0]);
1066 gfx12_opt_push_compute_sh_reg(R_00B820_COMPUTE_NUM_THREAD_Y,
1067 SI_TRACKED_COMPUTE_NUM_THREAD_Y, num_threads[1]);
1068 gfx12_opt_push_compute_sh_reg(R_00B824_COMPUTE_NUM_THREAD_Z,
1069 SI_TRACKED_COMPUTE_NUM_THREAD_Z, num_threads[2]);
1070 } else if (sctx->screen->info.has_set_sh_pairs_packed) {
1071 gfx11_opt_push_compute_sh_reg(R_00B81C_COMPUTE_NUM_THREAD_X,
1072 SI_TRACKED_COMPUTE_NUM_THREAD_X, num_threads[0]);
1073 gfx11_opt_push_compute_sh_reg(R_00B820_COMPUTE_NUM_THREAD_Y,
1074 SI_TRACKED_COMPUTE_NUM_THREAD_Y, num_threads[1]);
1075 gfx11_opt_push_compute_sh_reg(R_00B824_COMPUTE_NUM_THREAD_Z,
1076 SI_TRACKED_COMPUTE_NUM_THREAD_Z, num_threads[2]);
1077 } else {
1078 radeon_opt_set_sh_reg3(R_00B81C_COMPUTE_NUM_THREAD_X,
1079 SI_TRACKED_COMPUTE_NUM_THREAD_X,
1080 num_threads[0], num_threads[1], num_threads[2]);
1081 }
1082
1083 if (sctx->gfx_level >= GFX12 || sctx->screen->info.has_set_sh_pairs_packed) {
1084 radeon_end();
1085 si_emit_buffered_compute_sh_regs(sctx);
1086 radeon_begin_again(cs);
1087 }
1088
1089 if (info->indirect) {
1090 uint64_t base_va = si_resource(info->indirect)->gpu_address;
1091
1092 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(info->indirect),
1093 RADEON_USAGE_READ | RADEON_PRIO_DRAW_INDIRECT);
1094
1095 radeon_emit(PKT3(PKT3_SET_BASE, 2, 0) | PKT3_SHADER_TYPE_S(1));
1096 radeon_emit(1);
1097 radeon_emit(base_va);
1098 radeon_emit(base_va >> 32);
1099
1100 unsigned pkt = PKT3_DISPATCH_INDIRECT;
1101
1102 if (sctx->gfx_level >= GFX12 && G_00B800_INTERLEAVE_2D_EN(dispatch_initiator))
1103 pkt = PKT3_DISPATCH_INDIRECT_INTERLEAVED;
1104
1105 radeon_emit(PKT3(pkt, 1, render_cond_bit) | PKT3_SHADER_TYPE_S(1));
1106 radeon_emit(info->indirect_offset);
1107 radeon_emit(dispatch_initiator);
1108 } else {
1109 unsigned pkt = PKT3_DISPATCH_DIRECT;
1110
1111 if (sctx->gfx_level >= GFX12 && G_00B800_INTERLEAVE_2D_EN(dispatch_initiator))
1112 pkt = PKT3_DISPATCH_DIRECT_INTERLEAVED;
1113
1114 radeon_emit(PKT3(pkt, 3, render_cond_bit) | PKT3_SHADER_TYPE_S(1));
1115 radeon_emit(info->grid[0]);
1116 radeon_emit(info->grid[1]);
1117 radeon_emit(info->grid[2]);
1118 radeon_emit(dispatch_initiator);
1119 }
1120
1121 if (unlikely(sctx->sqtt_enabled && sctx->gfx_level >= GFX9))
1122 radeon_event_write(V_028A90_THREAD_TRACE_MARKER);
1123
1124 radeon_end();
1125 }
1126
si_check_needs_implicit_sync(struct si_context * sctx,uint32_t usage)1127 static bool si_check_needs_implicit_sync(struct si_context *sctx, uint32_t usage)
1128 {
1129 /* If the compute shader is going to read from a texture/image written by a
1130 * previous draw, we must wait for its completion before continuing.
1131 * Buffers and image stores (from the draw) are not taken into consideration
1132 * because that's the app responsibility.
1133 *
1134 * The OpenGL 4.6 spec says:
1135 *
1136 * buffer object and texture stores performed by shaders are not
1137 * automatically synchronized
1138 *
1139 * TODO: Bindless textures are not handled, and thus are not synchronized.
1140 */
1141 struct si_shader_info *info = &sctx->cs_shader_state.program->sel.info;
1142 struct si_samplers *samplers = &sctx->samplers[PIPE_SHADER_COMPUTE];
1143 unsigned mask = samplers->enabled_mask & info->base.textures_used[0];
1144
1145 while (mask) {
1146 int i = u_bit_scan(&mask);
1147 struct si_sampler_view *sview = (struct si_sampler_view *)samplers->views[i];
1148
1149 struct si_resource *res = si_resource(sview->base.texture);
1150 if (sctx->ws->cs_is_buffer_referenced(&sctx->gfx_cs, res->buf, usage))
1151 return true;
1152 }
1153
1154 struct si_images *images = &sctx->images[PIPE_SHADER_COMPUTE];
1155 mask = u_bit_consecutive(0, info->base.num_images) & images->enabled_mask;
1156
1157 while (mask) {
1158 int i = u_bit_scan(&mask);
1159 struct pipe_image_view *sview = &images->views[i];
1160
1161 struct si_resource *res = si_resource(sview->resource);
1162 if (sctx->ws->cs_is_buffer_referenced(&sctx->gfx_cs, res->buf, usage))
1163 return true;
1164 }
1165 return false;
1166 }
1167
si_launch_grid(struct pipe_context * ctx,const struct pipe_grid_info * info)1168 static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info *info)
1169 {
1170 struct si_context *sctx = (struct si_context *)ctx;
1171 struct si_screen *sscreen = sctx->screen;
1172 struct si_compute *program = sctx->cs_shader_state.program;
1173 const amd_kernel_code_t *code_object = si_compute_get_code_object(program, info->pc);
1174 int i;
1175 bool cs_regalloc_hang = sscreen->info.has_cs_regalloc_hang_bug &&
1176 info->block[0] * info->block[1] * info->block[2] > 256;
1177
1178 if (cs_regalloc_hang) {
1179 sctx->barrier_flags |= SI_BARRIER_SYNC_PS | SI_BARRIER_SYNC_CS;
1180 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
1181 }
1182
1183 if (program->ir_type != PIPE_SHADER_IR_NATIVE && program->shader.compilation_failed)
1184 return;
1185
1186 si_check_dirty_buffers_textures(sctx);
1187
1188 if (sctx->has_graphics) {
1189 if (sctx->num_draw_calls_sh_coherent.with_cb != sctx->num_draw_calls ||
1190 sctx->num_draw_calls_sh_coherent.with_db != sctx->num_draw_calls) {
1191 bool sync_cb = sctx->force_shader_coherency.with_cb ||
1192 si_check_needs_implicit_sync(sctx, RADEON_USAGE_CB_NEEDS_IMPLICIT_SYNC);
1193 bool sync_db = sctx->gfx_level >= GFX12 &&
1194 (sctx->force_shader_coherency.with_db ||
1195 si_check_needs_implicit_sync(sctx, RADEON_USAGE_DB_NEEDS_IMPLICIT_SYNC));
1196
1197 si_fb_barrier_after_rendering(sctx,
1198 (sync_cb ? SI_FB_BARRIER_SYNC_CB : 0) |
1199 (sync_db ? SI_FB_BARRIER_SYNC_DB : 0));
1200
1201 if (sync_cb)
1202 sctx->num_draw_calls_sh_coherent.with_cb = sctx->num_draw_calls;
1203
1204 if (sync_db)
1205 sctx->num_draw_calls_sh_coherent.with_db = sctx->num_draw_calls;
1206 }
1207
1208 if (sctx->gfx_level < GFX11)
1209 gfx6_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
1210 else if (sctx->gfx_level < GFX12)
1211 gfx11_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
1212 }
1213
1214 if (info->indirect) {
1215 /* Indirect buffers are read through L2 on GFX9-GFX11, but not other hw. */
1216 if ((sctx->gfx_level <= GFX8 || sscreen->info.cp_sdma_ge_use_system_memory_scope) &&
1217 si_resource(info->indirect)->L2_cache_dirty) {
1218 sctx->barrier_flags |= SI_BARRIER_WB_L2 | SI_BARRIER_PFP_SYNC_ME;
1219 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
1220 si_resource(info->indirect)->L2_cache_dirty = false;
1221 }
1222 }
1223
1224 si_need_gfx_cs_space(sctx, 0);
1225
1226 /* If we're using a secure context, determine if cs must be secure or not */
1227 if (unlikely(radeon_uses_secure_bos(sctx->ws))) {
1228 bool secure = si_compute_resources_check_encrypted(sctx);
1229 if (secure != sctx->ws->cs_is_secure(&sctx->gfx_cs)) {
1230 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW |
1231 RADEON_FLUSH_TOGGLE_SECURE_SUBMISSION,
1232 NULL);
1233 }
1234 }
1235
1236 if (u_trace_perfetto_active(&sctx->ds.trace_context))
1237 trace_si_begin_compute(&sctx->trace);
1238
1239 if (sctx->bo_list_add_all_compute_resources)
1240 si_compute_resources_add_all_to_bo_list(sctx);
1241
1242 /* Skipping setting redundant registers on compute queues breaks compute. */
1243 if (!sctx->has_graphics) {
1244 BITSET_CLEAR_RANGE(sctx->tracked_regs.reg_saved_mask,
1245 SI_FIRST_TRACKED_OTHER_REG, SI_NUM_ALL_TRACKED_REGS - 1);
1246 }
1247
1248 /* First emit registers. */
1249 bool prefetch;
1250 if (!si_switch_compute_shader(sctx, program, &program->shader, code_object, info->pc, &prefetch,
1251 info->variable_shared_mem))
1252 return;
1253
1254 si_emit_compute_shader_pointers(sctx);
1255
1256 if (program->ir_type == PIPE_SHADER_IR_NATIVE &&
1257 unlikely(!si_upload_compute_input(sctx, code_object, info)))
1258 return;
1259
1260 /* Global buffers */
1261 for (i = 0; i < sctx->max_global_buffers; i++) {
1262 struct si_resource *buffer = si_resource(sctx->global_buffers[i]);
1263 if (!buffer) {
1264 continue;
1265 }
1266 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, buffer,
1267 RADEON_USAGE_READWRITE | RADEON_PRIO_SHADER_RW_BUFFER);
1268 }
1269
1270 /* Registers that are not read from memory should be set before this: */
1271 si_emit_barrier_direct(sctx);
1272
1273 if (sctx->has_graphics && si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
1274 sctx->atoms.s.render_cond.emit(sctx, -1);
1275 si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
1276 }
1277
1278 /* Prefetch the compute shader to L2. */
1279 if (sctx->gfx_level >= GFX7 && sctx->screen->info.has_cp_dma && prefetch)
1280 si_cp_dma_prefetch(sctx, &program->shader.bo->b.b, 0, program->shader.bo->b.b.width0);
1281
1282 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
1283 si_setup_nir_user_data(sctx, info);
1284
1285 si_emit_dispatch_packets(sctx, info);
1286
1287 if (unlikely(sctx->current_saved_cs)) {
1288 si_trace_emit(sctx);
1289 si_log_compute_state(sctx, sctx->log);
1290 }
1291
1292 if (sctx->gfx_level < GFX12) {
1293 /* Mark displayable DCC as dirty for bound images. */
1294 unsigned display_dcc_store_mask = sctx->images[PIPE_SHADER_COMPUTE].display_dcc_store_mask &
1295 BITFIELD_MASK(program->sel.info.base.num_images);
1296 while (display_dcc_store_mask) {
1297 struct si_texture *tex = (struct si_texture *)
1298 sctx->images[PIPE_SHADER_COMPUTE].views[u_bit_scan(&display_dcc_store_mask)].resource;
1299
1300 si_mark_display_dcc_dirty(sctx, tex);
1301 }
1302
1303 /* TODO: Bindless images don't set displayable_dcc_dirty after image stores. */
1304 }
1305
1306 sctx->compute_is_busy = true;
1307 sctx->num_compute_calls++;
1308
1309 if (u_trace_perfetto_active(&sctx->ds.trace_context))
1310 trace_si_end_compute(&sctx->trace, info->grid[0], info->grid[1], info->grid[2]);
1311
1312 if (cs_regalloc_hang) {
1313 sctx->barrier_flags |= SI_BARRIER_SYNC_CS;
1314 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
1315 }
1316 }
1317
si_destroy_compute(struct si_compute * program)1318 void si_destroy_compute(struct si_compute *program)
1319 {
1320 struct si_shader_selector *sel = &program->sel;
1321
1322 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
1323 util_queue_drop_job(&sel->screen->shader_compiler_queue, &sel->ready);
1324 util_queue_fence_destroy(&sel->ready);
1325 }
1326
1327 si_shader_destroy(&program->shader);
1328 ralloc_free(program->sel.nir);
1329 simple_mtx_destroy(&sel->mutex);
1330 FREE(program);
1331 }
1332
si_delete_compute_state(struct pipe_context * ctx,void * state)1333 static void si_delete_compute_state(struct pipe_context *ctx, void *state)
1334 {
1335 struct si_compute *program = (struct si_compute *)state;
1336 struct si_context *sctx = (struct si_context *)ctx;
1337
1338 if (!state)
1339 return;
1340
1341 if (program == sctx->cs_shader_state.program)
1342 sctx->cs_shader_state.program = NULL;
1343
1344 if (program == sctx->cs_shader_state.emitted_program)
1345 sctx->cs_shader_state.emitted_program = NULL;
1346
1347 si_compute_reference(&program, NULL);
1348 }
1349
si_set_compute_resources(struct pipe_context * ctx_,unsigned start,unsigned count,struct pipe_surface ** surfaces)1350 static void si_set_compute_resources(struct pipe_context *ctx_, unsigned start, unsigned count,
1351 struct pipe_surface **surfaces)
1352 {
1353 }
1354
si_init_compute_functions(struct si_context * sctx)1355 void si_init_compute_functions(struct si_context *sctx)
1356 {
1357 sctx->b.create_compute_state = si_create_compute_state;
1358 sctx->b.delete_compute_state = si_delete_compute_state;
1359 sctx->b.bind_compute_state = si_bind_compute_state;
1360 sctx->b.get_compute_state_info = si_get_compute_state_info;
1361 sctx->b.set_compute_resources = si_set_compute_resources;
1362 sctx->b.set_global_binding = si_set_global_binding;
1363 sctx->b.launch_grid = si_launch_grid;
1364
1365 #if 0 /* test for si_get_2d_interleave_size */
1366 static bool visited = false;
1367 if (visited)
1368 return;
1369
1370 visited = true;
1371 struct pipe_grid_info info = {};
1372 info.grid[0] = info.grid[1] = info.grid[2] = 1024;
1373 info.block[2] = 1;
1374
1375 for (unsigned block_3d = 0; block_3d < 2; block_3d++) {
1376 printf(" WG size | WG block/SE | Thread block/SE\n");
1377
1378 for (unsigned x = 1; x <= 32; x *= 2) {
1379 for (unsigned y = 1; y <= 32; y *= 2) {
1380 info.block[0] = x;
1381 info.block[1] = y;
1382 info.block[2] = block_3d ? 8 : 1;
1383
1384 if ((x * y) % 32)
1385 continue;
1386
1387 unsigned log_x, log_y;
1388 if (!si_get_2d_interleave_size(&info, &log_x, &log_y))
1389 continue;
1390
1391 printf(" (%2u, %2u) = %3u | (%2u, %2u) = %2u | (%3u,%3u) = %u\n",
1392 info.block[0], info.block[1], info.block[0] * info.block[1],
1393 1 << log_x, 1 << log_y, (1 << log_x) * (1 << log_y),
1394 info.block[0] * (1 << log_x), info.block[1] * (1 << log_y),
1395 info.block[0] * (1 << log_x) * info.block[1] * (1 << log_y));
1396 }
1397 }
1398 }
1399 #endif
1400 }
1401