1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
7 #if AMD_LLVM_AVAILABLE
8 #include "ac_llvm_util.h"
9 #endif
10
11 #include "ac_nir.h"
12 #include "ac_shader_util.h"
13 #include "compiler/nir/nir_serialize.h"
14 #include "nir/tgsi_to_nir.h"
15 #include "si_build_pm4.h"
16 #include "sid.h"
17 #include "util/crc32.h"
18 #include "util/disk_cache.h"
19 #include "util/hash_table.h"
20 #include "util/mesa-sha1.h"
21 #include "util/u_async_debug.h"
22 #include "util/u_math.h"
23 #include "util/u_memory.h"
24 #include "util/u_prim.h"
25 #include "tgsi/tgsi_from_mesa.h"
26
27 static void si_update_tess_in_out_patch_vertices(struct si_context *sctx);
28
si_determine_wave_size(struct si_screen * sscreen,struct si_shader * shader)29 unsigned si_determine_wave_size(struct si_screen *sscreen, struct si_shader *shader)
30 {
31 struct si_shader_info *info = &shader->selector->info;
32 gl_shader_stage stage = shader->selector->stage;
33
34 struct si_shader_selector *prev_sel = NULL;
35 if (stage == MESA_SHADER_TESS_CTRL)
36 prev_sel = shader->key.ge.part.tcs.ls;
37 else if (stage == MESA_SHADER_GEOMETRY)
38 prev_sel = shader->key.ge.part.gs.es;
39
40 if (sscreen->info.gfx_level < GFX10)
41 return 64;
42
43 /* Legacy GS only supports Wave64. */
44 if ((stage == MESA_SHADER_VERTEX && shader->key.ge.as_es && !shader->key.ge.as_ngg) ||
45 (stage == MESA_SHADER_TESS_EVAL && shader->key.ge.as_es && !shader->key.ge.as_ngg) ||
46 (stage == MESA_SHADER_GEOMETRY && !shader->key.ge.as_ngg))
47 return 64;
48
49 /* For KHR_shader_subgroup which require a constant subgroup size known by user. */
50 if (info->base.subgroup_size == SUBGROUP_SIZE_API_CONSTANT ||
51 (prev_sel && prev_sel->info.base.subgroup_size == SUBGROUP_SIZE_API_CONSTANT))
52 return 64;
53
54 /* Workgroup sizes that are not divisible by 64 use Wave32. */
55 if (stage == MESA_SHADER_COMPUTE && !info->base.workgroup_size_variable &&
56 (info->base.workgroup_size[0] *
57 info->base.workgroup_size[1] *
58 info->base.workgroup_size[2]) % 64 != 0)
59 return 32;
60
61 /* AMD_DEBUG wave flags override everything else. */
62 if (sscreen->debug_flags &
63 (stage == MESA_SHADER_COMPUTE ? DBG(W32_CS) :
64 stage == MESA_SHADER_FRAGMENT ? DBG(W32_PS) : DBG(W32_GE)))
65 return 32;
66
67 if (sscreen->debug_flags &
68 (stage == MESA_SHADER_COMPUTE ? DBG(W64_CS) :
69 stage == MESA_SHADER_FRAGMENT ? DBG(W64_PS) : DBG(W64_GE)))
70 return 64;
71
72 /* Shader profiles. */
73 if (info->options & SI_PROFILE_WAVE32)
74 return 32;
75
76 if (info->options & SI_PROFILE_GFX10_WAVE64 &&
77 (sscreen->info.gfx_level == GFX10 || sscreen->info.gfx_level == GFX10_3))
78 return 64;
79
80 /* Gfx10: Pixel shaders without interp instructions don't suffer from reduced interpolation
81 * performance in Wave32, so use Wave32. This helps Piano and Voloplosion.
82 *
83 * Gfx11: Prefer Wave64 to take advantage of doubled VALU performance.
84 */
85 if (sscreen->info.gfx_level < GFX11 && stage == MESA_SHADER_FRAGMENT && !info->num_inputs)
86 return 32;
87
88 /* Gfx10: There are a few very rare cases where VS is better with Wave32, and there are no
89 * known cases where Wave64 is better.
90 *
91 * Wave32 is disabled for GFX10 when culling is active as a workaround for #6457. I don't
92 * know why this helps.
93 *
94 * Gfx11: Prefer Wave64 because it's slightly better than Wave32.
95 */
96 if (stage <= MESA_SHADER_GEOMETRY &&
97 (sscreen->info.gfx_level == GFX10 || sscreen->info.gfx_level == GFX10_3) &&
98 !(sscreen->info.gfx_level == GFX10 && si_shader_culling_enabled(shader)))
99 return 32;
100
101 /* Divergent loops in Wave64 can end up having too many iterations in one half of the wave
102 * while the other half is idling but occupying VGPRs, preventing other waves from launching.
103 * Wave32 eliminates the idling half to allow the next wave to start.
104 *
105 * Gfx11: Wave32 continues to be faster with divergent loops despite worse VALU performance.
106 */
107 if (info->has_divergent_loop ||
108 /* Merged shader has to use same wave size for two shader stages. */
109 (prev_sel && prev_sel->info.has_divergent_loop))
110 return 32;
111
112 return 64;
113 }
114
si_shader_uses_bindless_samplers(struct si_shader_selector * selector)115 static bool si_shader_uses_bindless_samplers(struct si_shader_selector *selector)
116 {
117 return selector ? selector->info.uses_bindless_samplers : false;
118 }
119
si_shader_uses_bindless_images(struct si_shader_selector * selector)120 static bool si_shader_uses_bindless_images(struct si_shader_selector *selector)
121 {
122 return selector ? selector->info.uses_bindless_images : false;
123 }
124
125 /* SHADER_CACHE */
126
127 /**
128 * Return the IR key for the shader cache.
129 */
si_get_ir_cache_key(struct si_shader_selector * sel,bool ngg,bool es,unsigned wave_size,unsigned char ir_sha1_cache_key[20])130 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
131 unsigned wave_size, unsigned char ir_sha1_cache_key[20])
132 {
133 struct blob blob = {};
134 unsigned ir_size;
135 void *ir_binary;
136
137 if (sel->nir_binary) {
138 ir_binary = sel->nir_binary;
139 ir_size = sel->nir_size;
140 } else {
141 assert(sel->nir);
142
143 blob_init(&blob);
144 /* Keep debug info if NIR debug prints are in use. */
145 nir_serialize(&blob, sel->nir, NIR_DEBUG(PRINT) == 0);
146 ir_binary = blob.data;
147 ir_size = blob.size;
148 }
149
150 /* These settings affect the compilation, but they are not derived
151 * from the input shader IR.
152 */
153 unsigned shader_variant_flags = 0;
154
155 if (ngg)
156 shader_variant_flags |= 1 << 0;
157 /* bit gap */
158 if (wave_size == 32)
159 shader_variant_flags |= 1 << 2;
160 /* bit gap */
161 /* use_ngg_culling disables NGG passthrough for non-culling shaders to reduce context
162 * rolls, which can be changed with AMD_DEBUG=nonggc or AMD_DEBUG=nggc.
163 */
164 if (sel->screen->use_ngg_culling)
165 shader_variant_flags |= 1 << 4;
166 if (sel->screen->record_llvm_ir)
167 shader_variant_flags |= 1 << 5;
168 if (sel->screen->info.has_image_opcodes)
169 shader_variant_flags |= 1 << 6;
170 if (sel->screen->options.no_infinite_interp)
171 shader_variant_flags |= 1 << 7;
172 if (sel->screen->options.clamp_div_by_zero)
173 shader_variant_flags |= 1 << 8;
174 if ((sel->stage == MESA_SHADER_VERTEX ||
175 sel->stage == MESA_SHADER_TESS_EVAL ||
176 sel->stage == MESA_SHADER_GEOMETRY) &&
177 !es &&
178 sel->screen->options.vrs2x2)
179 shader_variant_flags |= 1 << 10;
180 if (sel->screen->options.inline_uniforms)
181 shader_variant_flags |= 1 << 11;
182 if (sel->screen->options.clear_lds)
183 shader_variant_flags |= 1 << 12;
184
185 struct mesa_sha1 ctx;
186 _mesa_sha1_init(&ctx);
187 _mesa_sha1_update(&ctx, &shader_variant_flags, 4);
188 _mesa_sha1_update(&ctx, ir_binary, ir_size);
189 _mesa_sha1_final(&ctx, ir_sha1_cache_key);
190
191 if (ir_binary == blob.data)
192 blob_finish(&blob);
193 }
194
195 /** Copy "data" to "ptr" and return the next dword following copied data. */
write_data(uint32_t * ptr,const void * data,unsigned size)196 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
197 {
198 /* data may be NULL if size == 0 */
199 if (size)
200 memcpy(ptr, data, size);
201 ptr += DIV_ROUND_UP(size, 4);
202 return ptr;
203 }
204
205 /** Read data from "ptr". Return the next dword following the data. */
read_data(uint32_t * ptr,void * data,unsigned size)206 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
207 {
208 memcpy(data, ptr, size);
209 ptr += DIV_ROUND_UP(size, 4);
210 return ptr;
211 }
212
213 /**
214 * Write the size as uint followed by the data. Return the next dword
215 * following the copied data.
216 */
write_chunk(uint32_t * ptr,const void * data,unsigned size)217 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
218 {
219 *ptr++ = size;
220 return write_data(ptr, data, size);
221 }
222
223 /**
224 * Read the size as uint followed by the data. Return both via parameters.
225 * Return the next dword following the data.
226 */
read_chunk(uint32_t * ptr,void ** data,unsigned * size)227 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
228 {
229 *size = *ptr++;
230 assert(*data == NULL);
231 if (!*size)
232 return ptr;
233 *data = malloc(*size);
234 return read_data(ptr, *data, *size);
235 }
236
237 struct si_shader_blob_head {
238 uint32_t size;
239 uint32_t type;
240 uint32_t crc32;
241 };
242
243 /**
244 * Return the shader binary in a buffer.
245 */
si_get_shader_binary(struct si_shader * shader)246 static uint32_t *si_get_shader_binary(struct si_shader *shader)
247 {
248 /* There is always a size of data followed by the data itself. */
249 unsigned llvm_ir_size =
250 shader->binary.llvm_ir_string ? strlen(shader->binary.llvm_ir_string) + 1 : 0;
251
252 /* Refuse to allocate overly large buffers and guard against integer
253 * overflow. */
254 if (shader->binary.code_size > UINT_MAX / 4 || llvm_ir_size > UINT_MAX / 4 ||
255 shader->binary.num_symbols > UINT_MAX / 32)
256 return NULL;
257
258 unsigned size = sizeof(struct si_shader_blob_head) +
259 align(sizeof(shader->config), 4) +
260 align(sizeof(shader->info), 4) +
261 4 + 4 + align(shader->binary.code_size, 4) +
262 4 + shader->binary.num_symbols * 8 +
263 4 + align(llvm_ir_size, 4) +
264 4 + align(shader->binary.disasm_size, 4);
265 uint32_t *buffer = (uint32_t*)CALLOC(1, size);
266 if (!buffer)
267 return NULL;
268
269 struct si_shader_blob_head *head = (struct si_shader_blob_head *)buffer;
270 head->type = shader->binary.type;
271 head->size = size;
272
273 uint32_t *data = buffer + sizeof(*head) / 4;
274 uint32_t *ptr = data;
275
276 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
277 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
278 ptr = write_data(ptr, &shader->binary.exec_size, 4);
279 ptr = write_chunk(ptr, shader->binary.code_buffer, shader->binary.code_size);
280 ptr = write_chunk(ptr, shader->binary.symbols, shader->binary.num_symbols * 8);
281 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
282 ptr = write_chunk(ptr, shader->binary.disasm_string, shader->binary.disasm_size);
283 assert((char *)ptr - (char *)buffer == (ptrdiff_t)size);
284
285 /* Compute CRC32. */
286 head->crc32 = util_hash_crc32(data, size - sizeof(*head));
287
288 return buffer;
289 }
290
si_load_shader_binary(struct si_shader * shader,void * binary)291 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
292 {
293 struct si_shader_blob_head *head = (struct si_shader_blob_head *)binary;
294 unsigned chunk_size;
295 unsigned code_size;
296
297 uint32_t *ptr = (uint32_t *)binary + sizeof(*head) / 4;
298 if (util_hash_crc32(ptr, head->size - sizeof(*head)) != head->crc32) {
299 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
300 return false;
301 }
302
303 shader->binary.type = (enum si_shader_binary_type)head->type;
304 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
305 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
306 ptr = read_data(ptr, &shader->binary.exec_size, 4);
307 ptr = read_chunk(ptr, (void **)&shader->binary.code_buffer, &code_size);
308 shader->binary.code_size = code_size;
309 ptr = read_chunk(ptr, (void **)&shader->binary.symbols, &chunk_size);
310 shader->binary.num_symbols = chunk_size / 8;
311 ptr = read_chunk(ptr, (void **)&shader->binary.llvm_ir_string, &chunk_size);
312 ptr = read_chunk(ptr, (void **)&shader->binary.disasm_string, &chunk_size);
313 shader->binary.disasm_size = chunk_size;
314
315 if (!shader->is_gs_copy_shader &&
316 shader->selector->stage == MESA_SHADER_GEOMETRY && !shader->key.ge.as_ngg) {
317 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
318 if (!shader->gs_copy_shader)
319 return false;
320
321 shader->gs_copy_shader->is_gs_copy_shader = true;
322
323 if (!si_load_shader_binary(shader->gs_copy_shader, (uint8_t*)binary + head->size)) {
324 FREE(shader->gs_copy_shader);
325 shader->gs_copy_shader = NULL;
326 return false;
327 }
328
329 util_queue_fence_init(&shader->gs_copy_shader->ready);
330 shader->gs_copy_shader->selector = shader->selector;
331 shader->gs_copy_shader->is_gs_copy_shader = true;
332 shader->gs_copy_shader->wave_size =
333 si_determine_wave_size(shader->selector->screen, shader->gs_copy_shader);
334
335 si_shader_binary_upload(shader->selector->screen, shader->gs_copy_shader, 0);
336 }
337
338 return true;
339 }
340
341 /**
342 * Insert a shader into the cache. It's assumed the shader is not in the cache.
343 * Use si_shader_cache_load_shader before calling this.
344 */
si_shader_cache_insert_shader(struct si_screen * sscreen,unsigned char ir_sha1_cache_key[20],struct si_shader * shader,bool insert_into_disk_cache)345 void si_shader_cache_insert_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
346 struct si_shader *shader, bool insert_into_disk_cache)
347 {
348 uint32_t *hw_binary;
349 struct hash_entry *entry;
350 uint8_t key[CACHE_KEY_SIZE];
351 bool memory_cache_full = sscreen->shader_cache_size >= sscreen->shader_cache_max_size;
352
353 if (!insert_into_disk_cache && memory_cache_full)
354 return;
355
356 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
357 if (entry)
358 return; /* already added */
359
360 hw_binary = si_get_shader_binary(shader);
361 if (!hw_binary)
362 return;
363
364 unsigned size = *hw_binary;
365
366 if (shader->selector->stage == MESA_SHADER_GEOMETRY && !shader->key.ge.as_ngg) {
367 uint32_t *gs_copy_binary = si_get_shader_binary(shader->gs_copy_shader);
368 if (!gs_copy_binary) {
369 FREE(hw_binary);
370 return;
371 }
372
373 /* Combine both binaries. */
374 size += *gs_copy_binary;
375 uint32_t *combined_binary = (uint32_t*)MALLOC(size);
376 if (!combined_binary) {
377 FREE(hw_binary);
378 FREE(gs_copy_binary);
379 return;
380 }
381
382 memcpy(combined_binary, hw_binary, *hw_binary);
383 memcpy(combined_binary + *hw_binary / 4, gs_copy_binary, *gs_copy_binary);
384 FREE(hw_binary);
385 FREE(gs_copy_binary);
386 hw_binary = combined_binary;
387 }
388
389 if (!memory_cache_full) {
390 if (_mesa_hash_table_insert(sscreen->shader_cache,
391 mem_dup(ir_sha1_cache_key, 20),
392 hw_binary) == NULL) {
393 FREE(hw_binary);
394 return;
395 }
396
397 sscreen->shader_cache_size += size;
398 }
399
400 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
401 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key, 20, key);
402 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary, size, NULL);
403 }
404
405 if (memory_cache_full)
406 FREE(hw_binary);
407 }
408
si_shader_cache_load_shader(struct si_screen * sscreen,unsigned char ir_sha1_cache_key[20],struct si_shader * shader)409 bool si_shader_cache_load_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
410 struct si_shader *shader)
411 {
412 struct hash_entry *entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
413
414 if (entry) {
415 if (si_load_shader_binary(shader, entry->data)) {
416 p_atomic_inc(&sscreen->num_memory_shader_cache_hits);
417 return true;
418 }
419 }
420 p_atomic_inc(&sscreen->num_memory_shader_cache_misses);
421
422 if (!sscreen->disk_shader_cache)
423 return false;
424
425 unsigned char sha1[CACHE_KEY_SIZE];
426 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key, 20, sha1);
427
428 size_t total_size;
429 uint32_t *buffer = (uint32_t*)disk_cache_get(sscreen->disk_shader_cache, sha1, &total_size);
430 if (buffer) {
431 unsigned size = *buffer;
432 unsigned gs_copy_binary_size = 0;
433
434 /* The GS copy shader binary is after the GS binary. */
435 if (shader->selector->stage == MESA_SHADER_GEOMETRY && !shader->key.ge.as_ngg)
436 gs_copy_binary_size = buffer[size / 4];
437
438 if (total_size >= sizeof(uint32_t) && size + gs_copy_binary_size == total_size) {
439 if (si_load_shader_binary(shader, buffer)) {
440 free(buffer);
441 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, false);
442 p_atomic_inc(&sscreen->num_disk_shader_cache_hits);
443 return true;
444 }
445 } else {
446 /* Something has gone wrong discard the item from the cache and
447 * rebuild/link from source.
448 */
449 assert(!"Invalid radeonsi shader disk cache item!");
450 disk_cache_remove(sscreen->disk_shader_cache, sha1);
451 }
452 }
453
454 free(buffer);
455 p_atomic_inc(&sscreen->num_disk_shader_cache_misses);
456 return false;
457 }
458
si_shader_cache_key_hash(const void * key)459 static uint32_t si_shader_cache_key_hash(const void *key)
460 {
461 /* Take the first dword of SHA1. */
462 return *(uint32_t *)key;
463 }
464
si_shader_cache_key_equals(const void * a,const void * b)465 static bool si_shader_cache_key_equals(const void *a, const void *b)
466 {
467 /* Compare SHA1s. */
468 return memcmp(a, b, 20) == 0;
469 }
470
si_destroy_shader_cache_entry(struct hash_entry * entry)471 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
472 {
473 FREE((void *)entry->key);
474 FREE(entry->data);
475 }
476
si_init_shader_cache(struct si_screen * sscreen)477 bool si_init_shader_cache(struct si_screen *sscreen)
478 {
479 (void)simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
480 sscreen->shader_cache =
481 _mesa_hash_table_create(NULL, si_shader_cache_key_hash, si_shader_cache_key_equals);
482 sscreen->shader_cache_size = 0;
483 /* Maximum size: 64MB on 32 bits, 1GB else */
484 sscreen->shader_cache_max_size = ((sizeof(void *) == 4) ? 64 : 1024) * 1024 * 1024;
485
486 return sscreen->shader_cache != NULL;
487 }
488
si_destroy_shader_cache(struct si_screen * sscreen)489 void si_destroy_shader_cache(struct si_screen *sscreen)
490 {
491 if (sscreen->shader_cache)
492 _mesa_hash_table_destroy(sscreen->shader_cache, si_destroy_shader_cache_entry);
493 simple_mtx_destroy(&sscreen->shader_cache_mutex);
494 }
495
496 /* SHADER STATES */
497
si_shader_encode_vgprs(struct si_shader * shader)498 unsigned si_shader_encode_vgprs(struct si_shader *shader)
499 {
500 assert(shader->selector->screen->info.gfx_level >= GFX10 || shader->wave_size == 64);
501 return shader->config.num_vgprs / (shader->wave_size == 32 ? 8 : 4) - 1;
502 }
503
si_shader_encode_sgprs(struct si_shader * shader)504 unsigned si_shader_encode_sgprs(struct si_shader *shader)
505 {
506 if (shader->selector->screen->info.gfx_level >= GFX10)
507 return 0; /* Gfx10+ don't have the SGPRS field and always allocate 128 SGPRs. */
508
509 return shader->config.num_sgprs / 8 - 1;
510 }
511
si_shader_mem_ordered(struct si_shader * shader)512 bool si_shader_mem_ordered(struct si_shader *shader)
513 {
514 struct si_screen *sscreen = shader->selector->screen;
515
516 if (sscreen->info.gfx_level < GFX10 || sscreen->info.gfx_level >= GFX12)
517 return false;
518
519 /* Return true if both types of VMEM that return something are used. */
520 return shader->info.uses_vmem_sampler_or_bvh &&
521 (shader->info.uses_vmem_load_other ||
522 shader->config.scratch_bytes_per_wave);
523 }
524
si_set_tesseval_regs(struct si_screen * sscreen,const struct si_shader_selector * tes,struct si_shader * shader)525 static void si_set_tesseval_regs(struct si_screen *sscreen, const struct si_shader_selector *tes,
526 struct si_shader *shader)
527 {
528 const struct si_shader_info *info = &tes->info;
529 enum tess_primitive_mode tes_prim_mode = info->base.tess._primitive_mode;
530 unsigned tes_spacing = info->base.tess.spacing;
531 bool tes_vertex_order_cw = !info->base.tess.ccw;
532 bool tes_point_mode = info->base.tess.point_mode;
533 unsigned type, partitioning, topology, distribution_mode;
534
535 switch (tes_prim_mode) {
536 case TESS_PRIMITIVE_ISOLINES:
537 type = V_028B6C_TESS_ISOLINE;
538 break;
539 case TESS_PRIMITIVE_TRIANGLES:
540 type = V_028B6C_TESS_TRIANGLE;
541 break;
542 case TESS_PRIMITIVE_QUADS:
543 type = V_028B6C_TESS_QUAD;
544 break;
545 default:
546 assert(0);
547 return;
548 }
549
550 switch (tes_spacing) {
551 case TESS_SPACING_FRACTIONAL_ODD:
552 partitioning = V_028B6C_PART_FRAC_ODD;
553 break;
554 case TESS_SPACING_FRACTIONAL_EVEN:
555 partitioning = V_028B6C_PART_FRAC_EVEN;
556 break;
557 case TESS_SPACING_EQUAL:
558 partitioning = V_028B6C_PART_INTEGER;
559 break;
560 default:
561 assert(0);
562 return;
563 }
564
565 if (tes_point_mode)
566 topology = V_028B6C_OUTPUT_POINT;
567 else if (tes_prim_mode == TESS_PRIMITIVE_ISOLINES)
568 topology = V_028B6C_OUTPUT_LINE;
569 else if (tes_vertex_order_cw)
570 /* for some reason, this must be the other way around */
571 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
572 else
573 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
574
575 if (sscreen->info.has_distributed_tess) {
576 if (sscreen->info.family == CHIP_FIJI || sscreen->info.family >= CHIP_POLARIS10)
577 distribution_mode = V_028B6C_TRAPEZOIDS;
578 else
579 distribution_mode = V_028B6C_DONUTS;
580 } else
581 distribution_mode = V_028B6C_NO_DIST;
582
583 shader->vgt_tf_param = S_028B6C_TYPE(type) | S_028B6C_PARTITIONING(partitioning) |
584 S_028B6C_TOPOLOGY(topology) |
585 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
586
587 if (sscreen->info.gfx_level >= GFX12)
588 shader->vgt_tf_param |= S_028AA4_TEMPORAL(gfx12_load_last_use_discard);
589 }
590
591 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
592 * whether the "fractional odd" tessellation spacing is used.
593 *
594 * Possible VGT configurations and which state should set the register:
595 *
596 * Reg set in | VGT shader configuration | Value
597 * ------------------------------------------------------
598 * VS as VS | VS | 30
599 * VS as ES | ES -> GS -> VS | 30
600 * TES as VS | LS -> HS -> VS | 14 or 30
601 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
602 */
polaris_set_vgt_vertex_reuse(struct si_screen * sscreen,struct si_shader_selector * sel,struct si_shader * shader)603 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen, struct si_shader_selector *sel,
604 struct si_shader *shader)
605 {
606 if (sscreen->info.family < CHIP_POLARIS10 || sscreen->info.gfx_level >= GFX10)
607 return;
608
609 /* VS as VS, or VS as ES: */
610 if ((sel->stage == MESA_SHADER_VERTEX &&
611 (!shader->key.ge.as_ls && !shader->is_gs_copy_shader)) ||
612 /* TES as VS, or TES as ES: */
613 sel->stage == MESA_SHADER_TESS_EVAL) {
614 unsigned vtx_reuse_depth = 30;
615
616 if (sel->stage == MESA_SHADER_TESS_EVAL &&
617 sel->info.base.tess.spacing == TESS_SPACING_FRACTIONAL_ODD)
618 vtx_reuse_depth = 14;
619
620 shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
621 }
622 }
623
624 static struct si_pm4_state *
si_get_shader_pm4_state(struct si_shader * shader,void (* emit_func)(struct si_context * ctx,unsigned index))625 si_get_shader_pm4_state(struct si_shader *shader,
626 void (*emit_func)(struct si_context *ctx, unsigned index))
627 {
628 si_pm4_clear_state(&shader->pm4, shader->selector->screen, false);
629 shader->pm4.atom.emit = emit_func;
630 return &shader->pm4;
631 }
632
si_get_num_vs_user_sgprs(struct si_shader * shader,unsigned num_always_on_user_sgprs)633 static unsigned si_get_num_vs_user_sgprs(struct si_shader *shader,
634 unsigned num_always_on_user_sgprs)
635 {
636 struct si_shader_selector *vs =
637 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
638 unsigned num_vbos_in_user_sgprs = vs->info.num_vbos_in_user_sgprs;
639
640 /* 1 SGPR is reserved for the vertex buffer pointer. */
641 assert(num_always_on_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST - 1);
642
643 if (num_vbos_in_user_sgprs)
644 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST + num_vbos_in_user_sgprs * 4;
645
646 /* Add the pointer to VBO descriptors. */
647 return num_always_on_user_sgprs + 1;
648 }
649
650 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
si_get_vs_vgpr_comp_cnt(struct si_screen * sscreen,struct si_shader * shader,bool legacy_vs_prim_id)651 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen, struct si_shader *shader,
652 bool legacy_vs_prim_id)
653 {
654 assert(shader->selector->stage == MESA_SHADER_VERTEX ||
655 (shader->previous_stage_sel && shader->previous_stage_sel->stage == MESA_SHADER_VERTEX));
656
657 /* GFX6-9 LS (VertexID, RelAutoIndex, InstanceID / StepRate0, InstanceID)
658 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0, VSPrimID, InstanceID)
659 * GFX10-11 LS (VertexID, RelAutoIndex, UserVGPR1, UserVGPR2 or InstanceID)
660 * GFX10-11 ES,VS (VertexID, UserVGPR1, UserVGPR2 or VSPrimID, UserVGPR3 or InstanceID)
661 * GFX12 LS,ES (VertexID, InstanceID)
662 */
663 bool is_ls = shader->selector->stage == MESA_SHADER_TESS_CTRL || shader->key.ge.as_ls;
664 unsigned max = 0;
665
666 if (shader->info.uses_instanceid) {
667 if (sscreen->info.gfx_level >= GFX12)
668 max = MAX2(max, 1);
669 else if (sscreen->info.gfx_level >= GFX10)
670 max = MAX2(max, 3);
671 else if (is_ls)
672 max = MAX2(max, 2); /* use (InstanceID / StepRate0) because StepRate0 == 1 */
673 else
674 max = MAX2(max, 1); /* use (InstanceID / StepRate0) because StepRate0 == 1 */
675 }
676
677 if (legacy_vs_prim_id)
678 max = MAX2(max, 2); /* VSPrimID */
679
680 /* GFX11: We prefer to compute RelAutoIndex using (WaveID * WaveSize + ThreadID).
681 * Older chips didn't have WaveID in LS.
682 * GFX12 doesn't have RelAutoIndex.
683 */
684 if (is_ls && sscreen->info.gfx_level <= GFX10_3)
685 max = MAX2(max, 1); /* RelAutoIndex */
686
687 return max;
688 }
689
si_shader_ls(struct si_screen * sscreen,struct si_shader * shader)690 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
691 {
692 struct si_pm4_state *pm4;
693 uint64_t va;
694
695 assert(sscreen->info.gfx_level <= GFX8);
696
697 pm4 = si_get_shader_pm4_state(shader, NULL);
698 if (!pm4)
699 return;
700
701 va = shader->bo->gpu_address;
702 ac_pm4_set_reg(&pm4->base, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
703
704 shader->config.rsrc1 = S_00B528_VGPRS(si_shader_encode_vgprs(shader)) |
705 S_00B528_SGPRS(si_shader_encode_sgprs(shader)) |
706 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
707 S_00B528_DX10_CLAMP(1) |
708 S_00B528_FLOAT_MODE(shader->config.float_mode);
709 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR)) |
710 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
711 ac_pm4_finalize(&pm4->base);
712 }
713
si_shader_hs(struct si_screen * sscreen,struct si_shader * shader)714 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
715 {
716 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader, NULL);
717 if (!pm4)
718 return;
719
720 uint64_t va = shader->bo->gpu_address;
721 unsigned num_user_sgprs = sscreen->info.gfx_level >= GFX9 ?
722 si_get_num_vs_user_sgprs(shader, GFX9_TCS_NUM_USER_SGPR) :
723 GFX6_TCS_NUM_USER_SGPR;
724
725 if (sscreen->info.gfx_level >= GFX12) {
726 ac_pm4_set_reg(&pm4->base, R_00B420_SPI_SHADER_PGM_RSRC4_HS,
727 S_00B420_WAVE_LIMIT(0x3ff) |
728 S_00B420_GLG_FORCE_DISABLE(1) |
729 S_00B420_INST_PREF_SIZE(si_get_shader_prefetch_size(shader)));
730
731 ac_pm4_set_reg(&pm4->base, R_00B424_SPI_SHADER_PGM_LO_LS, va >> 8);
732 } else if (sscreen->info.gfx_level >= GFX11) {
733 ac_pm4_set_reg_idx3(&pm4->base, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
734 ac_apply_cu_en(S_00B404_INST_PREF_SIZE(si_get_shader_prefetch_size(shader)) |
735 S_00B404_CU_EN(0xffff),
736 C_00B404_CU_EN, 16, &sscreen->info));
737
738 ac_pm4_set_reg(&pm4->base, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
739 } else if (sscreen->info.gfx_level >= GFX10) {
740 ac_pm4_set_reg(&pm4->base, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
741 } else if (sscreen->info.gfx_level >= GFX9) {
742 ac_pm4_set_reg(&pm4->base, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
743 } else {
744 ac_pm4_set_reg(&pm4->base, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
745 ac_pm4_set_reg(&pm4->base, R_00B424_SPI_SHADER_PGM_HI_HS,
746 S_00B424_MEM_BASE(sscreen->info.address32_hi >> 8));
747 }
748
749 ac_pm4_set_reg(&pm4->base, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
750 S_00B428_VGPRS(si_shader_encode_vgprs(shader)) |
751 S_00B428_SGPRS(si_shader_encode_sgprs(shader)) |
752 S_00B428_DX10_CLAMP(sscreen->info.gfx_level < GFX12) |
753 S_00B428_MEM_ORDERED(si_shader_mem_ordered(shader)) |
754 S_00B428_FLOAT_MODE(shader->config.float_mode) |
755 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.gfx_level >= GFX9 ?
756 si_get_vs_vgpr_comp_cnt(sscreen, shader, false) : 0));
757
758 shader->config.rsrc2 = S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
759 S_00B42C_USER_SGPR(num_user_sgprs);
760
761 if (sscreen->info.gfx_level >= GFX10)
762 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
763 else if (sscreen->info.gfx_level >= GFX9)
764 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
765 else
766 shader->config.rsrc2 |= S_00B42C_OC_LDS_EN(1);
767
768 if (sscreen->info.gfx_level <= GFX8)
769 ac_pm4_set_reg(&pm4->base, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, shader->config.rsrc2);
770
771 ac_pm4_finalize(&pm4->base);
772 }
773
si_emit_shader_es(struct si_context * sctx,unsigned index)774 static void si_emit_shader_es(struct si_context *sctx, unsigned index)
775 {
776 struct si_shader *shader = sctx->queued.named.es;
777
778 radeon_begin(&sctx->gfx_cs);
779 radeon_opt_set_context_reg(R_028AAC_VGT_ESGS_RING_ITEMSIZE,
780 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
781 shader->selector->info.esgs_vertex_stride / 4);
782
783 if (shader->selector->stage == MESA_SHADER_TESS_EVAL)
784 radeon_opt_set_context_reg(R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
785 shader->vgt_tf_param);
786
787 if (shader->vgt_vertex_reuse_block_cntl)
788 radeon_opt_set_context_reg(R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
789 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
790 shader->vgt_vertex_reuse_block_cntl);
791 radeon_end_update_context_roll();
792 }
793
si_shader_es(struct si_screen * sscreen,struct si_shader * shader)794 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
795 {
796 struct si_pm4_state *pm4;
797 unsigned num_user_sgprs;
798 unsigned vgpr_comp_cnt;
799 uint64_t va;
800 unsigned oc_lds_en;
801
802 assert(sscreen->info.gfx_level <= GFX8);
803
804 pm4 = si_get_shader_pm4_state(shader, si_emit_shader_es);
805 if (!pm4)
806 return;
807
808 va = shader->bo->gpu_address;
809
810 if (shader->selector->stage == MESA_SHADER_VERTEX) {
811 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
812 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
813 } else if (shader->selector->stage == MESA_SHADER_TESS_EVAL) {
814 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
815 num_user_sgprs = SI_TES_NUM_USER_SGPR;
816 } else
817 unreachable("invalid shader selector type");
818
819 oc_lds_en = shader->selector->stage == MESA_SHADER_TESS_EVAL ? 1 : 0;
820
821 ac_pm4_set_reg(&pm4->base, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
822 ac_pm4_set_reg(&pm4->base, R_00B324_SPI_SHADER_PGM_HI_ES,
823 S_00B324_MEM_BASE(sscreen->info.address32_hi >> 8));
824 ac_pm4_set_reg(&pm4->base, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
825 S_00B328_VGPRS(si_shader_encode_vgprs(shader)) |
826 S_00B328_SGPRS(si_shader_encode_sgprs(shader)) |
827 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
828 S_00B328_DX10_CLAMP(1) |
829 S_00B328_FLOAT_MODE(shader->config.float_mode));
830 ac_pm4_set_reg(&pm4->base, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
831 S_00B32C_USER_SGPR(num_user_sgprs) | S_00B32C_OC_LDS_EN(oc_lds_en) |
832 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
833
834 if (shader->selector->stage == MESA_SHADER_TESS_EVAL)
835 si_set_tesseval_regs(sscreen, shader->selector, shader);
836
837 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader);
838 ac_pm4_finalize(&pm4->base);
839 }
840
gfx9_get_gs_info(struct si_shader_selector * es,struct si_shader_selector * gs,struct gfx9_gs_info * out)841 void gfx9_get_gs_info(struct si_shader_selector *es, struct si_shader_selector *gs,
842 struct gfx9_gs_info *out)
843 {
844 unsigned gs_num_invocations = MAX2(gs->info.base.gs.invocations, 1);
845 unsigned input_prim = gs->info.base.gs.input_primitive;
846 bool uses_adjacency = mesa_prim_has_adjacency((enum mesa_prim)input_prim);
847
848 /* All these are in dwords: */
849 /* We can't allow using the whole LDS, because GS waves compete with
850 * other shader stages for LDS space. */
851 const unsigned max_lds_size = 8 * 1024;
852 const unsigned esgs_itemsize = es->info.esgs_vertex_stride / 4;
853 unsigned esgs_lds_size;
854
855 /* All these are per subgroup: */
856 const unsigned max_out_prims = 32 * 1024;
857 const unsigned max_es_verts = 255;
858 const unsigned ideal_gs_prims = 64;
859 unsigned max_gs_prims, gs_prims;
860 unsigned min_es_verts, es_verts, worst_case_es_verts;
861
862 if (uses_adjacency || gs_num_invocations > 1)
863 max_gs_prims = 127 / gs_num_invocations;
864 else
865 max_gs_prims = 255;
866
867 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
868 * Make sure we don't go over the maximum value.
869 */
870 if (gs->info.base.gs.vertices_out > 0) {
871 max_gs_prims =
872 MIN2(max_gs_prims, max_out_prims / (gs->info.base.gs.vertices_out * gs_num_invocations));
873 }
874 assert(max_gs_prims > 0);
875
876 /* If the primitive has adjacency, halve the number of vertices
877 * that will be reused in multiple primitives.
878 */
879 min_es_verts = gs->info.gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
880
881 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
882 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
883
884 /* Compute ESGS LDS size based on the worst case number of ES vertices
885 * needed to create the target number of GS prims per subgroup.
886 */
887 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
888
889 /* If total LDS usage is too big, refactor partitions based on ratio
890 * of ESGS item sizes.
891 */
892 if (esgs_lds_size > max_lds_size) {
893 /* Our target GS Prims Per Subgroup was too large. Calculate
894 * the maximum number of GS Prims Per Subgroup that will fit
895 * into LDS, capped by the maximum that the hardware can support.
896 */
897 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)), max_gs_prims);
898 assert(gs_prims > 0);
899 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
900
901 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
902 assert(esgs_lds_size <= max_lds_size);
903 }
904
905 /* Now calculate remaining ESGS information. */
906 if (esgs_lds_size)
907 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
908 else
909 es_verts = max_es_verts;
910
911 /* Vertices for adjacency primitives are not always reused, so restore
912 * it for ES_VERTS_PER_SUBGRP.
913 */
914 min_es_verts = gs->info.gs_input_verts_per_prim;
915
916 /* For normal primitives, the VGT only checks if they are past the ES
917 * verts per subgroup after allocating a full GS primitive and if they
918 * are, kick off a new subgroup. But if those additional ES verts are
919 * unique (e.g. not reused) we need to make sure there is enough LDS
920 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
921 */
922 es_verts -= min_es_verts - 1;
923
924 out->es_verts_per_subgroup = es_verts;
925 out->gs_prims_per_subgroup = gs_prims;
926 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
927 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup * gs->info.base.gs.vertices_out;
928 out->esgs_ring_size = esgs_lds_size;
929
930 assert(out->max_prims_per_subgroup <= max_out_prims);
931 }
932
gfx9_set_gs_sgpr_num_es_outputs(struct si_context * sctx,unsigned esgs_vertex_stride)933 static void gfx9_set_gs_sgpr_num_es_outputs(struct si_context *sctx, unsigned esgs_vertex_stride)
934 {
935 /* The stride must always be odd (e.g. a multiple of 4 + 1) to reduce LDS bank conflicts. */
936 assert(!esgs_vertex_stride || esgs_vertex_stride % 4 == 1);
937 unsigned num_es_outputs = esgs_vertex_stride / 4;
938
939 /* If there are no ES outputs, GS doesn't use this SGPR field, so only set it if the number
940 * is non-zero.
941 */
942 if (num_es_outputs)
943 SET_FIELD(sctx->current_gs_state, GS_STATE_NUM_ES_OUTPUTS, num_es_outputs);
944 }
945
si_emit_shader_gs(struct si_context * sctx,unsigned index)946 static void si_emit_shader_gs(struct si_context *sctx, unsigned index)
947 {
948 struct si_shader *shader = sctx->queued.named.gs;
949
950 if (sctx->gfx_level >= GFX9)
951 gfx9_set_gs_sgpr_num_es_outputs(sctx, shader->key.ge.part.gs.es->info.esgs_vertex_stride / 4);
952
953 radeon_begin(&sctx->gfx_cs);
954
955 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
956 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
957 radeon_opt_set_context_reg3(
958 R_028A60_VGT_GSVS_RING_OFFSET_1, SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
959 shader->gs.vgt_gsvs_ring_offset_1, shader->gs.vgt_gsvs_ring_offset_2,
960 shader->gs.vgt_gsvs_ring_offset_3);
961
962 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
963 radeon_opt_set_context_reg(R_028AB0_VGT_GSVS_RING_ITEMSIZE,
964 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
965 shader->gs.vgt_gsvs_ring_itemsize);
966
967 /* R_028B38_VGT_GS_MAX_VERT_OUT */
968 radeon_opt_set_context_reg(R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
969 shader->gs.vgt_gs_max_vert_out);
970
971 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
972 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
973 radeon_opt_set_context_reg4(
974 R_028B5C_VGT_GS_VERT_ITEMSIZE, SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
975 shader->gs.vgt_gs_vert_itemsize, shader->gs.vgt_gs_vert_itemsize_1,
976 shader->gs.vgt_gs_vert_itemsize_2, shader->gs.vgt_gs_vert_itemsize_3);
977
978 /* R_028B90_VGT_GS_INSTANCE_CNT */
979 radeon_opt_set_context_reg(R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
980 shader->gs.vgt_gs_instance_cnt);
981
982 if (sctx->gfx_level >= GFX9) {
983 /* R_028A44_VGT_GS_ONCHIP_CNTL */
984 radeon_opt_set_context_reg(R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
985 shader->gs.vgt_gs_onchip_cntl);
986 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
987 if (sctx->gfx_level == GFX9) {
988 radeon_opt_set_context_reg(R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
989 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
990 shader->gs.vgt_gs_max_prims_per_subgroup);
991 }
992
993 if (shader->key.ge.part.gs.es->stage == MESA_SHADER_TESS_EVAL)
994 radeon_opt_set_context_reg(R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
995 shader->vgt_tf_param);
996 if (shader->vgt_vertex_reuse_block_cntl)
997 radeon_opt_set_context_reg(R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
998 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
999 shader->vgt_vertex_reuse_block_cntl);
1000 }
1001 radeon_end_update_context_roll();
1002
1003 /* These don't cause any context rolls. */
1004 radeon_begin_again(&sctx->gfx_cs);
1005 if (sctx->gfx_level >= GFX7) {
1006 if (sctx->screen->info.uses_kernel_cu_mask) {
1007 radeon_opt_set_sh_reg_idx(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
1008 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
1009 3, shader->gs.spi_shader_pgm_rsrc3_gs);
1010 } else {
1011 radeon_opt_set_sh_reg(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
1012 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
1013 shader->gs.spi_shader_pgm_rsrc3_gs);
1014 }
1015 }
1016 if (sctx->gfx_level >= GFX10) {
1017 if (sctx->screen->info.uses_kernel_cu_mask) {
1018 radeon_opt_set_sh_reg_idx(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1019 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
1020 3, shader->gs.spi_shader_pgm_rsrc4_gs);
1021 } else {
1022 radeon_opt_set_sh_reg(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1023 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
1024 shader->gs.spi_shader_pgm_rsrc4_gs);
1025 }
1026 }
1027 radeon_end();
1028 }
1029
si_shader_gs(struct si_screen * sscreen,struct si_shader * shader)1030 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
1031 {
1032 struct si_shader_selector *sel = shader->selector;
1033 const uint8_t *num_components = sel->info.num_stream_output_components;
1034 unsigned gs_num_invocations = sel->info.base.gs.invocations;
1035 struct si_pm4_state *pm4;
1036 uint64_t va;
1037 unsigned max_stream = util_last_bit(sel->info.base.gs.active_stream_mask);
1038 unsigned offset;
1039
1040 assert(sscreen->info.gfx_level < GFX11); /* gfx11 doesn't have the legacy pipeline */
1041
1042 pm4 = si_get_shader_pm4_state(shader, si_emit_shader_gs);
1043 if (!pm4)
1044 return;
1045
1046 offset = num_components[0] * sel->info.base.gs.vertices_out;
1047 shader->gs.vgt_gsvs_ring_offset_1 = offset;
1048
1049 if (max_stream >= 2)
1050 offset += num_components[1] * sel->info.base.gs.vertices_out;
1051 shader->gs.vgt_gsvs_ring_offset_2 = offset;
1052
1053 if (max_stream >= 3)
1054 offset += num_components[2] * sel->info.base.gs.vertices_out;
1055 shader->gs.vgt_gsvs_ring_offset_3 = offset;
1056
1057 if (max_stream >= 4)
1058 offset += num_components[3] * sel->info.base.gs.vertices_out;
1059 shader->gs.vgt_gsvs_ring_itemsize = offset;
1060
1061 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
1062 assert(offset < (1 << 15));
1063
1064 shader->gs.vgt_gs_max_vert_out = sel->info.base.gs.vertices_out;
1065
1066 shader->gs.vgt_gs_vert_itemsize = num_components[0];
1067 shader->gs.vgt_gs_vert_itemsize_1 = (max_stream >= 2) ? num_components[1] : 0;
1068 shader->gs.vgt_gs_vert_itemsize_2 = (max_stream >= 3) ? num_components[2] : 0;
1069 shader->gs.vgt_gs_vert_itemsize_3 = (max_stream >= 4) ? num_components[3] : 0;
1070
1071 shader->gs.vgt_gs_instance_cnt =
1072 S_028B90_CNT(MIN2(gs_num_invocations, 127)) | S_028B90_ENABLE(gs_num_invocations > 0);
1073
1074 /* Copy over fields from the GS copy shader to make them easily accessible from GS. */
1075 shader->pa_cl_vs_out_cntl = shader->gs_copy_shader->pa_cl_vs_out_cntl;
1076
1077 va = shader->bo->gpu_address;
1078
1079 if (sscreen->info.gfx_level >= GFX9) {
1080 unsigned input_prim = sel->info.base.gs.input_primitive;
1081 gl_shader_stage es_stage = shader->key.ge.part.gs.es->stage;
1082 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1083
1084 if (es_stage == MESA_SHADER_VERTEX) {
1085 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1086 } else if (es_stage == MESA_SHADER_TESS_EVAL)
1087 es_vgpr_comp_cnt = shader->key.ge.part.gs.es->info.uses_primid ? 3 : 2;
1088 else
1089 unreachable("invalid shader selector type");
1090
1091 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1092 * VGPR[0:4] are always loaded.
1093 */
1094 if (sel->info.uses_invocationid)
1095 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
1096 else if (sel->info.uses_primid)
1097 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1098 else if (input_prim >= MESA_PRIM_TRIANGLES)
1099 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1100 else
1101 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1102
1103 unsigned num_user_sgprs;
1104 if (es_stage == MESA_SHADER_VERTEX)
1105 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_GS_NUM_USER_SGPR);
1106 else
1107 num_user_sgprs = GFX9_GS_NUM_USER_SGPR;
1108
1109 if (sscreen->info.gfx_level >= GFX10) {
1110 ac_pm4_set_reg(&pm4->base, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1111 } else {
1112 ac_pm4_set_reg(&pm4->base, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
1113 }
1114
1115 uint32_t rsrc1 = S_00B228_VGPRS(si_shader_encode_vgprs(shader)) |
1116 S_00B228_SGPRS(si_shader_encode_sgprs(shader)) |
1117 S_00B228_DX10_CLAMP(1) |
1118 S_00B228_MEM_ORDERED(si_shader_mem_ordered(shader)) |
1119 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1120 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
1121 uint32_t rsrc2 = S_00B22C_USER_SGPR(num_user_sgprs) |
1122 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1123 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL) |
1124 S_00B22C_LDS_SIZE(shader->config.lds_size) |
1125 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1126
1127 if (sscreen->info.gfx_level >= GFX10) {
1128 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
1129 } else {
1130 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
1131 }
1132
1133 ac_pm4_set_reg(&pm4->base, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
1134 ac_pm4_set_reg(&pm4->base, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
1135
1136 shader->gs.spi_shader_pgm_rsrc3_gs =
1137 ac_apply_cu_en(S_00B21C_CU_EN(0xffff) |
1138 S_00B21C_WAVE_LIMIT(0x3F),
1139 C_00B21C_CU_EN, 0, &sscreen->info);
1140 shader->gs.spi_shader_pgm_rsrc4_gs =
1141 ac_apply_cu_en(S_00B204_CU_EN_GFX10(0xffff) |
1142 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0),
1143 C_00B204_CU_EN_GFX10, 16, &sscreen->info);
1144
1145 shader->gs.vgt_gs_onchip_cntl =
1146 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
1147 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
1148 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
1149 shader->gs.vgt_gs_max_prims_per_subgroup =
1150 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
1151 shader->gs.vgt_esgs_ring_itemsize = shader->key.ge.part.gs.es->info.esgs_vertex_stride / 4;
1152
1153 if (es_stage == MESA_SHADER_TESS_EVAL)
1154 si_set_tesseval_regs(sscreen, shader->key.ge.part.gs.es, shader);
1155
1156 polaris_set_vgt_vertex_reuse(sscreen, shader->key.ge.part.gs.es, shader);
1157 } else {
1158 shader->gs.spi_shader_pgm_rsrc3_gs =
1159 ac_apply_cu_en(S_00B21C_CU_EN(0xffff) |
1160 S_00B21C_WAVE_LIMIT(0x3F),
1161 C_00B21C_CU_EN, 0, &sscreen->info);
1162
1163 ac_pm4_set_reg(&pm4->base, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
1164 ac_pm4_set_reg(&pm4->base, R_00B224_SPI_SHADER_PGM_HI_GS,
1165 S_00B224_MEM_BASE(sscreen->info.address32_hi >> 8));
1166
1167 ac_pm4_set_reg(&pm4->base, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1168 S_00B228_VGPRS(si_shader_encode_vgprs(shader)) |
1169 S_00B228_SGPRS(si_shader_encode_sgprs(shader)) |
1170 S_00B228_DX10_CLAMP(1) |
1171 S_00B228_FLOAT_MODE(shader->config.float_mode));
1172 ac_pm4_set_reg(&pm4->base, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1173 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
1174 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1175 }
1176 ac_pm4_finalize(&pm4->base);
1177 }
1178
gfx10_is_ngg_passthrough(struct si_shader * shader)1179 bool gfx10_is_ngg_passthrough(struct si_shader *shader)
1180 {
1181 struct si_shader_selector *sel = shader->selector;
1182
1183 /* Never use NGG passthrough if culling is possible even when it's not used by this shader,
1184 * so that we don't get context rolls when enabling and disabling NGG passthrough.
1185 */
1186 if (sel->screen->use_ngg_culling)
1187 return false;
1188
1189 /* The definition of NGG passthrough is:
1190 * - user GS is turned off (no amplification, no GS instancing, and no culling)
1191 * - VGT_ESGS_RING_ITEMSIZE is ignored (behaving as if it was equal to 1)
1192 * - vertex indices are packed into 1 VGPR
1193 * - Navi23 and later chips can optionally skip the gs_alloc_req message
1194 *
1195 * NGG passthrough still allows the use of LDS.
1196 */
1197 return sel->stage != MESA_SHADER_GEOMETRY && !si_shader_culling_enabled(shader);
1198 }
1199
1200 template <enum si_has_tess HAS_TESS>
gfx10_emit_shader_ngg(struct si_context * sctx,unsigned index)1201 static void gfx10_emit_shader_ngg(struct si_context *sctx, unsigned index)
1202 {
1203 struct si_shader *shader = sctx->queued.named.gs;
1204
1205 if (shader->selector->stage == MESA_SHADER_GEOMETRY)
1206 gfx9_set_gs_sgpr_num_es_outputs(sctx, shader->ngg.esgs_vertex_stride);
1207
1208 radeon_begin(&sctx->gfx_cs);
1209 if (HAS_TESS) {
1210 radeon_opt_set_context_reg(R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
1211 shader->vgt_tf_param);
1212 }
1213 radeon_opt_set_context_reg(R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
1214 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
1215 shader->ngg.ge_max_output_per_subgroup);
1216 radeon_opt_set_context_reg(R_028B4C_GE_NGG_SUBGRP_CNTL, SI_TRACKED_GE_NGG_SUBGRP_CNTL,
1217 shader->ngg.ge_ngg_subgrp_cntl);
1218 radeon_opt_set_context_reg(R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
1219 shader->ngg.vgt_primitiveid_en);
1220 if (sctx->gfx_level < GFX11) {
1221 radeon_opt_set_context_reg(R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1222 shader->ngg.vgt_gs_onchip_cntl);
1223 }
1224 radeon_opt_set_context_reg(R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1225 shader->ngg.vgt_gs_max_vert_out);
1226 radeon_opt_set_context_reg(R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
1227 shader->ngg.vgt_gs_instance_cnt);
1228 radeon_opt_set_context_reg(R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
1229 shader->ngg.spi_vs_out_config);
1230 radeon_opt_set_context_reg(R_02870C_SPI_SHADER_POS_FORMAT,
1231 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1232 shader->ngg.spi_shader_pos_format);
1233 radeon_opt_set_context_reg(R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
1234 shader->ngg.pa_cl_vte_cntl);
1235 radeon_end_update_context_roll();
1236
1237 /* These don't cause a context roll. */
1238 radeon_begin_again(&sctx->gfx_cs);
1239 if (sctx->screen->info.uses_kernel_cu_mask) {
1240 radeon_opt_set_sh_reg_idx(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
1241 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
1242 3, shader->ngg.spi_shader_pgm_rsrc3_gs);
1243 radeon_opt_set_sh_reg_idx(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1244 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
1245 3, shader->ngg.spi_shader_pgm_rsrc4_gs);
1246 } else {
1247 radeon_opt_set_sh_reg(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
1248 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
1249 shader->ngg.spi_shader_pgm_rsrc3_gs);
1250 radeon_opt_set_sh_reg(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1251 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
1252 shader->ngg.spi_shader_pgm_rsrc4_gs);
1253 }
1254 radeon_opt_set_uconfig_reg(R_030980_GE_PC_ALLOC, SI_TRACKED_GE_PC_ALLOC,
1255 shader->ngg.ge_pc_alloc);
1256 radeon_end();
1257 }
1258
1259 template <enum si_has_tess HAS_TESS>
gfx11_dgpu_emit_shader_ngg(struct si_context * sctx,unsigned index)1260 static void gfx11_dgpu_emit_shader_ngg(struct si_context *sctx, unsigned index)
1261 {
1262 struct si_shader *shader = sctx->queued.named.gs;
1263
1264 if (shader->selector->stage == MESA_SHADER_GEOMETRY)
1265 gfx9_set_gs_sgpr_num_es_outputs(sctx, shader->ngg.esgs_vertex_stride);
1266
1267 radeon_begin(&sctx->gfx_cs);
1268 gfx11_begin_packed_context_regs();
1269 if (HAS_TESS) {
1270 gfx11_opt_set_context_reg(R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
1271 shader->vgt_tf_param);
1272 }
1273 gfx11_opt_set_context_reg(R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
1274 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
1275 shader->ngg.ge_max_output_per_subgroup);
1276 gfx11_opt_set_context_reg(R_028B4C_GE_NGG_SUBGRP_CNTL, SI_TRACKED_GE_NGG_SUBGRP_CNTL,
1277 shader->ngg.ge_ngg_subgrp_cntl);
1278 gfx11_opt_set_context_reg(R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
1279 shader->ngg.vgt_primitiveid_en);
1280 gfx11_opt_set_context_reg(R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1281 shader->ngg.vgt_gs_max_vert_out);
1282 gfx11_opt_set_context_reg(R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
1283 shader->ngg.vgt_gs_instance_cnt);
1284 gfx11_opt_set_context_reg(R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
1285 shader->ngg.spi_vs_out_config);
1286 gfx11_opt_set_context_reg(R_02870C_SPI_SHADER_POS_FORMAT, SI_TRACKED_SPI_SHADER_POS_FORMAT,
1287 shader->ngg.spi_shader_pos_format);
1288 gfx11_opt_set_context_reg(R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
1289 shader->ngg.pa_cl_vte_cntl);
1290 gfx11_end_packed_context_regs();
1291
1292 assert(!sctx->screen->info.uses_kernel_cu_mask);
1293 if (sctx->screen->info.has_set_sh_pairs_packed) {
1294 gfx11_opt_push_gfx_sh_reg(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
1295 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
1296 shader->gs.spi_shader_pgm_rsrc3_gs);
1297 gfx11_opt_push_gfx_sh_reg(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1298 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
1299 shader->gs.spi_shader_pgm_rsrc4_gs);
1300 } else {
1301 if (sctx->screen->info.uses_kernel_cu_mask) {
1302 radeon_opt_set_sh_reg_idx(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
1303 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
1304 3, shader->ngg.spi_shader_pgm_rsrc3_gs);
1305 radeon_opt_set_sh_reg_idx(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1306 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
1307 3, shader->ngg.spi_shader_pgm_rsrc4_gs);
1308 } else {
1309 radeon_opt_set_sh_reg(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
1310 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
1311 shader->ngg.spi_shader_pgm_rsrc3_gs);
1312 radeon_opt_set_sh_reg(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1313 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
1314 shader->ngg.spi_shader_pgm_rsrc4_gs);
1315 }
1316 }
1317
1318 radeon_opt_set_uconfig_reg(R_030980_GE_PC_ALLOC, SI_TRACKED_GE_PC_ALLOC,
1319 shader->ngg.ge_pc_alloc);
1320 radeon_end();
1321 }
1322
1323 template <enum si_has_tess HAS_TESS>
gfx12_emit_shader_ngg(struct si_context * sctx,unsigned index)1324 static void gfx12_emit_shader_ngg(struct si_context *sctx, unsigned index)
1325 {
1326 struct si_shader *shader = sctx->queued.named.gs;
1327
1328 if (shader->selector->stage == MESA_SHADER_GEOMETRY)
1329 gfx9_set_gs_sgpr_num_es_outputs(sctx, shader->ngg.esgs_vertex_stride);
1330
1331 radeon_begin(&sctx->gfx_cs);
1332 gfx12_begin_context_regs();
1333 if (HAS_TESS) {
1334 gfx12_opt_set_context_reg(R_028AA4_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
1335 shader->vgt_tf_param);
1336 }
1337 gfx12_opt_set_context_reg(R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
1338 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
1339 shader->ngg.ge_max_output_per_subgroup);
1340 gfx12_opt_set_context_reg(R_028B4C_GE_NGG_SUBGRP_CNTL, SI_TRACKED_GE_NGG_SUBGRP_CNTL,
1341 shader->ngg.ge_ngg_subgrp_cntl);
1342 gfx12_opt_set_context_reg(R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1343 shader->ngg.vgt_gs_max_vert_out);
1344 gfx12_opt_set_context_reg(R_028B3C_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
1345 shader->ngg.vgt_gs_instance_cnt);
1346 gfx12_opt_set_context_reg(R_02864C_SPI_SHADER_POS_FORMAT, SI_TRACKED_SPI_SHADER_POS_FORMAT,
1347 shader->ngg.spi_shader_pos_format);
1348 gfx12_opt_set_context_reg(R_028814_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
1349 shader->ngg.pa_cl_vte_cntl);
1350 gfx12_end_context_regs();
1351
1352 radeon_opt_set_uconfig_reg(R_030988_VGT_PRIMITIVEID_EN,
1353 SI_TRACKED_VGT_PRIMITIVEID_EN_UCONFIG,
1354 shader->ngg.vgt_primitiveid_en);
1355 radeon_end(); /* don't track context rolls on GFX12 */
1356
1357 assert(!sctx->screen->info.uses_kernel_cu_mask);
1358 gfx12_opt_push_gfx_sh_reg(R_00B220_SPI_SHADER_PGM_RSRC4_GS,
1359 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
1360 shader->ngg.spi_shader_pgm_rsrc4_gs);
1361 }
1362
si_get_input_prim(const struct si_shader_selector * gs,const union si_shader_key * key,bool return_unknown)1363 unsigned si_get_input_prim(const struct si_shader_selector *gs, const union si_shader_key *key,
1364 bool return_unknown)
1365 {
1366 if (gs->stage == MESA_SHADER_GEOMETRY)
1367 return gs->info.base.gs.input_primitive;
1368
1369 if (gs->stage == MESA_SHADER_TESS_EVAL) {
1370 if (gs->info.base.tess.point_mode)
1371 return MESA_PRIM_POINTS;
1372 if (gs->info.base.tess._primitive_mode == TESS_PRIMITIVE_ISOLINES)
1373 return MESA_PRIM_LINES;
1374 return MESA_PRIM_TRIANGLES;
1375 }
1376
1377 assert(gs->stage == MESA_SHADER_VERTEX);
1378
1379 if (key->ge.opt.ngg_culling & SI_NGG_CULL_VS_LINES)
1380 return MESA_PRIM_LINES;
1381
1382 switch (key->ge.opt.ngg_vs_streamout_num_verts_per_prim) {
1383 case 3:
1384 return MESA_PRIM_TRIANGLES;
1385 case 2:
1386 return MESA_PRIM_LINES;
1387 case 1:
1388 return MESA_PRIM_POINTS;
1389 }
1390
1391 if (return_unknown)
1392 return MESA_PRIM_UNKNOWN;
1393 else
1394 return MESA_PRIM_TRIANGLES; /* worst case for all callers */
1395 }
1396
1397 /* Return a simplified primitive type, e.g. don't return *_STRIP and *_FAN.
1398 * This returns MESA_PRIM_UNKNOWN if the primitive type is not known at compile time.
1399 */
si_get_output_prim_simplified(const struct si_shader_selector * sel,const union si_shader_key * key)1400 unsigned si_get_output_prim_simplified(const struct si_shader_selector *sel,
1401 const union si_shader_key *key)
1402 {
1403 if (sel->stage == MESA_SHADER_GEOMETRY) {
1404 if (util_rast_prim_is_triangles(sel->info.base.gs.output_primitive))
1405 return MESA_PRIM_TRIANGLES;
1406 else if (util_prim_is_lines(sel->info.base.gs.output_primitive))
1407 return MESA_PRIM_LINES;
1408 else
1409 return MESA_PRIM_POINTS;
1410 }
1411
1412 if (sel->stage == MESA_SHADER_VERTEX && sel->info.base.vs.blit_sgprs_amd)
1413 return SI_PRIM_RECTANGLE_LIST;
1414
1415 /* It's the same as the input primitive type for VS and TES. */
1416 return si_get_input_prim(sel, key, true);
1417 }
1418
si_get_num_vertices_per_output_prim(struct si_shader * shader)1419 unsigned si_get_num_vertices_per_output_prim(struct si_shader *shader)
1420 {
1421 unsigned prim = si_get_output_prim_simplified(shader->selector, &shader->key);
1422
1423 switch (prim) {
1424 case MESA_PRIM_TRIANGLES:
1425 case SI_PRIM_RECTANGLE_LIST:
1426 return 3;
1427 case MESA_PRIM_LINES:
1428 return 2;
1429 case MESA_PRIM_POINTS:
1430 return 1;
1431 case MESA_PRIM_UNKNOWN:
1432 return 0;
1433 default:
1434 unreachable("unexpected prim type");
1435 }
1436 }
1437
si_get_vs_out_cntl(const struct si_shader_selector * sel,const struct si_shader * shader,bool ngg)1438 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel,
1439 const struct si_shader *shader, bool ngg)
1440 {
1441 /* Clip distances can be killed, but cull distances can't. */
1442 unsigned clipcull_mask = (sel->info.clipdist_mask & ~shader->key.ge.opt.kill_clip_distances) |
1443 sel->info.culldist_mask;
1444 bool writes_psize = sel->info.writes_psize && !shader->key.ge.opt.kill_pointsize;
1445 bool writes_layer = sel->info.writes_layer && !shader->key.ge.opt.kill_layer;
1446 bool misc_vec_ena = writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1447 writes_layer || sel->info.writes_viewport_index ||
1448 sel->screen->options.vrs2x2;
1449
1450 return S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipcull_mask & 0x0F) != 0) |
1451 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipcull_mask & 0xF0) != 0) |
1452 S_02881C_USE_VTX_POINT_SIZE(writes_psize) |
1453 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1454 S_02881C_USE_VTX_VRS_RATE(sel->screen->options.vrs2x2) |
1455 S_02881C_USE_VTX_RENDER_TARGET_INDX(writes_layer) |
1456 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1457 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1458 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena ||
1459 (sel->screen->info.gfx_level >= GFX10_3 &&
1460 shader->info.nr_pos_exports > 1));
1461 }
1462
1463 /* Return the number of allocated param exports. This can be more than the number of param
1464 * exports in the shader.
1465 */
si_shader_num_alloc_param_exports(struct si_shader * shader)1466 unsigned si_shader_num_alloc_param_exports(struct si_shader *shader)
1467 {
1468 unsigned num_params = shader->info.nr_param_exports;
1469
1470 /* Since there is no alloc/dealloc mechanism for the 12-bit ordered IDs on GFX12, they can wrap
1471 * around if there are more than 2^12 workgroups, causing 2 workgroups to get the same
1472 * ordered ID, which can deadlock the "ordered add" loop.
1473 *
1474 * The recommended solution is to use the alloc/dealloc mechanism of the attribute ring to limit
1475 * the number of workgroups in flight and thus the number of ordered IDs in flight.
1476 */
1477 if (shader->selector->screen->info.gfx_level >= GFX12 && si_shader_uses_streamout(shader))
1478 num_params = MAX2(num_params, 8);
1479
1480 return num_params;
1481 }
1482
1483 /**
1484 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1485 * in NGG mode.
1486 */
gfx10_shader_ngg(struct si_screen * sscreen,struct si_shader * shader)1487 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1488 {
1489 const struct si_shader_selector *gs_sel = shader->selector;
1490 const struct si_shader_info *gs_info = &gs_sel->info;
1491 const gl_shader_stage gs_stage = shader->selector->stage;
1492 const struct si_shader_selector *es_sel =
1493 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1494 const struct si_shader_info *es_info = &es_sel->info;
1495 const gl_shader_stage es_stage = es_sel->stage;
1496 unsigned num_user_sgprs;
1497 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1498 uint64_t va;
1499 bool window_space = gs_sel->stage == MESA_SHADER_VERTEX ?
1500 gs_info->base.vs.window_space_position : 0;
1501 bool es_enable_prim_id = shader->key.ge.mono.u.vs_export_prim_id || es_info->uses_primid;
1502 unsigned gs_num_invocations = gs_sel->stage == MESA_SHADER_GEOMETRY ?
1503 CLAMP(gs_info->base.gs.invocations, 1, 32) : 0;
1504 unsigned input_prim = si_get_input_prim(gs_sel, &shader->key, false);
1505
1506 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader, NULL);
1507 if (!pm4)
1508 return;
1509
1510 if (sscreen->info.gfx_level >= GFX12) {
1511 if (es_stage == MESA_SHADER_TESS_EVAL)
1512 pm4->atom.emit = gfx12_emit_shader_ngg<TESS_ON>;
1513 else
1514 pm4->atom.emit = gfx12_emit_shader_ngg<TESS_OFF>;
1515 } else if (sscreen->info.has_set_context_pairs_packed) {
1516 if (es_stage == MESA_SHADER_TESS_EVAL)
1517 pm4->atom.emit = gfx11_dgpu_emit_shader_ngg<TESS_ON>;
1518 else
1519 pm4->atom.emit = gfx11_dgpu_emit_shader_ngg<TESS_OFF>;
1520 } else {
1521 if (es_stage == MESA_SHADER_TESS_EVAL)
1522 pm4->atom.emit = gfx10_emit_shader_ngg<TESS_ON>;
1523 else
1524 pm4->atom.emit = gfx10_emit_shader_ngg<TESS_OFF>;
1525 }
1526
1527 va = shader->bo->gpu_address;
1528
1529 if (es_stage == MESA_SHADER_VERTEX) {
1530 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1531
1532 if (es_info->base.vs.blit_sgprs_amd) {
1533 num_user_sgprs =
1534 SI_SGPR_VS_BLIT_DATA + es_info->base.vs.blit_sgprs_amd;
1535 } else {
1536 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_GS_NUM_USER_SGPR);
1537 }
1538 } else {
1539 assert(es_stage == MESA_SHADER_TESS_EVAL);
1540 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1541 num_user_sgprs = GFX9_GS_NUM_USER_SGPR;
1542 }
1543
1544 /* Primitives with adjancency can only occur without tessellation. */
1545 assert(gs_info->gs_input_verts_per_prim <= 3 || es_stage == MESA_SHADER_VERTEX);
1546
1547 if (sscreen->info.gfx_level >= GFX12) {
1548 if (gs_info->gs_input_verts_per_prim >= 4)
1549 gs_vgpr_comp_cnt = 2; /* VGPR2 contains offsets 3-5 */
1550 else if ((gs_stage == MESA_SHADER_GEOMETRY && gs_info->uses_primid) ||
1551 (gs_stage == MESA_SHADER_VERTEX && shader->key.ge.mono.u.vs_export_prim_id))
1552 gs_vgpr_comp_cnt = 1; /* VGPR1 contains PrimitiveID */
1553 else
1554 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0-2, edgeflags, GS invocation ID. */
1555 } else {
1556 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1557 * VGPR[0:4] are always loaded.
1558 *
1559 * Vertex shaders always need to load VGPR3, because they need to
1560 * pass edge flags for decomposed primitives (such as quads) to the PA
1561 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1562 */
1563 if (gs_info->uses_invocationid ||
1564 (gfx10_has_variable_edgeflags(shader) && !gfx10_is_ngg_passthrough(shader)))
1565 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1566 else if ((gs_stage == MESA_SHADER_GEOMETRY && gs_info->uses_primid) ||
1567 (gs_stage == MESA_SHADER_VERTEX && shader->key.ge.mono.u.vs_export_prim_id))
1568 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1569 else if (input_prim >= MESA_PRIM_TRIANGLES && !gfx10_is_ngg_passthrough(shader))
1570 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1571 else
1572 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1573 }
1574
1575 if (sscreen->info.gfx_level >= GFX12) {
1576 ac_pm4_set_reg(&pm4->base, R_00B224_SPI_SHADER_PGM_LO_ES, va >> 8);
1577 } else {
1578 ac_pm4_set_reg(&pm4->base, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1579 }
1580
1581 ac_pm4_set_reg(&pm4->base, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1582 S_00B228_VGPRS(si_shader_encode_vgprs(shader)) |
1583 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1584 S_00B228_DX10_CLAMP(sscreen->info.gfx_level < GFX12) |
1585 S_00B228_MEM_ORDERED(si_shader_mem_ordered(shader)) |
1586 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1587 ac_pm4_set_reg(&pm4->base, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1588 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1589 S_00B22C_USER_SGPR(num_user_sgprs) |
1590 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1591 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1592 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL) |
1593 S_00B22C_LDS_SIZE(shader->config.lds_size));
1594
1595 /* Set register values emitted conditionally in gfx10_emit_shader_ngg_*. */
1596 shader->ngg.spi_shader_pos_format =
1597 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1598 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
1599 : V_02870C_SPI_SHADER_NONE) |
1600 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP
1601 : V_02870C_SPI_SHADER_NONE) |
1602 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP
1603 : V_02870C_SPI_SHADER_NONE);
1604 shader->ngg.ge_max_output_per_subgroup = S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1605 shader->ngg.vgt_gs_instance_cnt =
1606 S_028B90_ENABLE(gs_num_invocations > 1) |
1607 S_028B90_CNT(gs_num_invocations) |
1608 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(shader->ngg.max_vert_out_per_gs_instance);
1609 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, shader, true);
1610
1611 if (gs_stage == MESA_SHADER_GEOMETRY) {
1612 shader->ngg.esgs_vertex_stride = es_sel->info.esgs_vertex_stride / 4;
1613 shader->ngg.vgt_gs_max_vert_out = gs_sel->info.base.gs.vertices_out;
1614 shader->ngg.ge_ngg_subgrp_cntl = S_028B4C_PRIM_AMP_FACTOR(gs_sel->info.base.gs.vertices_out);
1615 } else {
1616 shader->ngg.esgs_vertex_stride = 1;
1617 shader->ngg.vgt_gs_max_vert_out = 1;
1618 shader->ngg.ge_ngg_subgrp_cntl = S_028B4C_PRIM_AMP_FACTOR(1);
1619 }
1620
1621 if (es_stage == MESA_SHADER_TESS_EVAL)
1622 si_set_tesseval_regs(sscreen, es_sel, shader);
1623
1624 shader->ngg.vgt_primitiveid_en =
1625 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader->key.ge.mono.u.vs_export_prim_id ||
1626 gs_sel->info.writes_primid);
1627
1628 if (sscreen->info.gfx_level >= GFX12) {
1629 unsigned num_params = si_shader_num_alloc_param_exports(shader);
1630 unsigned wave_limit_per_se = 0x3ff;
1631
1632 /* This tuning adds up to 50% streamout performance. */
1633 if (si_shader_uses_streamout(shader)) {
1634 unsigned num_streamout_vec4s = DIV_ROUND_UP(shader->selector->info.num_streamout_components, 4);
1635
1636 /* TODO: Tested on a pre-production chip. Re-test on the final chip. */
1637 if (num_streamout_vec4s <= 4)
1638 wave_limit_per_se = 48;
1639 else if (num_streamout_vec4s <= 5)
1640 wave_limit_per_se = 24;
1641 else if (num_streamout_vec4s <= 6)
1642 wave_limit_per_se = 20;
1643 else if (num_streamout_vec4s <= 8)
1644 wave_limit_per_se = 18;
1645 else if (num_streamout_vec4s <= 11)
1646 wave_limit_per_se = 17;
1647 else if (num_streamout_vec4s <= 12)
1648 wave_limit_per_se = 16;
1649 else if (num_streamout_vec4s <= 15)
1650 wave_limit_per_se = 15;
1651 else
1652 wave_limit_per_se = 14;
1653 }
1654
1655 shader->ngg.spi_shader_pgm_rsrc4_gs = S_00B220_SPI_SHADER_LATE_ALLOC_GS(127) |
1656 S_00B220_GLG_FORCE_DISABLE(1) |
1657 S_00B220_WAVE_LIMIT(wave_limit_per_se) |
1658 S_00B220_INST_PREF_SIZE(si_get_shader_prefetch_size(shader));
1659 shader->ngg.spi_vs_out_config = S_00B0C4_VS_EXPORT_COUNT(MAX2(num_params, 1) - 1) |
1660 S_00B0C4_NO_PC_EXPORT(num_params == 0);
1661 } else {
1662 unsigned late_alloc_wave64, cu_mask;
1663
1664 ac_compute_late_alloc(&sscreen->info, true, si_shader_culling_enabled(shader),
1665 shader->config.scratch_bytes_per_wave > 0,
1666 &late_alloc_wave64, &cu_mask);
1667
1668 /* Oversubscribe PC. This improves performance when there are too many varyings. */
1669 unsigned oversub_pc_lines, oversub_pc_factor = 1;
1670
1671 if (si_shader_culling_enabled(shader)) {
1672 /* Be more aggressive with NGG culling. */
1673 if (shader->info.nr_param_exports > 4)
1674 oversub_pc_factor = 4;
1675 else if (shader->info.nr_param_exports > 2)
1676 oversub_pc_factor = 3;
1677 else
1678 oversub_pc_factor = 2;
1679 }
1680 oversub_pc_lines = late_alloc_wave64 ? (sscreen->info.pc_lines / 4) * oversub_pc_factor : 0;
1681 shader->ngg.ge_pc_alloc = S_030980_OVERSUB_EN(oversub_pc_lines > 0) |
1682 S_030980_NUM_PC_LINES(oversub_pc_lines - 1);
1683 shader->ngg.vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(es_enable_prim_id);
1684 shader->ngg.spi_shader_pgm_rsrc3_gs =
1685 ac_apply_cu_en(S_00B21C_CU_EN(cu_mask) |
1686 S_00B21C_WAVE_LIMIT(0x3F),
1687 C_00B21C_CU_EN, 0, &sscreen->info);
1688 shader->ngg.spi_shader_pgm_rsrc4_gs = S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64);
1689 shader->ngg.spi_vs_out_config =
1690 S_0286C4_VS_EXPORT_COUNT(MAX2(shader->info.nr_param_exports, 1) - 1) |
1691 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1692
1693 if (sscreen->info.gfx_level >= GFX11) {
1694 shader->ngg.spi_shader_pgm_rsrc4_gs |=
1695 ac_apply_cu_en(S_00B204_CU_EN_GFX11(0x1) |
1696 S_00B204_INST_PREF_SIZE(si_get_shader_prefetch_size(shader)),
1697 C_00B204_CU_EN_GFX11, 16, &sscreen->info);
1698 } else {
1699 shader->ngg.spi_shader_pgm_rsrc4_gs |=
1700 ac_apply_cu_en(S_00B204_CU_EN_GFX10(0xffff),
1701 C_00B204_CU_EN_GFX10, 16, &sscreen->info);
1702 }
1703 }
1704
1705 if (sscreen->info.gfx_level >= GFX11) {
1706 /* This should be <= 252 for performance on Gfx11. 256 works too but is slower. */
1707 unsigned max_prim_grp_size = sscreen->info.gfx_level >= GFX12 ? 256 : 252;
1708 unsigned prim_amp_factor = gs_stage == MESA_SHADER_GEOMETRY ?
1709 gs_sel->info.base.gs.vertices_out : 1;
1710
1711 shader->ge_cntl = S_03096C_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1712 S_03096C_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1713 S_03096C_PRIM_GRP_SIZE_GFX11(
1714 CLAMP(max_prim_grp_size / MAX2(prim_amp_factor, 1), 1, 256)) |
1715 S_03096C_DIS_PG_SIZE_ADJUST_FOR_STRIP(sscreen->info.gfx_level >= GFX12);
1716 } else {
1717 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE_GFX10(shader->ngg.max_gsprims) |
1718 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts);
1719
1720 shader->ngg.vgt_gs_onchip_cntl =
1721 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1722 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1723 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1724
1725 /* On gfx10, the GE only checks against the maximum number of ES verts after
1726 * allocating a full GS primitive. So we need to ensure that whenever
1727 * this check passes, there is enough space for a full primitive without
1728 * vertex reuse. VERT_GRP_SIZE=256 doesn't need this. We should always get 256
1729 * if we have enough LDS.
1730 *
1731 * Tessellation is unaffected because it always sets GE_CNTL.VERT_GRP_SIZE = 0.
1732 */
1733 if ((sscreen->info.gfx_level == GFX10) &&
1734 (es_stage == MESA_SHADER_VERTEX || gs_stage == MESA_SHADER_VERTEX) && /* = no tess */
1735 shader->ngg.hw_max_esverts != 256 &&
1736 shader->ngg.hw_max_esverts > 5) {
1737 /* This could be based on the input primitive type. 5 is the worst case
1738 * for primitive types with adjacency.
1739 */
1740 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1741 shader->ge_cntl |= S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1742 }
1743 }
1744
1745 if (window_space) {
1746 shader->ngg.pa_cl_vte_cntl = S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1747 } else {
1748 shader->ngg.pa_cl_vte_cntl = S_028818_VTX_W0_FMT(1) |
1749 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1750 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1751 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1752 }
1753
1754 if (sscreen->info.gfx_level >= GFX12) {
1755 shader->ngg.vgt_shader_stages_en =
1756 S_028A98_GS_EN(gs_stage == MESA_SHADER_GEOMETRY) |
1757 S_028A98_PRIMGEN_PASSTHRU_NO_MSG(gfx10_is_ngg_passthrough(shader)) |
1758 S_028A98_GS_W32_EN(shader->wave_size == 32) |
1759 S_028A98_NGG_WAVE_ID_EN(si_shader_uses_streamout(shader));
1760 } else {
1761 shader->ngg.vgt_shader_stages_en =
1762 S_028B54_ES_EN(es_stage == MESA_SHADER_TESS_EVAL ?
1763 V_028B54_ES_STAGE_DS : V_028B54_ES_STAGE_REAL) |
1764 S_028B54_GS_EN(gs_stage == MESA_SHADER_GEOMETRY) |
1765 S_028B54_PRIMGEN_EN(1) |
1766 S_028B54_PRIMGEN_PASSTHRU_EN(gfx10_is_ngg_passthrough(shader)) |
1767 S_028B54_PRIMGEN_PASSTHRU_NO_MSG(gfx10_is_ngg_passthrough(shader) &&
1768 sscreen->info.family >= CHIP_NAVI23) |
1769 S_028B54_NGG_WAVE_ID_EN(si_shader_uses_streamout(shader)) |
1770 S_028B54_GS_W32_EN(shader->wave_size == 32) |
1771 S_028B54_MAX_PRIMGRP_IN_WAVE(2);
1772 }
1773
1774 ac_pm4_finalize(&pm4->base);
1775 }
1776
si_emit_shader_vs(struct si_context * sctx,unsigned index)1777 static void si_emit_shader_vs(struct si_context *sctx, unsigned index)
1778 {
1779 struct si_shader *shader = sctx->queued.named.vs;
1780
1781 radeon_begin(&sctx->gfx_cs);
1782 radeon_opt_set_context_reg(R_028A40_VGT_GS_MODE, SI_TRACKED_VGT_GS_MODE,
1783 shader->vs.vgt_gs_mode);
1784 radeon_opt_set_context_reg(R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
1785 shader->vs.vgt_primitiveid_en);
1786
1787 if (sctx->gfx_level <= GFX8) {
1788 radeon_opt_set_context_reg(R_028AB4_VGT_REUSE_OFF, SI_TRACKED_VGT_REUSE_OFF,
1789 shader->vs.vgt_reuse_off);
1790 }
1791
1792 radeon_opt_set_context_reg(R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
1793 shader->vs.spi_vs_out_config);
1794
1795 radeon_opt_set_context_reg(R_02870C_SPI_SHADER_POS_FORMAT,
1796 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1797 shader->vs.spi_shader_pos_format);
1798
1799 radeon_opt_set_context_reg(R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
1800 shader->vs.pa_cl_vte_cntl);
1801
1802 if (shader->selector->stage == MESA_SHADER_TESS_EVAL)
1803 radeon_opt_set_context_reg(R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
1804 shader->vgt_tf_param);
1805
1806 if (shader->vgt_vertex_reuse_block_cntl)
1807 radeon_opt_set_context_reg(R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1808 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1809 shader->vgt_vertex_reuse_block_cntl);
1810
1811 /* Required programming for tessellation. (legacy pipeline only) */
1812 if (sctx->gfx_level >= GFX10 && shader->selector->stage == MESA_SHADER_TESS_EVAL) {
1813 radeon_opt_set_context_reg(R_028A44_VGT_GS_ONCHIP_CNTL,
1814 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1815 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1816 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1817 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1818 }
1819
1820 radeon_end_update_context_roll();
1821
1822 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1823 if (sctx->gfx_level >= GFX10) {
1824 radeon_begin_again(&sctx->gfx_cs);
1825 radeon_opt_set_uconfig_reg(R_030980_GE_PC_ALLOC, SI_TRACKED_GE_PC_ALLOC,
1826 shader->vs.ge_pc_alloc);
1827 radeon_end();
1828 }
1829 }
1830
1831 /**
1832 * Compute the state for \p shader, which will run as a vertex shader on the
1833 * hardware.
1834 *
1835 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1836 * is the copy shader.
1837 */
si_shader_vs(struct si_screen * sscreen,struct si_shader * shader,struct si_shader_selector * gs)1838 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1839 struct si_shader_selector *gs)
1840 {
1841 const struct si_shader_info *info = &shader->selector->info;
1842 struct si_pm4_state *pm4;
1843 unsigned num_user_sgprs, vgpr_comp_cnt;
1844 uint64_t va;
1845 unsigned nparams, oc_lds_en;
1846 bool window_space = shader->selector->stage == MESA_SHADER_VERTEX ?
1847 info->base.vs.window_space_position : 0;
1848 bool enable_prim_id = shader->key.ge.mono.u.vs_export_prim_id || info->uses_primid;
1849
1850 assert(sscreen->info.gfx_level < GFX11);
1851
1852 pm4 = si_get_shader_pm4_state(shader, si_emit_shader_vs);
1853 if (!pm4)
1854 return;
1855
1856 /* We always write VGT_GS_MODE in the VS state, because every switch
1857 * between different shader pipelines involving a different GS or no
1858 * GS at all involves a switch of the VS (different GS use different
1859 * copy shaders). On the other hand, when the API switches from a GS to
1860 * no GS and then back to the same GS used originally, the GS state is
1861 * not sent again.
1862 */
1863 if (!gs) {
1864 unsigned mode = V_028A40_GS_OFF;
1865
1866 /* PrimID needs GS scenario A. */
1867 if (enable_prim_id)
1868 mode = V_028A40_GS_SCENARIO_A;
1869
1870 shader->vs.vgt_gs_mode = S_028A40_MODE(mode);
1871 shader->vs.vgt_primitiveid_en = enable_prim_id;
1872 } else {
1873 shader->vs.vgt_gs_mode =
1874 ac_vgt_gs_mode(gs->info.base.gs.vertices_out, sscreen->info.gfx_level);
1875 shader->vs.vgt_primitiveid_en = 0;
1876 }
1877
1878 if (sscreen->info.gfx_level <= GFX8) {
1879 /* Reuse needs to be set off if we write oViewport. */
1880 shader->vs.vgt_reuse_off = S_028AB4_REUSE_OFF(info->writes_viewport_index);
1881 }
1882
1883 va = shader->bo->gpu_address;
1884
1885 if (gs) {
1886 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1887 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1888 } else if (shader->selector->stage == MESA_SHADER_VERTEX) {
1889 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
1890
1891 if (info->base.vs.blit_sgprs_amd) {
1892 num_user_sgprs = SI_SGPR_VS_BLIT_DATA + info->base.vs.blit_sgprs_amd;
1893 } else {
1894 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
1895 }
1896 } else if (shader->selector->stage == MESA_SHADER_TESS_EVAL) {
1897 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1898 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1899 } else
1900 unreachable("invalid shader selector type");
1901
1902 /* VS is required to export at least one param. */
1903 nparams = MAX2(shader->info.nr_param_exports, 1);
1904 shader->vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1905
1906 if (sscreen->info.gfx_level >= GFX10) {
1907 shader->vs.spi_vs_out_config |=
1908 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1909 }
1910
1911 shader->vs.spi_shader_pos_format =
1912 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1913 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
1914 : V_02870C_SPI_SHADER_NONE) |
1915 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP
1916 : V_02870C_SPI_SHADER_NONE) |
1917 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP
1918 : V_02870C_SPI_SHADER_NONE);
1919 unsigned late_alloc_wave64, cu_mask;
1920 ac_compute_late_alloc(&sscreen->info, false, false,
1921 shader->config.scratch_bytes_per_wave > 0,
1922 &late_alloc_wave64, &cu_mask);
1923
1924 shader->vs.ge_pc_alloc = S_030980_OVERSUB_EN(late_alloc_wave64 > 0) |
1925 S_030980_NUM_PC_LINES(sscreen->info.pc_lines / 4 - 1);
1926 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, shader, false);
1927
1928 oc_lds_en = shader->selector->stage == MESA_SHADER_TESS_EVAL ? 1 : 0;
1929
1930 if (sscreen->info.gfx_level >= GFX7) {
1931 ac_pm4_set_reg_idx3(&pm4->base, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
1932 ac_apply_cu_en(S_00B118_CU_EN(cu_mask) |
1933 S_00B118_WAVE_LIMIT(0x3F),
1934 C_00B118_CU_EN, 0, &sscreen->info));
1935 ac_pm4_set_reg(&pm4->base, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(late_alloc_wave64));
1936 }
1937
1938 ac_pm4_set_reg(&pm4->base, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1939 ac_pm4_set_reg(&pm4->base, R_00B124_SPI_SHADER_PGM_HI_VS,
1940 S_00B124_MEM_BASE(sscreen->info.address32_hi >> 8));
1941
1942 uint32_t rsrc1 =
1943 S_00B128_VGPRS(si_shader_encode_vgprs(shader)) |
1944 S_00B128_SGPRS(si_shader_encode_sgprs(shader)) |
1945 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1946 S_00B128_DX10_CLAMP(1) |
1947 S_00B128_MEM_ORDERED(si_shader_mem_ordered(shader)) |
1948 S_00B128_FLOAT_MODE(shader->config.float_mode);
1949 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) | S_00B12C_OC_LDS_EN(oc_lds_en) |
1950 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1951
1952 if (sscreen->info.gfx_level >= GFX10)
1953 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
1954 else if (sscreen->info.gfx_level == GFX9)
1955 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
1956
1957 if (si_shader_uses_streamout(shader)) {
1958 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->info.base.xfb_stride[0]) |
1959 S_00B12C_SO_BASE1_EN(!!shader->selector->info.base.xfb_stride[1]) |
1960 S_00B12C_SO_BASE2_EN(!!shader->selector->info.base.xfb_stride[2]) |
1961 S_00B12C_SO_BASE3_EN(!!shader->selector->info.base.xfb_stride[3]) |
1962 S_00B12C_SO_EN(1);
1963 }
1964
1965 ac_pm4_set_reg(&pm4->base, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1966 ac_pm4_set_reg(&pm4->base, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1967
1968 if (window_space)
1969 shader->vs.pa_cl_vte_cntl = S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1970 else
1971 shader->vs.pa_cl_vte_cntl =
1972 S_028818_VTX_W0_FMT(1) | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1973 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1974 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1975
1976 if (shader->selector->stage == MESA_SHADER_TESS_EVAL)
1977 si_set_tesseval_regs(sscreen, shader->selector, shader);
1978
1979 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader);
1980 ac_pm4_finalize(&pm4->base);
1981 }
1982
si_get_spi_shader_col_format(struct si_shader * shader)1983 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1984 {
1985 unsigned spi_shader_col_format = shader->key.ps.part.epilog.spi_shader_col_format;
1986 unsigned value = 0, num_mrts = 0;
1987 unsigned i, num_targets = (util_last_bit(spi_shader_col_format) + 3) / 4;
1988
1989 /* Remove holes in spi_shader_col_format. */
1990 for (i = 0; i < num_targets; i++) {
1991 unsigned spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
1992
1993 if (spi_format) {
1994 value |= spi_format << (num_mrts * 4);
1995 num_mrts++;
1996 }
1997 }
1998
1999 return value;
2000 }
2001
gfx6_emit_shader_ps(struct si_context * sctx,unsigned index)2002 static void gfx6_emit_shader_ps(struct si_context *sctx, unsigned index)
2003 {
2004 struct si_shader *shader = sctx->queued.named.ps;
2005
2006 radeon_begin(&sctx->gfx_cs);
2007 radeon_opt_set_context_reg2(R_0286CC_SPI_PS_INPUT_ENA, SI_TRACKED_SPI_PS_INPUT_ENA,
2008 shader->ps.spi_ps_input_ena,
2009 shader->ps.spi_ps_input_addr);
2010 radeon_opt_set_context_reg(R_0286E0_SPI_BARYC_CNTL, SI_TRACKED_SPI_BARYC_CNTL,
2011 shader->ps.spi_baryc_cntl);
2012 radeon_opt_set_context_reg(R_0286D8_SPI_PS_IN_CONTROL, SI_TRACKED_SPI_PS_IN_CONTROL,
2013 shader->ps.spi_ps_in_control);
2014 radeon_opt_set_context_reg2(R_028710_SPI_SHADER_Z_FORMAT, SI_TRACKED_SPI_SHADER_Z_FORMAT,
2015 shader->ps.spi_shader_z_format,
2016 shader->ps.spi_shader_col_format);
2017 radeon_opt_set_context_reg(R_02823C_CB_SHADER_MASK, SI_TRACKED_CB_SHADER_MASK,
2018 shader->ps.cb_shader_mask);
2019 radeon_end_update_context_roll();
2020 }
2021
gfx11_dgpu_emit_shader_ps(struct si_context * sctx,unsigned index)2022 static void gfx11_dgpu_emit_shader_ps(struct si_context *sctx, unsigned index)
2023 {
2024 struct si_shader *shader = sctx->queued.named.ps;
2025
2026 radeon_begin(&sctx->gfx_cs);
2027 gfx11_begin_packed_context_regs();
2028 gfx11_opt_set_context_reg(R_0286CC_SPI_PS_INPUT_ENA, SI_TRACKED_SPI_PS_INPUT_ENA,
2029 shader->ps.spi_ps_input_ena);
2030 gfx11_opt_set_context_reg(R_0286D0_SPI_PS_INPUT_ADDR, SI_TRACKED_SPI_PS_INPUT_ADDR,
2031 shader->ps.spi_ps_input_addr);
2032 gfx11_opt_set_context_reg(R_0286E0_SPI_BARYC_CNTL, SI_TRACKED_SPI_BARYC_CNTL,
2033 shader->ps.spi_baryc_cntl);
2034 gfx11_opt_set_context_reg(R_0286D8_SPI_PS_IN_CONTROL, SI_TRACKED_SPI_PS_IN_CONTROL,
2035 shader->ps.spi_ps_in_control);
2036 gfx11_opt_set_context_reg(R_028710_SPI_SHADER_Z_FORMAT, SI_TRACKED_SPI_SHADER_Z_FORMAT,
2037 shader->ps.spi_shader_z_format);
2038 gfx11_opt_set_context_reg(R_028714_SPI_SHADER_COL_FORMAT, SI_TRACKED_SPI_SHADER_COL_FORMAT,
2039 shader->ps.spi_shader_col_format);
2040 gfx11_opt_set_context_reg(R_02823C_CB_SHADER_MASK, SI_TRACKED_CB_SHADER_MASK,
2041 shader->ps.cb_shader_mask);
2042 gfx11_end_packed_context_regs();
2043 radeon_end(); /* don't track context rolls on GFX11 */
2044 }
2045
gfx12_emit_shader_ps(struct si_context * sctx,unsigned index)2046 static void gfx12_emit_shader_ps(struct si_context *sctx, unsigned index)
2047 {
2048 struct si_shader *shader = sctx->queued.named.ps;
2049
2050 radeon_begin(&sctx->gfx_cs);
2051 gfx12_begin_context_regs();
2052 gfx12_opt_set_context_reg(R_028640_SPI_PS_IN_CONTROL, SI_TRACKED_SPI_PS_IN_CONTROL,
2053 shader->ps.spi_ps_in_control);
2054 gfx12_opt_set_context_reg(R_028650_SPI_SHADER_Z_FORMAT, SI_TRACKED_SPI_SHADER_Z_FORMAT,
2055 shader->ps.spi_shader_z_format);
2056 gfx12_opt_set_context_reg(R_028654_SPI_SHADER_COL_FORMAT, SI_TRACKED_SPI_SHADER_COL_FORMAT,
2057 shader->ps.spi_shader_col_format);
2058 gfx12_opt_set_context_reg(R_028658_SPI_BARYC_CNTL, SI_TRACKED_SPI_BARYC_CNTL,
2059 shader->ps.spi_baryc_cntl);
2060 gfx12_opt_set_context_reg(R_02865C_SPI_PS_INPUT_ENA, SI_TRACKED_SPI_PS_INPUT_ENA,
2061 shader->ps.spi_ps_input_ena);
2062 gfx12_opt_set_context_reg(R_028660_SPI_PS_INPUT_ADDR, SI_TRACKED_SPI_PS_INPUT_ADDR,
2063 shader->ps.spi_ps_input_addr);
2064 gfx12_opt_set_context_reg(R_028854_CB_SHADER_MASK, SI_TRACKED_CB_SHADER_MASK,
2065 shader->ps.cb_shader_mask);
2066 gfx12_opt_set_context_reg(R_028BBC_PA_SC_HISZ_CONTROL, SI_TRACKED_PA_SC_HISZ_CONTROL,
2067 shader->ps.pa_sc_hisz_control);
2068 gfx12_end_context_regs();
2069 radeon_end(); /* don't track context rolls on GFX12 */
2070 }
2071
si_shader_ps(struct si_screen * sscreen,struct si_shader * shader)2072 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
2073 {
2074 struct si_shader_info *info = &shader->selector->info;
2075 const unsigned input_ena = shader->config.spi_ps_input_ena;
2076 /* At least one of these is required to be set. */
2077 ASSERTED unsigned num_required_vgpr_inputs =
2078 G_0286CC_PERSP_SAMPLE_ENA(input_ena) + G_0286CC_PERSP_CENTER_ENA(input_ena) +
2079 G_0286CC_PERSP_CENTROID_ENA(input_ena) + G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) +
2080 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) + G_0286CC_LINEAR_CENTER_ENA(input_ena) +
2081 G_0286CC_LINEAR_CENTROID_ENA(input_ena) + G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena);
2082
2083 /* we need to enable at least one of them, otherwise we hang the GPU */
2084 assert(num_required_vgpr_inputs > 0);
2085 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
2086 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) || G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
2087 G_0286CC_PERSP_CENTER_ENA(input_ena) || G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
2088 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
2089
2090 /* Validate interpolation optimization flags (read as implications). */
2091 assert(!shader->key.ps.part.prolog.bc_optimize_for_persp ||
2092 (G_0286CC_PERSP_CENTER_ENA(input_ena) && G_0286CC_PERSP_CENTROID_ENA(input_ena)));
2093 assert(!shader->key.ps.part.prolog.bc_optimize_for_linear ||
2094 (G_0286CC_LINEAR_CENTER_ENA(input_ena) && G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
2095 assert(!shader->key.ps.part.prolog.force_persp_center_interp || num_required_vgpr_inputs == 1 ||
2096 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) && !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
2097 assert(!shader->key.ps.part.prolog.force_linear_center_interp || num_required_vgpr_inputs == 1 ||
2098 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
2099 assert(!shader->key.ps.part.prolog.force_persp_sample_interp || num_required_vgpr_inputs == 1 ||
2100 (!G_0286CC_PERSP_CENTER_ENA(input_ena) && !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
2101 assert(!shader->key.ps.part.prolog.force_linear_sample_interp || num_required_vgpr_inputs == 1 ||
2102 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
2103
2104 /* color_two_side always enables FRONT_FACE. Since st/mesa disables two-side colors if the back
2105 * face is culled, the only case when both color_two_side and force_front_face_input can be set
2106 * is when the front face is culled (which means force_front_face_input == -1).
2107 */
2108 assert(!shader->key.ps.opt.force_front_face_input || !G_0286CC_FRONT_FACE_ENA(input_ena) ||
2109 (shader->key.ps.part.prolog.color_two_side &&
2110 shader->key.ps.opt.force_front_face_input == -1));
2111
2112 /* Validate cases when the optimizations are off (read as implications). */
2113 assert(shader->key.ps.part.prolog.bc_optimize_for_persp ||
2114 !G_0286CC_PERSP_CENTER_ENA(input_ena) || !G_0286CC_PERSP_CENTROID_ENA(input_ena));
2115 assert(shader->key.ps.part.prolog.bc_optimize_for_linear ||
2116 !G_0286CC_LINEAR_CENTER_ENA(input_ena) || !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
2117
2118 /* DB_SHADER_CONTROL */
2119 shader->ps.db_shader_control =
2120 S_02880C_Z_EXPORT_ENABLE(shader->ps.writes_z) |
2121 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(shader->ps.writes_stencil) |
2122 S_02880C_MASK_EXPORT_ENABLE(shader->ps.writes_samplemask) |
2123 S_02880C_COVERAGE_TO_MASK_ENABLE(sscreen->info.gfx_level <= GFX10_3 &&
2124 shader->key.ps.part.epilog.alpha_to_coverage_via_mrtz) |
2125 S_02880C_KILL_ENABLE(si_shader_uses_discard(shader));
2126
2127 if (sscreen->info.gfx_level >= GFX12)
2128 shader->ps.pa_sc_hisz_control = S_028BBC_ROUND(2); /* required minimum value */
2129
2130 switch (info->base.fs.depth_layout) {
2131 case FRAG_DEPTH_LAYOUT_GREATER:
2132 shader->ps.db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2133 if (sscreen->info.gfx_level >= GFX12)
2134 shader->ps.pa_sc_hisz_control |= S_028BBC_CONSERVATIVE_Z_EXPORT(V_028BBC_EXPORT_GREATER_THAN_Z);
2135 break;
2136 case FRAG_DEPTH_LAYOUT_LESS:
2137 shader->ps.db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2138 if (sscreen->info.gfx_level >= GFX12)
2139 shader->ps.pa_sc_hisz_control |= S_028BBC_CONSERVATIVE_Z_EXPORT(V_028BBC_EXPORT_LESS_THAN_Z);
2140 break;
2141 default:;
2142 }
2143
2144 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2145 *
2146 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2147 * --|-----------|------------|------------|--------------------|-------------------|-------------
2148 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2149 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2150 * 2 | false | true | n/a | LateZ | 1 | 0
2151 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2152 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2153 *
2154 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2155 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2156 *
2157 * Don't use ReZ without profiling !!!
2158 *
2159 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2160 * shaders.
2161 */
2162 if (info->base.fs.early_fragment_tests) {
2163 /* Cases 3, 4. */
2164 shader->ps.db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2165 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2166 S_02880C_EXEC_ON_NOOP(info->base.writes_memory);
2167 } else if (info->base.writes_memory) {
2168 /* Case 2. */
2169 shader->ps.db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2170 S_02880C_EXEC_ON_HIER_FAIL(1);
2171 } else {
2172 /* Case 1. */
2173 shader->ps.db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2174 }
2175
2176 if (info->base.fs.post_depth_coverage)
2177 shader->ps.db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2178
2179 /* Bug workaround for smoothing (overrasterization) on GFX6. */
2180 if (sscreen->info.gfx_level == GFX6 && shader->key.ps.mono.poly_line_smoothing) {
2181 shader->ps.db_shader_control &= C_02880C_Z_ORDER;
2182 shader->ps.db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2183 }
2184
2185 if (sscreen->info.has_rbplus && !sscreen->info.rbplus_allowed)
2186 shader->ps.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
2187
2188 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
2189 * Possible values:
2190 * 0 -> Position = pixel center
2191 * 1 -> Position = pixel centroid
2192 * 2 -> Position = at sample position
2193 *
2194 * From GLSL 4.5 specification, section 7.1:
2195 * "The variable gl_FragCoord is available as an input variable from
2196 * within fragment shaders and it holds the window relative coordinates
2197 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
2198 * value can be for any location within the pixel, or one of the
2199 * fragment samples. The use of centroid does not further restrict
2200 * this value to be inside the current primitive."
2201 *
2202 * Meaning that centroid has no effect and we can return anything within
2203 * the pixel. Thus, return the value at sample position, because that's
2204 * the most accurate one shaders can get.
2205 */
2206 shader->ps.spi_baryc_cntl = S_0286E0_POS_FLOAT_LOCATION(2) |
2207 S_0286E0_POS_FLOAT_ULC(info->base.fs.pixel_center_integer) |
2208 S_0286E0_FRONT_FACE_ALL_BITS(0);
2209 shader->ps.spi_shader_col_format = si_get_spi_shader_col_format(shader);
2210 shader->ps.cb_shader_mask = ac_get_cb_shader_mask(shader->key.ps.part.epilog.spi_shader_col_format);
2211 shader->ps.spi_ps_input_ena = shader->config.spi_ps_input_ena;
2212 shader->ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
2213 shader->ps.num_interp = si_get_ps_num_interp(shader);
2214 shader->ps.spi_shader_z_format =
2215 ac_get_spi_shader_z_format(shader->ps.writes_z, shader->ps.writes_stencil,
2216 shader->ps.writes_samplemask,
2217 shader->key.ps.part.epilog.alpha_to_coverage_via_mrtz);
2218
2219 /* Ensure that some export memory is always allocated, for two reasons:
2220 *
2221 * 1) Correctness: The hardware ignores the EXEC mask if no export
2222 * memory is allocated, so KILL and alpha test do not work correctly
2223 * without this.
2224 * 2) Performance: Every shader needs at least a NULL export, even when
2225 * it writes no color/depth output. The NULL export instruction
2226 * stalls without this setting.
2227 *
2228 * Don't add this to CB_SHADER_MASK.
2229 *
2230 * GFX10 supports pixel shaders without exports by setting both
2231 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
2232 * instructions if any are present.
2233 *
2234 * RB+ depth-only rendering requires SPI_SHADER_32_R.
2235 */
2236 bool has_mrtz = shader->ps.spi_shader_z_format != V_028710_SPI_SHADER_ZERO;
2237
2238 if (!shader->ps.spi_shader_col_format) {
2239 if (shader->key.ps.part.epilog.rbplus_depth_only_opt) {
2240 shader->ps.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2241 } else if (!has_mrtz) {
2242 if (sscreen->info.gfx_level >= GFX10) {
2243 if (G_02880C_KILL_ENABLE(shader->ps.db_shader_control))
2244 shader->ps.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2245 } else {
2246 shader->ps.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2247 }
2248 }
2249 }
2250
2251 if (sscreen->info.gfx_level >= GFX12) {
2252 shader->ps.spi_ps_in_control = S_028640_PARAM_GEN(shader->key.ps.mono.point_smoothing) |
2253 S_028640_PS_W32_EN(shader->wave_size == 32);
2254 shader->ps.spi_gs_out_config_ps = S_00B0C4_NUM_INTERP(shader->ps.num_interp);
2255 } else {
2256 /* Enable PARAM_GEN for point smoothing.
2257 * Gfx11 workaround when there are no PS inputs but LDS is used.
2258 */
2259 bool param_gen = shader->key.ps.mono.point_smoothing ||
2260 (sscreen->info.gfx_level == GFX11 && !shader->ps.num_interp &&
2261 shader->config.lds_size);
2262
2263 shader->ps.spi_ps_in_control = S_0286D8_NUM_INTERP(shader->ps.num_interp) |
2264 S_0286D8_PARAM_GEN(param_gen) |
2265 S_0286D8_PS_W32_EN(shader->wave_size == 32);
2266 }
2267
2268 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader, NULL);
2269 if (!pm4)
2270 return;
2271
2272 if (sscreen->info.gfx_level >= GFX12)
2273 pm4->atom.emit = gfx12_emit_shader_ps;
2274 else if (sscreen->info.has_set_context_pairs_packed)
2275 pm4->atom.emit = gfx11_dgpu_emit_shader_ps;
2276 else
2277 pm4->atom.emit = gfx6_emit_shader_ps;
2278
2279 /* If multiple state sets are allowed to be in a bin, break the batch on a new PS. */
2280 if (sscreen->dpbb_allowed &&
2281 (sscreen->pbb_context_states_per_bin > 1 ||
2282 sscreen->pbb_persistent_states_per_bin > 1)) {
2283 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_EVENT_WRITE, 0, 0));
2284 ac_pm4_cmd_add(&pm4->base, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2285 }
2286
2287 if (sscreen->info.gfx_level >= GFX12) {
2288 ac_pm4_set_reg(&pm4->base, R_00B01C_SPI_SHADER_PGM_RSRC4_PS,
2289 S_00B01C_WAVE_LIMIT_GFX12(0x3FF) |
2290 S_00B01C_LDS_GROUP_SIZE_GFX12(1) |
2291 S_00B01C_INST_PREF_SIZE(si_get_shader_prefetch_size(shader)));
2292 } else if (sscreen->info.gfx_level >= GFX11) {
2293 unsigned cu_mask_ps = ac_gfx103_get_cu_mask_ps(&sscreen->info);
2294
2295 ac_pm4_set_reg_idx3(&pm4->base, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
2296 ac_apply_cu_en(S_00B004_CU_EN(cu_mask_ps >> 16) |
2297 S_00B004_INST_PREF_SIZE(si_get_shader_prefetch_size(shader)),
2298 C_00B004_CU_EN, 16, &sscreen->info));
2299 }
2300
2301 uint64_t va = shader->bo->gpu_address;
2302 ac_pm4_set_reg(&pm4->base, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
2303 ac_pm4_set_reg(&pm4->base, R_00B024_SPI_SHADER_PGM_HI_PS,
2304 S_00B024_MEM_BASE(sscreen->info.address32_hi >> 8));
2305
2306 ac_pm4_set_reg(&pm4->base, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
2307 S_00B028_VGPRS(si_shader_encode_vgprs(shader)) |
2308 S_00B028_SGPRS(si_shader_encode_sgprs(shader)) |
2309 S_00B028_DX10_CLAMP(sscreen->info.gfx_level < GFX12) |
2310 S_00B028_MEM_ORDERED(si_shader_mem_ordered(shader)) |
2311 S_00B028_FLOAT_MODE(shader->config.float_mode));
2312 ac_pm4_set_reg(&pm4->base, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
2313 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
2314 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
2315 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
2316 ac_pm4_finalize(&pm4->base);
2317 }
2318
si_shader_init_pm4_state(struct si_screen * sscreen,struct si_shader * shader)2319 static void si_shader_init_pm4_state(struct si_screen *sscreen, struct si_shader *shader)
2320 {
2321 assert(shader->wave_size);
2322
2323 switch (shader->selector->stage) {
2324 case MESA_SHADER_VERTEX:
2325 if (shader->key.ge.as_ls)
2326 si_shader_ls(sscreen, shader);
2327 else if (shader->key.ge.as_es)
2328 si_shader_es(sscreen, shader);
2329 else if (shader->key.ge.as_ngg)
2330 gfx10_shader_ngg(sscreen, shader);
2331 else
2332 si_shader_vs(sscreen, shader, NULL);
2333 break;
2334 case MESA_SHADER_TESS_CTRL:
2335 si_shader_hs(sscreen, shader);
2336 break;
2337 case MESA_SHADER_TESS_EVAL:
2338 if (shader->key.ge.as_es)
2339 si_shader_es(sscreen, shader);
2340 else if (shader->key.ge.as_ngg)
2341 gfx10_shader_ngg(sscreen, shader);
2342 else
2343 si_shader_vs(sscreen, shader, NULL);
2344 break;
2345 case MESA_SHADER_GEOMETRY:
2346 if (shader->key.ge.as_ngg) {
2347 gfx10_shader_ngg(sscreen, shader);
2348 } else {
2349 /* VS must be initialized first because GS uses its fields. */
2350 si_shader_vs(sscreen, shader->gs_copy_shader, shader->selector);
2351 si_shader_gs(sscreen, shader);
2352 }
2353 break;
2354 case MESA_SHADER_FRAGMENT:
2355 si_shader_ps(sscreen, shader);
2356 break;
2357 default:
2358 assert(0);
2359 }
2360
2361 assert(!(sscreen->debug_flags & DBG(SQTT)) || shader->pm4.base.spi_shader_pgm_lo_reg != 0);
2362 }
2363
si_clear_vs_key_inputs(union si_shader_key * key)2364 static void si_clear_vs_key_inputs(union si_shader_key *key)
2365 {
2366 key->ge.mono.instance_divisor_is_one = 0;
2367 key->ge.mono.instance_divisor_is_fetched = 0;
2368 key->ge.mono.vs_fetch_opencode = 0;
2369 memset(key->ge.mono.vs_fix_fetch, 0, sizeof(key->ge.mono.vs_fix_fetch));
2370 }
2371
si_vs_key_update_inputs(struct si_context * sctx)2372 void si_vs_key_update_inputs(struct si_context *sctx)
2373 {
2374 struct si_shader_selector *vs = sctx->shader.vs.cso;
2375 struct si_vertex_elements *elts = sctx->vertex_elements;
2376 union si_shader_key *key = &sctx->shader.vs.key;
2377
2378 if (!vs)
2379 return;
2380
2381 if (vs->info.base.vs.blit_sgprs_amd) {
2382 si_clear_vs_key_inputs(key);
2383 key->ge.opt.prefer_mono = 0;
2384 sctx->uses_nontrivial_vs_inputs = false;
2385 return;
2386 }
2387
2388 bool uses_nontrivial_vs_inputs = false;
2389
2390 if (elts->instance_divisor_is_one || elts->instance_divisor_is_fetched)
2391 uses_nontrivial_vs_inputs = true;
2392
2393 key->ge.mono.instance_divisor_is_one = elts->instance_divisor_is_one;
2394 key->ge.mono.instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
2395 key->ge.opt.prefer_mono = elts->instance_divisor_is_fetched;
2396
2397 unsigned count_mask = (1 << vs->info.num_inputs) - 1;
2398 unsigned fix = elts->fix_fetch_always & count_mask;
2399 unsigned opencode = elts->fix_fetch_opencode & count_mask;
2400
2401 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
2402 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
2403 while (mask) {
2404 unsigned i = u_bit_scan(&mask);
2405 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
2406 unsigned vbidx = elts->vertex_buffer_index[i];
2407 const struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
2408 unsigned align_mask = (1 << log_hw_load_size) - 1;
2409 if (vb->buffer_offset & align_mask) {
2410 fix |= 1 << i;
2411 opencode |= 1 << i;
2412 }
2413 }
2414 }
2415
2416 memset(key->ge.mono.vs_fix_fetch, 0, sizeof(key->ge.mono.vs_fix_fetch));
2417
2418 while (fix) {
2419 unsigned i = u_bit_scan(&fix);
2420 uint8_t fix_fetch = elts->fix_fetch[i];
2421
2422 key->ge.mono.vs_fix_fetch[i].bits = fix_fetch;
2423 if (fix_fetch)
2424 uses_nontrivial_vs_inputs = true;
2425 }
2426 key->ge.mono.vs_fetch_opencode = opencode;
2427 if (opencode)
2428 uses_nontrivial_vs_inputs = true;
2429
2430 sctx->uses_nontrivial_vs_inputs = uses_nontrivial_vs_inputs;
2431
2432 /* draw_vertex_state (display lists) requires that all VS input lowering is disabled
2433 * because its vertex elements never need any lowering.
2434 *
2435 * We just computed the key because we needed to set uses_nontrivial_vs_inputs, so that we know
2436 * whether the VS should be updated when we switch from draw_vertex_state to draw_vbo. Now
2437 * clear the VS input bits for draw_vertex_state. This should happen rarely because VS inputs
2438 * don't usually need any lowering.
2439 */
2440 if (uses_nontrivial_vs_inputs && sctx->force_trivial_vs_inputs)
2441 si_clear_vs_key_inputs(key);
2442 }
2443
si_get_vs_key_inputs(struct si_context * sctx,union si_shader_key * key)2444 static void si_get_vs_key_inputs(struct si_context *sctx, union si_shader_key *key)
2445 {
2446 key->ge.mono.instance_divisor_is_one = sctx->shader.vs.key.ge.mono.instance_divisor_is_one;
2447 key->ge.mono.instance_divisor_is_fetched = sctx->shader.vs.key.ge.mono.instance_divisor_is_fetched;
2448 key->ge.mono.vs_fetch_opencode = sctx->shader.vs.key.ge.mono.vs_fetch_opencode;
2449 memcpy(key->ge.mono.vs_fix_fetch, sctx->shader.vs.key.ge.mono.vs_fix_fetch,
2450 sizeof(key->ge.mono.vs_fix_fetch));
2451 }
2452
si_update_ps_inputs_read_or_disabled(struct si_context * sctx)2453 void si_update_ps_inputs_read_or_disabled(struct si_context *sctx)
2454 {
2455 struct si_shader_selector *ps = sctx->shader.ps.cso;
2456
2457 /* Find out if PS is disabled. */
2458 bool ps_disabled = true;
2459 if (ps) {
2460 bool ps_modifies_zs = ps->info.base.fs.uses_discard ||
2461 ps->info.writes_z ||
2462 ps->info.writes_stencil ||
2463 ps->info.writes_samplemask ||
2464 sctx->queued.named.blend->alpha_to_coverage ||
2465 sctx->queued.named.dsa->alpha_func != PIPE_FUNC_ALWAYS ||
2466 sctx->queued.named.rasterizer->poly_stipple_enable ||
2467 sctx->queued.named.rasterizer->point_smooth;
2468
2469 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
2470 (!ps_modifies_zs && !ps->info.base.writes_memory &&
2471 !si_any_colorbuffer_written(sctx));
2472 }
2473
2474 uint64_t ps_inputs_read_or_disabled;
2475
2476 if (ps_disabled) {
2477 ps_inputs_read_or_disabled = 0;
2478 } else {
2479 uint64_t inputs_read = ps->info.inputs_read;
2480
2481 if (ps->info.colors_read && sctx->queued.named.rasterizer->two_side) {
2482 if (inputs_read & BITFIELD64_BIT(SI_UNIQUE_SLOT_COL0))
2483 inputs_read |= BITFIELD64_BIT(SI_UNIQUE_SLOT_BFC0);
2484
2485 if (inputs_read & BITFIELD64_BIT(SI_UNIQUE_SLOT_COL1))
2486 inputs_read |= BITFIELD64_BIT(SI_UNIQUE_SLOT_BFC1);
2487 }
2488
2489 ps_inputs_read_or_disabled = inputs_read;
2490 }
2491
2492 if (sctx->ps_inputs_read_or_disabled != ps_inputs_read_or_disabled) {
2493 sctx->ps_inputs_read_or_disabled = ps_inputs_read_or_disabled;
2494 sctx->do_update_shaders = true;
2495 }
2496 }
2497
si_vs_ps_key_update_rast_prim_smooth_stipple(struct si_context * sctx)2498 void si_vs_ps_key_update_rast_prim_smooth_stipple(struct si_context *sctx)
2499 {
2500 struct si_shader_ctx_state *hw_vs = si_get_vs(sctx);
2501 struct si_shader_selector *ps = sctx->shader.ps.cso;
2502
2503 if (!hw_vs->cso || !ps)
2504 return;
2505
2506 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2507 union si_shader_key *vs_key = &hw_vs->key; /* could also be TES or GS before PS */
2508 union si_shader_key *ps_key = &sctx->shader.ps.key;
2509
2510 bool old_kill_pointsize = vs_key->ge.opt.kill_pointsize;
2511 bool old_color_two_side = ps_key->ps.part.prolog.color_two_side;
2512 bool old_poly_stipple = ps_key->ps.part.prolog.poly_stipple;
2513 bool old_poly_line_smoothing = ps_key->ps.mono.poly_line_smoothing;
2514 bool old_point_smoothing = ps_key->ps.mono.point_smoothing;
2515 int old_force_front_face_input = ps_key->ps.opt.force_front_face_input;
2516
2517 if (sctx->current_rast_prim == MESA_PRIM_POINTS) {
2518 vs_key->ge.opt.kill_pointsize = 0;
2519 ps_key->ps.part.prolog.color_two_side = 0;
2520 ps_key->ps.part.prolog.poly_stipple = 0;
2521 ps_key->ps.mono.poly_line_smoothing = 0;
2522 ps_key->ps.mono.point_smoothing = rs->point_smooth;
2523 ps_key->ps.opt.force_front_face_input = ps->info.uses_frontface;
2524 } else if (util_prim_is_lines(sctx->current_rast_prim)) {
2525 vs_key->ge.opt.kill_pointsize = hw_vs->cso->info.writes_psize;
2526 ps_key->ps.part.prolog.color_two_side = 0;
2527 ps_key->ps.part.prolog.poly_stipple = 0;
2528 ps_key->ps.mono.poly_line_smoothing = rs->line_smooth && sctx->framebuffer.nr_samples <= 1;
2529 ps_key->ps.mono.point_smoothing = 0;
2530 ps_key->ps.opt.force_front_face_input = ps->info.uses_frontface;
2531 } else {
2532 /* Triangles. */
2533 vs_key->ge.opt.kill_pointsize = hw_vs->cso->info.writes_psize &&
2534 !rs->polygon_mode_is_points;
2535 ps_key->ps.part.prolog.color_two_side = rs->two_side && ps->info.colors_read;
2536 ps_key->ps.part.prolog.poly_stipple = rs->poly_stipple_enable;
2537 ps_key->ps.mono.poly_line_smoothing = rs->poly_smooth && sctx->framebuffer.nr_samples <= 1;
2538 ps_key->ps.mono.point_smoothing = 0;
2539 ps_key->ps.opt.force_front_face_input = ps->info.uses_frontface ? rs->force_front_face_input : 0;
2540 }
2541
2542 if (vs_key->ge.opt.kill_pointsize != old_kill_pointsize ||
2543 ps_key->ps.part.prolog.color_two_side != old_color_two_side ||
2544 ps_key->ps.part.prolog.poly_stipple != old_poly_stipple ||
2545 ps_key->ps.mono.poly_line_smoothing != old_poly_line_smoothing ||
2546 ps_key->ps.mono.point_smoothing != old_point_smoothing ||
2547 ps_key->ps.opt.force_front_face_input != old_force_front_face_input)
2548 sctx->do_update_shaders = true;
2549 }
2550
si_get_vs_key_outputs(struct si_context * sctx,struct si_shader_selector * vs,union si_shader_key * key)2551 static void si_get_vs_key_outputs(struct si_context *sctx, struct si_shader_selector *vs,
2552 union si_shader_key *key)
2553 {
2554 key->ge.opt.kill_clip_distances = vs->info.clipdist_mask & ~sctx->queued.named.rasterizer->clip_plane_enable;
2555
2556 /* Find out which VS outputs aren't used by the PS. */
2557 uint64_t outputs_written = vs->info.outputs_written_before_ps;
2558 uint64_t linked = outputs_written & sctx->ps_inputs_read_or_disabled;
2559
2560 key->ge.opt.kill_layer = vs->info.writes_layer &&
2561 sctx->framebuffer.state.layers <= 1;
2562 key->ge.opt.kill_outputs = ~linked & outputs_written;
2563 key->ge.opt.ngg_culling = sctx->ngg_culling;
2564 key->ge.mono.u.vs_export_prim_id = vs->stage != MESA_SHADER_GEOMETRY &&
2565 sctx->shader.ps.cso && sctx->shader.ps.cso->info.uses_primid;
2566
2567 if (vs->info.enabled_streamout_buffer_mask) {
2568 if (sctx->streamout.enabled_mask) {
2569 key->ge.opt.remove_streamout = 0;
2570 key->ge.opt.ngg_vs_streamout_num_verts_per_prim =
2571 sctx->gfx_level >= GFX11 ? sctx->streamout.num_verts_per_prim : 0;
2572 } else {
2573 key->ge.opt.remove_streamout = 1;
2574 key->ge.opt.ngg_vs_streamout_num_verts_per_prim = 0;
2575 }
2576 } else {
2577 key->ge.opt.remove_streamout = 0;
2578 key->ge.opt.ngg_vs_streamout_num_verts_per_prim = 0;
2579 }
2580
2581 if (sctx->gfx_level >= GFX12)
2582 key->ge.mono.remove_streamout = key->ge.opt.remove_streamout;
2583 }
2584
si_clear_vs_key_outputs(struct si_context * sctx,struct si_shader_selector * vs,union si_shader_key * key)2585 static void si_clear_vs_key_outputs(struct si_context *sctx, struct si_shader_selector *vs,
2586 union si_shader_key *key)
2587 {
2588 key->ge.opt.kill_clip_distances = 0;
2589 key->ge.opt.kill_outputs = 0;
2590 key->ge.opt.remove_streamout = 0;
2591 key->ge.opt.ngg_culling = 0;
2592 key->ge.opt.ngg_vs_streamout_num_verts_per_prim = 0;
2593 key->ge.mono.u.vs_export_prim_id = 0;
2594 key->ge.mono.remove_streamout = 0;
2595 }
2596
si_ps_key_update_framebuffer(struct si_context * sctx)2597 void si_ps_key_update_framebuffer(struct si_context *sctx)
2598 {
2599 struct si_shader_selector *sel = sctx->shader.ps.cso;
2600 union si_shader_key *key = &sctx->shader.ps.key;
2601
2602 if (!sel)
2603 return;
2604
2605 if (sel->info.color0_writes_all_cbufs &&
2606 sel->info.colors_written == 0x1)
2607 key->ps.part.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
2608 else
2609 key->ps.part.epilog.last_cbuf = 0;
2610
2611 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2612 if (sctx->ps_uses_fbfetch) {
2613 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2614 struct pipe_resource *tex = cb0->texture;
2615
2616 /* 1D textures are allocated and used as 2D on GFX9. */
2617 key->ps.mono.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2618 key->ps.mono.fbfetch_is_1D =
2619 sctx->gfx_level != GFX9 &&
2620 (tex->target == PIPE_TEXTURE_1D || tex->target == PIPE_TEXTURE_1D_ARRAY);
2621 key->ps.mono.fbfetch_layered =
2622 tex->target == PIPE_TEXTURE_1D_ARRAY || tex->target == PIPE_TEXTURE_2D_ARRAY ||
2623 tex->target == PIPE_TEXTURE_CUBE || tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2624 tex->target == PIPE_TEXTURE_3D;
2625 } else {
2626 key->ps.mono.fbfetch_msaa = 0;
2627 key->ps.mono.fbfetch_is_1D = 0;
2628 key->ps.mono.fbfetch_layered = 0;
2629 }
2630 }
2631
si_ps_key_update_framebuffer_blend_dsa_rasterizer(struct si_context * sctx)2632 void si_ps_key_update_framebuffer_blend_dsa_rasterizer(struct si_context *sctx)
2633 {
2634 struct si_shader_selector *sel = sctx->shader.ps.cso;
2635 if (!sel)
2636 return;
2637
2638 union si_shader_key *key = &sctx->shader.ps.key;
2639 struct si_state_blend *blend = sctx->queued.named.blend;
2640 struct si_state_dsa *dsa = sctx->queued.named.dsa;
2641 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2642 bool alpha_to_coverage = sel->info.colors_written & 0x1 && blend->alpha_to_coverage &&
2643 rs->multisample_enable && sctx->framebuffer.nr_samples >= 2;
2644 unsigned need_src_alpha_4bit = blend->need_src_alpha_4bit;
2645
2646 /* Old key data for comparison. */
2647 struct si_ps_epilog_bits old_epilog;
2648 memcpy(&old_epilog, &key->ps.part.epilog, sizeof(old_epilog));
2649 bool old_prefer_mono = key->ps.opt.prefer_mono;
2650 #ifndef NDEBUG
2651 struct si_shader_key_ps old_key;
2652 memcpy(&old_key, &key->ps, sizeof(old_key));
2653 #endif
2654
2655 key->ps.part.epilog.kill_z = sel->info.writes_z &&
2656 (!sctx->framebuffer.state.zsbuf || !dsa->depth_enabled ||
2657 (sel->info.output_z_equals_input_z && !rs->multisample_enable));
2658 key->ps.part.epilog.kill_stencil = sel->info.writes_stencil &&
2659 (!sctx->framebuffer.has_stencil || !dsa->stencil_enabled);
2660
2661 /* Remove the gl_SampleMask fragment shader output if MSAA is disabled.
2662 * This is required for correctness and it's also an optimization.
2663 */
2664 key->ps.part.epilog.kill_samplemask = sel->info.writes_samplemask &&
2665 (sctx->framebuffer.nr_samples <= 1 ||
2666 !rs->multisample_enable);
2667
2668 key->ps.part.epilog.alpha_to_one = sel->info.colors_written & 0x1 && blend->alpha_to_one &&
2669 rs->multisample_enable;
2670 /* GFX11+ always exports alpha for alpha-to-coverage via mrtz. */
2671 key->ps.part.epilog.alpha_to_coverage_via_mrtz =
2672 alpha_to_coverage && (sctx->gfx_level >= GFX11 || key->ps.part.epilog.alpha_to_one) &&
2673 ((sel->info.writes_z && !key->ps.part.epilog.kill_z) ||
2674 (sel->info.writes_stencil && !key->ps.part.epilog.kill_stencil) ||
2675 (sel->info.writes_samplemask && !key->ps.part.epilog.kill_samplemask) ||
2676 /* If both alpha-to-coverage and alpha-to-one are enabled, alpha for alpha-to-coverage must
2677 * be exported from mrtz because mrt0.a must contain 1.0 for alpha-to-one. */
2678 key->ps.part.epilog.alpha_to_one);
2679
2680 /* If alpha-to-coverage isn't exported via MRTZ, set that we need to export alpha
2681 * through MRT0.
2682 */
2683 if (alpha_to_coverage && !key->ps.part.epilog.alpha_to_coverage_via_mrtz)
2684 need_src_alpha_4bit |= 0xf;
2685
2686 /* Select the shader color format based on whether
2687 * blending or alpha are needed.
2688 */
2689 key->ps.part.epilog.spi_shader_col_format =
2690 (blend->blend_enable_4bit & need_src_alpha_4bit &
2691 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
2692 (blend->blend_enable_4bit & ~need_src_alpha_4bit &
2693 sctx->framebuffer.spi_shader_col_format_blend) |
2694 (~blend->blend_enable_4bit & need_src_alpha_4bit &
2695 sctx->framebuffer.spi_shader_col_format_alpha) |
2696 (~blend->blend_enable_4bit & ~need_src_alpha_4bit &
2697 sctx->framebuffer.spi_shader_col_format);
2698 key->ps.part.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
2699
2700 key->ps.part.epilog.dual_src_blend_swizzle = sctx->gfx_level >= GFX11 &&
2701 blend->dual_src_blend &&
2702 (sel->info.colors_written_4bit & 0xff) == 0xff;
2703
2704 /* The output for dual source blending should have
2705 * the same format as the first output.
2706 */
2707 if (blend->dual_src_blend) {
2708 key->ps.part.epilog.spi_shader_col_format |=
2709 (key->ps.part.epilog.spi_shader_col_format & 0xf) << 4;
2710 }
2711
2712 /* If alpha-to-coverage is enabled, we have to export alpha
2713 * even if there is no color buffer.
2714 *
2715 * Gfx11 exports alpha-to-coverage via MRTZ if MRTZ is present.
2716 */
2717 if (!(key->ps.part.epilog.spi_shader_col_format & 0xf) && alpha_to_coverage &&
2718 !key->ps.part.epilog.alpha_to_coverage_via_mrtz)
2719 key->ps.part.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
2720
2721 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
2722 * to the range supported by the type if a channel has less
2723 * than 16 bits and the export format is 16_ABGR.
2724 */
2725 if (sctx->gfx_level <= GFX7 && sctx->family != CHIP_HAWAII) {
2726 key->ps.part.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
2727 key->ps.part.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
2728 }
2729
2730 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
2731 if (!key->ps.part.epilog.last_cbuf) {
2732 key->ps.part.epilog.spi_shader_col_format &= sel->info.colors_written_4bit;
2733 key->ps.part.epilog.color_is_int8 &= sel->info.colors_written;
2734 key->ps.part.epilog.color_is_int10 &= sel->info.colors_written;
2735 }
2736
2737 /* Enable RB+ for depth-only rendering. Registers must be programmed as follows:
2738 * CB_COLOR_CONTROL.MODE = CB_DISABLE
2739 * CB_COLOR0_INFO.FORMAT = COLOR_32
2740 * CB_COLOR0_INFO.NUMBER_TYPE = NUMBER_FLOAT
2741 * SPI_SHADER_COL_FORMAT.COL0_EXPORT_FORMAT = SPI_SHADER_32_R
2742 * SX_PS_DOWNCONVERT.MRT0 = SX_RT_EXPORT_32_R
2743 *
2744 * Also, the following conditions must be met.
2745 */
2746 key->ps.part.epilog.rbplus_depth_only_opt =
2747 sctx->screen->info.rbplus_allowed &&
2748 blend->cb_target_enabled_4bit == 0 && /* implies CB_DISABLE */
2749 !alpha_to_coverage &&
2750 !sel->info.base.writes_memory &&
2751 !key->ps.part.epilog.spi_shader_col_format;
2752
2753 /* Compile PS monolithically if it eliminates code or improves performance. */
2754 if (sel->info.colors_written_4bit &
2755 /* Dual source blending never has color buffer 1 enabled, so ignore it. */
2756 (blend->dual_src_blend ? 0xffffff0f : 0xffffffff) &
2757 ~(sctx->framebuffer.colorbuf_enabled_4bit & blend->cb_target_enabled_4bit)) {
2758 /* Eliminate shader code computing the color outputs that have missing color buffer
2759 * attachments or are disabled by colormask.
2760 */
2761 key->ps.opt.prefer_mono = 1;
2762 } else if (sctx->gfx_level >= GFX11 && sel->info.base.writes_memory) {
2763 /* On gfx11, pixel shaders that write memory should be compiled with an inlined epilog,
2764 * so that the compiler can see s_endpgm and deallocates VGPRs before memory stores return.
2765 */
2766 key->ps.opt.prefer_mono = 1;
2767 } else if (key->ps.part.epilog.kill_z || key->ps.part.epilog.kill_stencil ||
2768 key->ps.part.epilog.kill_samplemask) {
2769 /* Eliminate shader code computing the Z/S/samplemask outputs. */
2770 key->ps.opt.prefer_mono = 1;
2771 } else {
2772 key->ps.opt.prefer_mono = 0;
2773 }
2774
2775 /* Update shaders only if the key changed. */
2776 if (memcmp(&key->ps.part.epilog, &old_epilog, sizeof(old_epilog)) ||
2777 key->ps.opt.prefer_mono != old_prefer_mono) {
2778 sctx->do_update_shaders = true;
2779 } else {
2780 assert(memcmp(&key->ps, &old_key, sizeof(old_key)) == 0);
2781 }
2782 }
2783
si_ps_key_update_rasterizer(struct si_context * sctx)2784 void si_ps_key_update_rasterizer(struct si_context *sctx)
2785 {
2786 struct si_shader_selector *sel = sctx->shader.ps.cso;
2787 union si_shader_key *key = &sctx->shader.ps.key;
2788 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2789
2790 if (!sel)
2791 return;
2792
2793 bool old_flatshade_colors = key->ps.part.prolog.flatshade_colors;
2794 bool old_clamp_color = key->ps.part.epilog.clamp_color;
2795
2796 key->ps.part.prolog.flatshade_colors = rs->flatshade && sel->info.uses_interp_color;
2797 key->ps.part.epilog.clamp_color = rs->clamp_fragment_color;
2798
2799 if (key->ps.part.prolog.flatshade_colors != old_flatshade_colors ||
2800 key->ps.part.epilog.clamp_color != old_clamp_color)
2801 sctx->do_update_shaders = true;
2802 }
2803
si_ps_key_update_dsa(struct si_context * sctx)2804 void si_ps_key_update_dsa(struct si_context *sctx)
2805 {
2806 union si_shader_key *key = &sctx->shader.ps.key;
2807
2808 key->ps.part.epilog.alpha_func = sctx->queued.named.dsa->alpha_func;
2809 }
2810
si_ps_key_update_sample_shading(struct si_context * sctx)2811 void si_ps_key_update_sample_shading(struct si_context *sctx)
2812 {
2813 struct si_shader_selector *sel = sctx->shader.ps.cso;
2814 union si_shader_key *key = &sctx->shader.ps.key;
2815
2816 if (!sel)
2817 return;
2818
2819 if (sctx->ps_iter_samples > 1 && sel->info.reads_samplemask)
2820 key->ps.part.prolog.samplemask_log_ps_iter = util_logbase2(sctx->ps_iter_samples);
2821 else
2822 key->ps.part.prolog.samplemask_log_ps_iter = 0;
2823 }
2824
si_ps_key_update_framebuffer_rasterizer_sample_shading(struct si_context * sctx)2825 void si_ps_key_update_framebuffer_rasterizer_sample_shading(struct si_context *sctx)
2826 {
2827 struct si_shader_selector *sel = sctx->shader.ps.cso;
2828 union si_shader_key *key = &sctx->shader.ps.key;
2829 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2830
2831 if (!sel)
2832 return;
2833
2834 /* Old key data for comparison. */
2835 struct si_ps_prolog_bits old_prolog;
2836 memcpy(&old_prolog, &key->ps.part.prolog, sizeof(old_prolog));
2837 bool old_interpolate_at_sample_force_center = key->ps.mono.interpolate_at_sample_force_center;
2838
2839 bool uses_persp_center = sel->info.uses_persp_center ||
2840 (!rs->flatshade && sel->info.uses_persp_center_color);
2841 bool uses_persp_centroid = sel->info.uses_persp_centroid ||
2842 (!rs->flatshade && sel->info.uses_persp_centroid_color);
2843 bool uses_persp_sample = sel->info.uses_persp_sample ||
2844 (!rs->flatshade && sel->info.uses_persp_sample_color);
2845
2846 if (rs->force_persample_interp && rs->multisample_enable &&
2847 sctx->framebuffer.nr_samples > 1 && sctx->ps_iter_samples > 1) {
2848 key->ps.part.prolog.force_persp_sample_interp =
2849 uses_persp_center || uses_persp_centroid;
2850
2851 key->ps.part.prolog.force_linear_sample_interp =
2852 sel->info.uses_linear_center || sel->info.uses_linear_centroid;
2853
2854 key->ps.part.prolog.force_persp_center_interp = 0;
2855 key->ps.part.prolog.force_linear_center_interp = 0;
2856 key->ps.part.prolog.bc_optimize_for_persp = 0;
2857 key->ps.part.prolog.bc_optimize_for_linear = 0;
2858 key->ps.mono.interpolate_at_sample_force_center = 0;
2859 } else if (rs->multisample_enable && sctx->framebuffer.nr_samples > 1) {
2860 key->ps.part.prolog.force_persp_sample_interp = 0;
2861 key->ps.part.prolog.force_linear_sample_interp = 0;
2862 key->ps.part.prolog.force_persp_center_interp = 0;
2863 key->ps.part.prolog.force_linear_center_interp = 0;
2864 key->ps.part.prolog.bc_optimize_for_persp =
2865 uses_persp_center && uses_persp_centroid;
2866 key->ps.part.prolog.bc_optimize_for_linear =
2867 sel->info.uses_linear_center && sel->info.uses_linear_centroid;
2868 key->ps.mono.interpolate_at_sample_force_center = 0;
2869 } else {
2870 key->ps.part.prolog.force_persp_sample_interp = 0;
2871 key->ps.part.prolog.force_linear_sample_interp = 0;
2872
2873 /* Make sure SPI doesn't compute more than 1 pair
2874 * of (i,j), which is the optimization here. */
2875 key->ps.part.prolog.force_persp_center_interp = uses_persp_center +
2876 uses_persp_centroid +
2877 uses_persp_sample > 1;
2878
2879 key->ps.part.prolog.force_linear_center_interp = sel->info.uses_linear_center +
2880 sel->info.uses_linear_centroid +
2881 sel->info.uses_linear_sample > 1;
2882 key->ps.part.prolog.bc_optimize_for_persp = 0;
2883 key->ps.part.prolog.bc_optimize_for_linear = 0;
2884 key->ps.mono.interpolate_at_sample_force_center = sel->info.uses_interp_at_sample;
2885 }
2886
2887 /* Update shaders only if the key changed. */
2888 if (memcmp(&key->ps.part.prolog, &old_prolog, sizeof(old_prolog)) ||
2889 key->ps.mono.interpolate_at_sample_force_center != old_interpolate_at_sample_force_center)
2890 sctx->do_update_shaders = true;
2891 }
2892
2893 /* Compute the key for the hw shader variant */
si_shader_selector_key(struct pipe_context * ctx,struct si_shader_selector * sel,union si_shader_key * key)2894 static inline void si_shader_selector_key(struct pipe_context *ctx, struct si_shader_selector *sel,
2895 union si_shader_key *key)
2896 {
2897 struct si_context *sctx = (struct si_context *)ctx;
2898
2899 switch (sel->stage) {
2900 case MESA_SHADER_VERTEX:
2901 if (!sctx->shader.tes.cso && !sctx->shader.gs.cso)
2902 si_get_vs_key_outputs(sctx, sel, key);
2903 else
2904 si_clear_vs_key_outputs(sctx, sel, key);
2905 break;
2906 case MESA_SHADER_TESS_CTRL:
2907 if (sctx->gfx_level >= GFX9) {
2908 si_get_vs_key_inputs(sctx, key);
2909 key->ge.part.tcs.ls = sctx->shader.vs.cso;
2910 }
2911 break;
2912 case MESA_SHADER_TESS_EVAL:
2913 if (!sctx->shader.gs.cso)
2914 si_get_vs_key_outputs(sctx, sel, key);
2915 else
2916 si_clear_vs_key_outputs(sctx, sel, key);
2917 break;
2918 case MESA_SHADER_GEOMETRY:
2919 if (sctx->gfx_level >= GFX9) {
2920 if (sctx->shader.tes.cso) {
2921 si_clear_vs_key_inputs(key);
2922 key->ge.part.gs.es = sctx->shader.tes.cso;
2923 } else {
2924 si_get_vs_key_inputs(sctx, key);
2925 key->ge.part.gs.es = sctx->shader.vs.cso;
2926 }
2927
2928 /* Only NGG can eliminate GS outputs, because the code is shared with VS. */
2929 if (sctx->ngg)
2930 si_get_vs_key_outputs(sctx, sel, key);
2931 else
2932 si_clear_vs_key_outputs(sctx, sel, key);
2933 }
2934 break;
2935 case MESA_SHADER_FRAGMENT:
2936 break;
2937 default:
2938 assert(0);
2939 }
2940 }
2941
si_build_shader_variant(struct si_shader * shader,int thread_index,bool low_priority)2942 static void si_build_shader_variant(struct si_shader *shader, int thread_index, bool low_priority)
2943 {
2944 struct si_shader_selector *sel = shader->selector;
2945 struct si_screen *sscreen = sel->screen;
2946 struct ac_llvm_compiler **compiler;
2947 struct util_debug_callback *debug = &shader->compiler_ctx_state.debug;
2948
2949 if (thread_index >= 0) {
2950 if (low_priority) {
2951 assert(thread_index < (int)ARRAY_SIZE(sscreen->compiler_lowp));
2952 compiler = &sscreen->compiler_lowp[thread_index];
2953 } else {
2954 assert(thread_index < (int)ARRAY_SIZE(sscreen->compiler));
2955 compiler = &sscreen->compiler[thread_index];
2956 }
2957 if (!debug->async)
2958 debug = NULL;
2959 } else {
2960 assert(!low_priority);
2961 compiler = &shader->compiler_ctx_state.compiler;
2962 }
2963
2964 if (!sel->info.base.use_aco_amd && !*compiler)
2965 *compiler = si_create_llvm_compiler(sscreen);
2966
2967 if (unlikely(!si_create_shader_variant(sscreen, *compiler, shader, debug))) {
2968 PRINT_ERR("Failed to build shader variant (type=%u)\n", sel->stage);
2969 shader->compilation_failed = true;
2970 return;
2971 }
2972
2973 if (shader->compiler_ctx_state.is_debug_context) {
2974 FILE *f = open_memstream(&shader->shader_log, &shader->shader_log_size);
2975 if (f) {
2976 si_shader_dump(sscreen, shader, NULL, f, false);
2977 fclose(f);
2978 }
2979 }
2980
2981 si_shader_init_pm4_state(sscreen, shader);
2982 }
2983
si_build_shader_variant_low_priority(void * job,void * gdata,int thread_index)2984 static void si_build_shader_variant_low_priority(void *job, void *gdata, int thread_index)
2985 {
2986 struct si_shader *shader = (struct si_shader *)job;
2987
2988 assert(thread_index >= 0);
2989
2990 si_build_shader_variant(shader, thread_index, true);
2991 }
2992
2993 /* This should be const, but C++ doesn't allow implicit zero-initialization with const. */
2994 static union si_shader_key zeroed;
2995
si_check_missing_main_part(struct si_screen * sscreen,struct si_shader_selector * sel,struct si_compiler_ctx_state * compiler_state,const union si_shader_key * key,unsigned wave_size)2996 static bool si_check_missing_main_part(struct si_screen *sscreen, struct si_shader_selector *sel,
2997 struct si_compiler_ctx_state *compiler_state,
2998 const union si_shader_key *key, unsigned wave_size)
2999 {
3000 struct si_shader **mainp = si_get_main_shader_part(sel, key, wave_size);
3001
3002 if (!*mainp) {
3003 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
3004
3005 if (!main_part)
3006 return false;
3007
3008 /* We can leave the fence as permanently signaled because the
3009 * main part becomes visible globally only after it has been
3010 * compiled. */
3011 util_queue_fence_init(&main_part->ready);
3012
3013 main_part->selector = sel;
3014 if (sel->stage <= MESA_SHADER_GEOMETRY) {
3015 main_part->key.ge.as_es = key->ge.as_es;
3016 main_part->key.ge.as_ls = key->ge.as_ls;
3017 main_part->key.ge.as_ngg = key->ge.as_ngg;
3018 }
3019 main_part->is_monolithic = false;
3020 main_part->wave_size = wave_size;
3021
3022 if (!si_compile_shader(sscreen, compiler_state->compiler, main_part,
3023 &compiler_state->debug)) {
3024 FREE(main_part);
3025 return false;
3026 }
3027 *mainp = main_part;
3028 }
3029 return true;
3030 }
3031
3032 /* A helper to copy *key to *local_key and return local_key. */
3033 template<typename SHADER_KEY_TYPE>
3034 static ALWAYS_INLINE const SHADER_KEY_TYPE *
use_local_key_copy(const SHADER_KEY_TYPE * key,SHADER_KEY_TYPE * local_key,unsigned key_size)3035 use_local_key_copy(const SHADER_KEY_TYPE *key, SHADER_KEY_TYPE *local_key, unsigned key_size)
3036 {
3037 if (key != local_key)
3038 memcpy(local_key, key, key_size);
3039
3040 return local_key;
3041 }
3042
3043 #define NO_INLINE_UNIFORMS false
3044
3045 /**
3046 * Select a shader variant according to the shader key.
3047 *
3048 * This uses a C++ template to compute the optimal memcmp size at compile time, which is important
3049 * for getting inlined memcmp. The memcmp size depends on the shader key type and whether inlined
3050 * uniforms are enabled.
3051 */
3052 template<bool INLINE_UNIFORMS = true, typename SHADER_KEY_TYPE>
si_shader_select_with_key(struct si_context * sctx,struct si_shader_ctx_state * state,const SHADER_KEY_TYPE * key)3053 static int si_shader_select_with_key(struct si_context *sctx, struct si_shader_ctx_state *state,
3054 const SHADER_KEY_TYPE *key)
3055 {
3056 struct si_screen *sscreen = sctx->screen;
3057 struct si_shader_selector *sel = state->cso;
3058 struct si_shader_selector *previous_stage_sel = NULL;
3059 struct si_shader *current = state->current;
3060 struct si_shader *shader = NULL;
3061 const SHADER_KEY_TYPE *zeroed_key = (SHADER_KEY_TYPE*)&zeroed;
3062
3063 /* "opt" must be the last field and "inlined_uniform_values" must be the last field inside opt.
3064 * If there is padding, insert the padding manually before opt or inside opt.
3065 */
3066 STATIC_ASSERT(offsetof(SHADER_KEY_TYPE, opt) + sizeof(key->opt) == sizeof(*key));
3067 STATIC_ASSERT(offsetof(SHADER_KEY_TYPE, opt.inlined_uniform_values) +
3068 sizeof(key->opt.inlined_uniform_values) == sizeof(*key));
3069
3070 const unsigned key_size_no_uniforms = sizeof(*key) - sizeof(key->opt.inlined_uniform_values);
3071 /* Don't compare inlined_uniform_values if uniform inlining is disabled. */
3072 const unsigned key_size = INLINE_UNIFORMS ? sizeof(*key) : key_size_no_uniforms;
3073 const unsigned key_opt_size =
3074 INLINE_UNIFORMS ? sizeof(key->opt) :
3075 sizeof(key->opt) - sizeof(key->opt.inlined_uniform_values);
3076
3077 /* si_shader_select_with_key must not modify 'key' because it would affect future shaders.
3078 * If we need to modify it for this specific shader (eg: to disable optimizations), we
3079 * use a copy.
3080 */
3081 SHADER_KEY_TYPE local_key;
3082
3083 if (unlikely(sscreen->debug_flags & DBG(NO_OPT_VARIANT))) {
3084 /* Disable shader variant optimizations. */
3085 key = use_local_key_copy<SHADER_KEY_TYPE>(key, &local_key, key_size);
3086 memset(&local_key.opt, 0, key_opt_size);
3087 }
3088
3089 again:
3090 /* Check if we don't need to change anything.
3091 * This path is also used for most shaders that don't need multiple
3092 * variants, it will cost just a computation of the key and this
3093 * test. */
3094 if (likely(current && memcmp(¤t->key, key, key_size) == 0)) {
3095 if (unlikely(!util_queue_fence_is_signalled(¤t->ready))) {
3096 if (current->is_optimized) {
3097 key = use_local_key_copy(key, &local_key, key_size);
3098 memset(&local_key.opt, 0, key_opt_size);
3099 goto current_not_ready;
3100 }
3101
3102 util_queue_fence_wait(¤t->ready);
3103 }
3104
3105 return current->compilation_failed ? -1 : 0;
3106 }
3107 current_not_ready:
3108
3109 /* This must be done before the mutex is locked, because async GS
3110 * compilation calls this function too, and therefore must enter
3111 * the mutex first.
3112 */
3113 util_queue_fence_wait(&sel->ready);
3114
3115 simple_mtx_lock(&sel->mutex);
3116
3117 int variant_count = 0;
3118 const int max_inline_uniforms_variants = 5;
3119
3120 /* Find the shader variant. */
3121 const unsigned cnt = sel->variants_count;
3122 for (unsigned i = 0; i < cnt; i++) {
3123 const SHADER_KEY_TYPE *iter_key = (const SHADER_KEY_TYPE *)&sel->keys[i];
3124
3125 if (memcmp(iter_key, key, key_size_no_uniforms) == 0) {
3126 struct si_shader *iter = sel->variants[i];
3127
3128 /* Check the inlined uniform values separately, and count
3129 * the number of variants based on them.
3130 */
3131 if (key->opt.inline_uniforms &&
3132 memcmp(iter_key->opt.inlined_uniform_values,
3133 key->opt.inlined_uniform_values,
3134 MAX_INLINABLE_UNIFORMS * 4) != 0) {
3135 if (variant_count++ > max_inline_uniforms_variants) {
3136 key = use_local_key_copy(key, &local_key, key_size);
3137 /* Too many variants. Disable inlining for this shader. */
3138 local_key.opt.inline_uniforms = 0;
3139 memset(local_key.opt.inlined_uniform_values, 0, MAX_INLINABLE_UNIFORMS * 4);
3140 simple_mtx_unlock(&sel->mutex);
3141 goto again;
3142 }
3143 continue;
3144 }
3145
3146 simple_mtx_unlock(&sel->mutex);
3147
3148 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
3149 /* If it's an optimized shader and its compilation has
3150 * been started but isn't done, use the unoptimized
3151 * shader so as not to cause a stall due to compilation.
3152 */
3153 if (iter->is_optimized) {
3154 key = use_local_key_copy(key, &local_key, key_size);
3155 memset(&local_key.opt, 0, key_opt_size);
3156 goto again;
3157 }
3158
3159 util_queue_fence_wait(&iter->ready);
3160 }
3161
3162 if (iter->compilation_failed) {
3163 return -1; /* skip the draw call */
3164 }
3165
3166 state->current = sel->variants[i];
3167 return 0;
3168 }
3169 }
3170
3171 /* Build a new shader. */
3172 shader = CALLOC_STRUCT(si_shader);
3173 if (!shader) {
3174 simple_mtx_unlock(&sel->mutex);
3175 return -ENOMEM;
3176 }
3177
3178 util_queue_fence_init(&shader->ready);
3179
3180 if (!sel->info.base.use_aco_amd && !sctx->compiler)
3181 sctx->compiler = si_create_llvm_compiler(sctx->screen);
3182
3183 shader->selector = sel;
3184 *((SHADER_KEY_TYPE*)&shader->key) = *key;
3185 shader->wave_size = si_determine_wave_size(sscreen, shader);
3186 shader->compiler_ctx_state.compiler = sctx->compiler;
3187 shader->compiler_ctx_state.debug = sctx->debug;
3188 shader->compiler_ctx_state.is_debug_context = sctx->is_debug;
3189
3190 /* If this is a merged shader, get the first shader's selector. */
3191 if (sscreen->info.gfx_level >= GFX9) {
3192 if (sel->stage == MESA_SHADER_TESS_CTRL)
3193 previous_stage_sel = ((struct si_shader_key_ge*)key)->part.tcs.ls;
3194 else if (sel->stage == MESA_SHADER_GEOMETRY)
3195 previous_stage_sel = ((struct si_shader_key_ge*)key)->part.gs.es;
3196
3197 /* We need to wait for the previous shader. */
3198 if (previous_stage_sel)
3199 util_queue_fence_wait(&previous_stage_sel->ready);
3200 }
3201
3202 bool is_pure_monolithic =
3203 sscreen->use_monolithic_shaders || memcmp(&key->mono, &zeroed_key->mono, sizeof(key->mono)) != 0;
3204
3205 /* Compile the main shader part if it doesn't exist. This can happen
3206 * if the initial guess was wrong.
3207 */
3208 if (!is_pure_monolithic) {
3209 bool ok = true;
3210
3211 /* Make sure the main shader part is present. This is needed
3212 * for shaders that can be compiled as VS, LS, or ES, and only
3213 * one of them is compiled at creation.
3214 *
3215 * It is also needed for GS, which can be compiled as non-NGG
3216 * and NGG.
3217 *
3218 * For merged shaders, check that the starting shader's main
3219 * part is present.
3220 */
3221 if (previous_stage_sel) {
3222 union si_shader_key shader1_key = zeroed;
3223
3224 if (sel->stage == MESA_SHADER_TESS_CTRL) {
3225 shader1_key.ge.as_ls = 1;
3226 } else if (sel->stage == MESA_SHADER_GEOMETRY) {
3227 shader1_key.ge.as_es = 1;
3228 shader1_key.ge.as_ngg = ((struct si_shader_key_ge*)key)->as_ngg; /* for Wave32 vs Wave64 */
3229 } else {
3230 assert(0);
3231 }
3232
3233 simple_mtx_lock(&previous_stage_sel->mutex);
3234 ok = si_check_missing_main_part(sscreen, previous_stage_sel, &shader->compiler_ctx_state,
3235 &shader1_key, shader->wave_size);
3236 simple_mtx_unlock(&previous_stage_sel->mutex);
3237 }
3238
3239 if (ok) {
3240 ok = si_check_missing_main_part(sscreen, sel, &shader->compiler_ctx_state,
3241 (union si_shader_key*)key, shader->wave_size);
3242 }
3243
3244 if (!ok) {
3245 FREE(shader);
3246 simple_mtx_unlock(&sel->mutex);
3247 return -ENOMEM; /* skip the draw call */
3248 }
3249 }
3250
3251 if (sel->variants_count == sel->variants_max_count) {
3252 sel->variants_max_count += 2;
3253 sel->variants = (struct si_shader**)
3254 realloc(sel->variants, sel->variants_max_count * sizeof(struct si_shader*));
3255 sel->keys = (union si_shader_key*)
3256 realloc(sel->keys, sel->variants_max_count * sizeof(union si_shader_key));
3257 }
3258
3259 /* Keep the reference to the 1st shader of merged shaders, so that
3260 * Gallium can't destroy it before we destroy the 2nd shader.
3261 *
3262 * Set sctx = NULL, because it's unused if we're not releasing
3263 * the shader, and we don't have any sctx here.
3264 */
3265 si_shader_selector_reference(NULL, &shader->previous_stage_sel, previous_stage_sel);
3266
3267 /* Monolithic-only shaders don't make a distinction between optimized
3268 * and unoptimized. */
3269 shader->is_monolithic =
3270 is_pure_monolithic || memcmp(&key->opt, &zeroed_key->opt, key_opt_size) != 0;
3271
3272 shader->is_optimized = !is_pure_monolithic &&
3273 memcmp(&key->opt, &zeroed_key->opt, key_opt_size) != 0;
3274
3275 /* If it's an optimized shader, compile it asynchronously. */
3276 if (shader->is_optimized) {
3277 /* Compile it asynchronously. */
3278 util_queue_add_job(&sscreen->shader_compiler_queue_opt_variants, shader, &shader->ready,
3279 si_build_shader_variant_low_priority, NULL, 0);
3280
3281 /* Add only after the ready fence was reset, to guard against a
3282 * race with si_bind_XX_shader. */
3283 sel->variants[sel->variants_count] = shader;
3284 sel->keys[sel->variants_count] = shader->key;
3285 sel->variants_count++;
3286
3287 /* Use the default (unoptimized) shader for now. */
3288 key = use_local_key_copy(key, &local_key, key_size);
3289 memset(&local_key.opt, 0, key_opt_size);
3290 simple_mtx_unlock(&sel->mutex);
3291
3292 if (sscreen->options.sync_compile)
3293 util_queue_fence_wait(&shader->ready);
3294
3295 goto again;
3296 }
3297
3298 /* Reset the fence before adding to the variant list. */
3299 util_queue_fence_reset(&shader->ready);
3300
3301 sel->variants[sel->variants_count] = shader;
3302 sel->keys[sel->variants_count] = shader->key;
3303 sel->variants_count++;
3304
3305 simple_mtx_unlock(&sel->mutex);
3306
3307 assert(!shader->is_optimized);
3308 si_build_shader_variant(shader, -1, false);
3309
3310 util_queue_fence_signal(&shader->ready);
3311
3312 if (!shader->compilation_failed)
3313 state->current = shader;
3314
3315 return shader->compilation_failed ? -1 : 0;
3316 }
3317
si_shader_select(struct pipe_context * ctx,struct si_shader_ctx_state * state)3318 int si_shader_select(struct pipe_context *ctx, struct si_shader_ctx_state *state)
3319 {
3320 struct si_context *sctx = (struct si_context *)ctx;
3321
3322 si_shader_selector_key(ctx, state->cso, &state->key);
3323
3324 if (state->cso->stage == MESA_SHADER_FRAGMENT) {
3325 if (state->key.ps.opt.inline_uniforms)
3326 return si_shader_select_with_key(sctx, state, &state->key.ps);
3327 else
3328 return si_shader_select_with_key<NO_INLINE_UNIFORMS>(sctx, state, &state->key.ps);
3329 } else {
3330 if (state->key.ge.opt.inline_uniforms) {
3331 return si_shader_select_with_key(sctx, state, &state->key.ge);
3332 } else {
3333 return si_shader_select_with_key<NO_INLINE_UNIFORMS>(sctx, state, &state->key.ge);
3334 }
3335 }
3336 }
3337
si_parse_next_shader_property(const struct si_shader_info * info,union si_shader_key * key)3338 static void si_parse_next_shader_property(const struct si_shader_info *info,
3339 union si_shader_key *key)
3340 {
3341 gl_shader_stage next_shader = info->base.next_stage;
3342
3343 switch (info->base.stage) {
3344 case MESA_SHADER_VERTEX:
3345 switch (next_shader) {
3346 case MESA_SHADER_GEOMETRY:
3347 key->ge.as_es = 1;
3348 break;
3349 case MESA_SHADER_TESS_CTRL:
3350 case MESA_SHADER_TESS_EVAL:
3351 key->ge.as_ls = 1;
3352 break;
3353 default:
3354 /* If POSITION isn't written, it can only be a HW VS
3355 * if streamout is used. If streamout isn't used,
3356 * assume that it's a HW LS. (the next shader is TCS)
3357 * This heuristic is needed for separate shader objects.
3358 */
3359 if (!info->writes_position && !info->enabled_streamout_buffer_mask)
3360 key->ge.as_ls = 1;
3361 }
3362 break;
3363
3364 case MESA_SHADER_TESS_EVAL:
3365 if (next_shader == MESA_SHADER_GEOMETRY || !info->writes_position)
3366 key->ge.as_es = 1;
3367 break;
3368
3369 default:;
3370 }
3371 }
3372
3373 /**
3374 * Compile the main shader part or the monolithic shader as part of
3375 * si_shader_selector initialization. Since it can be done asynchronously,
3376 * there is no way to report compile failures to applications.
3377 */
si_init_shader_selector_async(void * job,void * gdata,int thread_index)3378 static void si_init_shader_selector_async(void *job, void *gdata, int thread_index)
3379 {
3380 struct si_shader_selector *sel = (struct si_shader_selector *)job;
3381 struct si_screen *sscreen = sel->screen;
3382 struct ac_llvm_compiler **compiler;
3383 struct util_debug_callback *debug = &sel->compiler_ctx_state.debug;
3384
3385 assert(!debug->debug_message || debug->async);
3386 assert(thread_index >= 0);
3387 assert(thread_index < (int)ARRAY_SIZE(sscreen->compiler));
3388 compiler = &sscreen->compiler[thread_index];
3389
3390 if (!sel->info.base.use_aco_amd && !*compiler)
3391 *compiler = si_create_llvm_compiler(sscreen);
3392
3393 /* Serialize NIR to save memory. Monolithic shader variants
3394 * have to deserialize NIR before compilation.
3395 */
3396 if (sel->nir) {
3397 struct blob blob;
3398 size_t size;
3399
3400 blob_init(&blob);
3401 /* true = remove optional debugging data to increase
3402 * the likehood of getting more shader cache hits.
3403 * It also drops variable names, so we'll save more memory.
3404 * If NIR debug prints are used we don't strip to get more
3405 * useful logs.
3406 */
3407 nir_serialize(&blob, sel->nir, NIR_DEBUG(PRINT) == 0);
3408 blob_finish_get_buffer(&blob, &sel->nir_binary, &size);
3409 sel->nir_size = size;
3410 }
3411
3412 /* Compile the main shader part for use with a prolog and/or epilog.
3413 * If this fails, the driver will try to compile a monolithic shader
3414 * on demand.
3415 */
3416 if (!sscreen->use_monolithic_shaders) {
3417 struct si_shader *shader = CALLOC_STRUCT(si_shader);
3418 unsigned char ir_sha1_cache_key[20];
3419
3420 if (!shader) {
3421 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
3422 return;
3423 }
3424
3425 /* We can leave the fence signaled because use of the default
3426 * main part is guarded by the selector's ready fence. */
3427 util_queue_fence_init(&shader->ready);
3428
3429 shader->selector = sel;
3430 shader->is_monolithic = false;
3431 si_parse_next_shader_property(&sel->info, &shader->key);
3432
3433 if (sel->stage <= MESA_SHADER_GEOMETRY &&
3434 sscreen->use_ngg && (!sel->info.enabled_streamout_buffer_mask ||
3435 sscreen->info.gfx_level >= GFX11) &&
3436 ((sel->stage == MESA_SHADER_VERTEX && !shader->key.ge.as_ls) ||
3437 sel->stage == MESA_SHADER_TESS_EVAL || sel->stage == MESA_SHADER_GEOMETRY))
3438 shader->key.ge.as_ngg = 1;
3439
3440 shader->wave_size = si_determine_wave_size(sscreen, shader);
3441
3442 if (sel->nir) {
3443 if (sel->stage <= MESA_SHADER_GEOMETRY) {
3444 si_get_ir_cache_key(sel, shader->key.ge.as_ngg, shader->key.ge.as_es,
3445 shader->wave_size, ir_sha1_cache_key);
3446 } else {
3447 si_get_ir_cache_key(sel, false, false, shader->wave_size, ir_sha1_cache_key);
3448 }
3449 }
3450
3451 /* Try to load the shader from the shader cache. */
3452 simple_mtx_lock(&sscreen->shader_cache_mutex);
3453
3454 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
3455 simple_mtx_unlock(&sscreen->shader_cache_mutex);
3456 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
3457 } else {
3458 simple_mtx_unlock(&sscreen->shader_cache_mutex);
3459
3460 /* Compile the shader if it hasn't been loaded from the cache. */
3461 if (!si_compile_shader(sscreen, *compiler, shader, debug)) {
3462 fprintf(stderr,
3463 "radeonsi: can't compile a main shader part (type: %s, name: %s).\n"
3464 "This is probably a driver bug, please report "
3465 "it to https://gitlab.freedesktop.org/mesa/mesa/-/issues.\n",
3466 gl_shader_stage_name(shader->selector->stage),
3467 shader->selector->info.base.name);
3468 FREE(shader);
3469 return;
3470 }
3471
3472 simple_mtx_lock(&sscreen->shader_cache_mutex);
3473 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, true);
3474 simple_mtx_unlock(&sscreen->shader_cache_mutex);
3475 }
3476
3477 *si_get_main_shader_part(sel, &shader->key, shader->wave_size) = shader;
3478
3479 /* Unset "outputs_written" flags for outputs converted to
3480 * DEFAULT_VAL, so that later inter-shader optimizations don't
3481 * try to eliminate outputs that don't exist in the final
3482 * shader.
3483 *
3484 * This is only done if non-monolithic shaders are enabled.
3485 */
3486 if ((sel->stage == MESA_SHADER_VERTEX ||
3487 sel->stage == MESA_SHADER_TESS_EVAL ||
3488 sel->stage == MESA_SHADER_GEOMETRY) &&
3489 !shader->key.ge.as_ls && !shader->key.ge.as_es) {
3490 unsigned i;
3491
3492 for (i = 0; i < sel->info.num_outputs; i++) {
3493 unsigned semantic = sel->info.output_semantic[i];
3494 unsigned ps_input_cntl = shader->info.vs_output_ps_input_cntl[semantic];
3495
3496 /* OFFSET=0x20 means DEFAULT_VAL, which means VS doesn't export it. */
3497 if (G_028644_OFFSET(ps_input_cntl) != 0x20)
3498 continue;
3499
3500 unsigned id;
3501
3502 /* Remove the output from the mask. */
3503 if ((semantic <= VARYING_SLOT_VAR31 || semantic >= VARYING_SLOT_VAR0_16BIT) &&
3504 semantic != VARYING_SLOT_POS &&
3505 semantic != VARYING_SLOT_PSIZ &&
3506 semantic != VARYING_SLOT_CLIP_VERTEX &&
3507 semantic != VARYING_SLOT_EDGE &&
3508 semantic != VARYING_SLOT_LAYER) {
3509 id = si_shader_io_get_unique_index(semantic);
3510 sel->info.outputs_written_before_ps &= ~(1ull << id);
3511 }
3512 }
3513 }
3514 }
3515
3516 /* Free NIR. We only keep serialized NIR after this point. */
3517 if (sel->nir) {
3518 ralloc_free(sel->nir);
3519 sel->nir = NULL;
3520 }
3521 }
3522
si_schedule_initial_compile(struct si_context * sctx,gl_shader_stage stage,struct util_queue_fence * ready_fence,struct si_compiler_ctx_state * compiler_ctx_state,void * job,util_queue_execute_func execute)3523 void si_schedule_initial_compile(struct si_context *sctx, gl_shader_stage stage,
3524 struct util_queue_fence *ready_fence,
3525 struct si_compiler_ctx_state *compiler_ctx_state, void *job,
3526 util_queue_execute_func execute)
3527 {
3528 util_queue_fence_init(ready_fence);
3529
3530 struct util_async_debug_callback async_debug;
3531 bool debug = (sctx->debug.debug_message && !sctx->debug.async) || sctx->is_debug ||
3532 si_can_dump_shader(sctx->screen, stage, SI_DUMP_ALWAYS);
3533
3534 if (debug) {
3535 u_async_debug_init(&async_debug);
3536 compiler_ctx_state->debug = async_debug.base;
3537 }
3538
3539 util_queue_add_job(&sctx->screen->shader_compiler_queue, job, ready_fence, execute, NULL, 0);
3540
3541 if (debug) {
3542 util_queue_fence_wait(ready_fence);
3543 u_async_debug_drain(&async_debug, &sctx->debug);
3544 u_async_debug_cleanup(&async_debug);
3545 }
3546
3547 if (sctx->screen->options.sync_compile)
3548 util_queue_fence_wait(ready_fence);
3549 }
3550
3551 /* Return descriptor slot usage masks from the given shader info. */
si_get_active_slot_masks(struct si_screen * sscreen,const struct si_shader_info * info,uint64_t * const_and_shader_buffers,uint64_t * samplers_and_images)3552 void si_get_active_slot_masks(struct si_screen *sscreen, const struct si_shader_info *info,
3553 uint64_t *const_and_shader_buffers, uint64_t *samplers_and_images)
3554 {
3555 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
3556
3557 num_shaderbufs = info->base.num_ssbos;
3558 num_constbufs = info->base.num_ubos;
3559 /* two 8-byte images share one 16-byte slot */
3560 num_images = align(info->base.num_images, 2);
3561 num_msaa_images = align(BITSET_LAST_BIT(info->base.msaa_images), 2);
3562 num_samplers = BITSET_LAST_BIT(info->base.textures_used);
3563
3564 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
3565 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
3566 *const_and_shader_buffers = u_bit_consecutive64(start, num_shaderbufs + num_constbufs);
3567
3568 /* The layout is:
3569 * - fmask[last] ... fmask[0] go to [15-last .. 15]
3570 * - image[last] ... image[0] go to [31-last .. 31]
3571 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
3572 *
3573 * FMASKs for images are placed separately, because MSAA images are rare,
3574 * and so we can benefit from a better cache hit rate if we keep image
3575 * descriptors together.
3576 */
3577 if (sscreen->info.gfx_level < GFX11 && num_msaa_images)
3578 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */
3579
3580 start = si_get_image_slot(num_images - 1) / 2;
3581 *samplers_and_images = u_bit_consecutive64(start, num_images / 2 + num_samplers);
3582 }
3583
si_create_shader_selector(struct pipe_context * ctx,const struct pipe_shader_state * state)3584 static void *si_create_shader_selector(struct pipe_context *ctx,
3585 const struct pipe_shader_state *state)
3586 {
3587 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
3588 struct si_context *sctx = (struct si_context *)ctx;
3589 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
3590
3591 if (!sel)
3592 return NULL;
3593
3594 sel->screen = sscreen;
3595 sel->compiler_ctx_state.debug = sctx->debug;
3596 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
3597 sel->variants_max_count = 2;
3598 sel->keys = (union si_shader_key *)
3599 realloc(NULL, sel->variants_max_count * sizeof(union si_shader_key));
3600 sel->variants = (struct si_shader **)
3601 realloc(NULL, sel->variants_max_count * sizeof(struct si_shader *));
3602
3603 if (state->type == PIPE_SHADER_IR_TGSI) {
3604 sel->nir = tgsi_to_nir(state->tokens, ctx->screen, true);
3605 } else {
3606 assert(state->type == PIPE_SHADER_IR_NIR);
3607 sel->nir = (nir_shader*)state->ir.nir;
3608 }
3609
3610 si_nir_scan_shader(sscreen, sel->nir, &sel->info);
3611
3612 sel->stage = sel->nir->info.stage;
3613 sel->const_and_shader_buf_descriptors_index =
3614 si_const_and_shader_buffer_descriptors_idx(sel->stage);
3615 sel->sampler_and_images_descriptors_index =
3616 si_sampler_and_image_descriptors_idx(sel->stage);
3617
3618 if (si_can_dump_shader(sscreen, sel->stage, SI_DUMP_INIT_NIR))
3619 nir_print_shader(sel->nir, stderr);
3620
3621 p_atomic_inc(&sscreen->num_shaders_created);
3622 si_get_active_slot_masks(sscreen, &sel->info, &sel->active_const_and_shader_buffers,
3623 &sel->active_samplers_and_images);
3624
3625 switch (sel->stage) {
3626 case MESA_SHADER_GEOMETRY:
3627 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
3628 sel->rast_prim = (enum mesa_prim)sel->nir->info.gs.output_primitive;
3629 if (util_rast_prim_is_triangles(sel->rast_prim))
3630 sel->rast_prim = MESA_PRIM_TRIANGLES;
3631
3632 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tessellation so
3633 * we can't split workgroups. Disable ngg if any of the following conditions is true:
3634 * - num_invocations * gs.vertices_out > 256
3635 * - LDS usage is too high
3636 */
3637 sel->tess_turns_off_ngg = sscreen->info.gfx_level >= GFX10 &&
3638 sscreen->info.gfx_level <= GFX10_3 &&
3639 (sel->nir->info.gs.invocations * sel->nir->info.gs.vertices_out > 256 ||
3640 sel->nir->info.gs.invocations * sel->nir->info.gs.vertices_out *
3641 (sel->info.num_outputs * 4 + 1) > 6500 /* max dw per GS primitive */);
3642 break;
3643
3644 case MESA_SHADER_VERTEX:
3645 case MESA_SHADER_TESS_EVAL:
3646 if (sel->stage == MESA_SHADER_TESS_EVAL) {
3647 if (sel->nir->info.tess.point_mode)
3648 sel->rast_prim = MESA_PRIM_POINTS;
3649 else if (sel->nir->info.tess._primitive_mode == TESS_PRIMITIVE_ISOLINES)
3650 sel->rast_prim = MESA_PRIM_LINE_STRIP;
3651 else
3652 sel->rast_prim = MESA_PRIM_TRIANGLES;
3653 } else {
3654 sel->rast_prim = MESA_PRIM_TRIANGLES;
3655 }
3656 break;
3657 default:;
3658 }
3659
3660 bool ngg_culling_allowed =
3661 sscreen->info.gfx_level >= GFX10 &&
3662 sscreen->use_ngg_culling &&
3663 sel->info.writes_position &&
3664 !sel->info.writes_viewport_index && /* cull only against viewport 0 */
3665 !sel->nir->info.writes_memory &&
3666 /* NGG GS supports culling with streamout because it culls after streamout. */
3667 (sel->stage == MESA_SHADER_GEOMETRY || !sel->info.enabled_streamout_buffer_mask) &&
3668 (sel->stage != MESA_SHADER_GEOMETRY || sel->info.num_stream_output_components[0]) &&
3669 (sel->stage != MESA_SHADER_VERTEX ||
3670 (!sel->nir->info.vs.blit_sgprs_amd &&
3671 !sel->nir->info.vs.window_space_position));
3672
3673 sel->ngg_cull_vert_threshold = UINT_MAX; /* disabled (changed below) */
3674
3675 if (ngg_culling_allowed) {
3676 if (sel->stage == MESA_SHADER_VERTEX) {
3677 if (sscreen->debug_flags & DBG(ALWAYS_NGG_CULLING_ALL))
3678 sel->ngg_cull_vert_threshold = 0; /* always enabled */
3679 else
3680 sel->ngg_cull_vert_threshold = 128;
3681 } else if (sel->stage == MESA_SHADER_TESS_EVAL ||
3682 sel->stage == MESA_SHADER_GEOMETRY) {
3683 if (sel->rast_prim != MESA_PRIM_POINTS)
3684 sel->ngg_cull_vert_threshold = 0; /* always enabled */
3685 }
3686 }
3687
3688 (void)simple_mtx_init(&sel->mutex, mtx_plain);
3689
3690 si_schedule_initial_compile(sctx, sel->stage, &sel->ready, &sel->compiler_ctx_state,
3691 sel, si_init_shader_selector_async);
3692 return sel;
3693 }
3694
si_create_shader(struct pipe_context * ctx,const struct pipe_shader_state * state)3695 static void *si_create_shader(struct pipe_context *ctx, const struct pipe_shader_state *state)
3696 {
3697 struct si_context *sctx = (struct si_context *)ctx;
3698 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
3699 bool cache_hit;
3700 struct si_shader_selector *sel = (struct si_shader_selector *)util_live_shader_cache_get(
3701 ctx, &sscreen->live_shader_cache, state, &cache_hit);
3702
3703 if (sel && cache_hit && sctx->debug.debug_message) {
3704 for (unsigned i = 0; i < 2; i++) {
3705 if (sel->main_shader_part[i])
3706 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part[i], &sctx->debug);
3707 if (sel->main_shader_part_ls[i])
3708 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ls[i], &sctx->debug);
3709 if (sel->main_shader_part_ngg[i])
3710 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ngg[i], &sctx->debug);
3711 if (sel->main_shader_part_ngg_es[i])
3712 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ngg_es[i], &sctx->debug);
3713 }
3714
3715 if (sel->main_shader_part_es)
3716 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_es, &sctx->debug);
3717 }
3718 return sel;
3719 }
3720
si_update_streamout_state(struct si_context * sctx)3721 static void si_update_streamout_state(struct si_context *sctx)
3722 {
3723 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
3724
3725 if (!shader_with_so)
3726 return;
3727
3728 sctx->streamout.enabled_stream_buffers_mask = shader_with_so->info.enabled_streamout_buffer_mask;
3729 sctx->streamout.stride_in_dw = shader_with_so->info.base.xfb_stride;
3730
3731 /* GDS must be allocated when any GDS instructions are used, otherwise it hangs. */
3732 if (sctx->gfx_level >= GFX11 && sctx->gfx_level < GFX12 &&
3733 shader_with_so->info.enabled_streamout_buffer_mask && !sctx->screen->gds_oa) {
3734 /* Gfx11 only uses GDS OA, not GDS memory. */
3735 simple_mtx_lock(&sctx->screen->gds_mutex);
3736 if (!sctx->screen->gds_oa) {
3737 sctx->screen->gds_oa = sctx->ws->buffer_create(sctx->ws, 1, 1, RADEON_DOMAIN_OA,
3738 RADEON_FLAG_DRIVER_INTERNAL);
3739 assert(sctx->screen->gds_oa);
3740 }
3741 simple_mtx_unlock(&sctx->screen->gds_mutex);
3742
3743 if (sctx->screen->gds_oa)
3744 sctx->ws->cs_add_buffer(&sctx->gfx_cs, sctx->screen->gds_oa, RADEON_USAGE_READWRITE,
3745 (enum radeon_bo_domain)0);
3746 }
3747 }
3748
si_update_clip_regs(struct si_context * sctx,struct si_shader_selector * old_hw_vs,struct si_shader * old_hw_vs_variant,struct si_shader_selector * next_hw_vs,struct si_shader * next_hw_vs_variant)3749 static void si_update_clip_regs(struct si_context *sctx, struct si_shader_selector *old_hw_vs,
3750 struct si_shader *old_hw_vs_variant,
3751 struct si_shader_selector *next_hw_vs,
3752 struct si_shader *next_hw_vs_variant)
3753 {
3754 if (next_hw_vs &&
3755 (!old_hw_vs ||
3756 (old_hw_vs->stage == MESA_SHADER_VERTEX && old_hw_vs->info.base.vs.window_space_position) !=
3757 (next_hw_vs->stage == MESA_SHADER_VERTEX && next_hw_vs->info.base.vs.window_space_position) ||
3758 old_hw_vs->info.clipdist_mask != next_hw_vs->info.clipdist_mask ||
3759 old_hw_vs->info.culldist_mask != next_hw_vs->info.culldist_mask || !old_hw_vs_variant ||
3760 !next_hw_vs_variant ||
3761 old_hw_vs_variant->pa_cl_vs_out_cntl != next_hw_vs_variant->pa_cl_vs_out_cntl))
3762 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3763 }
3764
si_update_rasterized_prim(struct si_context * sctx)3765 static void si_update_rasterized_prim(struct si_context *sctx)
3766 {
3767 struct si_shader *hw_vs = si_get_vs(sctx)->current;
3768
3769 if (sctx->shader.gs.cso) {
3770 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
3771 si_set_rasterized_prim(sctx, sctx->shader.gs.cso->rast_prim, hw_vs, sctx->ngg);
3772 } else if (sctx->shader.tes.cso) {
3773 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
3774 si_set_rasterized_prim(sctx, sctx->shader.tes.cso->rast_prim, hw_vs, sctx->ngg);
3775 } else {
3776 /* The rasterized prim is determined by draw calls. */
3777 }
3778
3779 /* This must be done unconditionally because it also depends on si_shader fields. */
3780 si_update_ngg_sgpr_state_out_prim(sctx, hw_vs, sctx->ngg);
3781 }
3782
si_update_common_shader_state(struct si_context * sctx,struct si_shader_selector * sel,enum pipe_shader_type type)3783 static void si_update_common_shader_state(struct si_context *sctx, struct si_shader_selector *sel,
3784 enum pipe_shader_type type)
3785 {
3786 si_set_active_descriptors_for_shader(sctx, sel);
3787
3788 sctx->uses_bindless_samplers = si_shader_uses_bindless_samplers(sctx->shader.vs.cso) ||
3789 si_shader_uses_bindless_samplers(sctx->shader.gs.cso) ||
3790 si_shader_uses_bindless_samplers(sctx->shader.ps.cso) ||
3791 si_shader_uses_bindless_samplers(sctx->shader.tcs.cso) ||
3792 si_shader_uses_bindless_samplers(sctx->shader.tes.cso);
3793 sctx->uses_bindless_images = si_shader_uses_bindless_images(sctx->shader.vs.cso) ||
3794 si_shader_uses_bindless_images(sctx->shader.gs.cso) ||
3795 si_shader_uses_bindless_images(sctx->shader.ps.cso) ||
3796 si_shader_uses_bindless_images(sctx->shader.tcs.cso) ||
3797 si_shader_uses_bindless_images(sctx->shader.tes.cso);
3798
3799 if (type == PIPE_SHADER_VERTEX || type == PIPE_SHADER_TESS_EVAL || type == PIPE_SHADER_GEOMETRY)
3800 sctx->ngg_culling = 0; /* this will be enabled on the first draw if needed */
3801
3802 si_invalidate_inlinable_uniforms(sctx, type);
3803 sctx->do_update_shaders = true;
3804 }
3805
si_update_last_vgt_stage_state(struct si_context * sctx,struct si_shader_selector * old_hw_vs,struct si_shader * old_hw_vs_variant)3806 static void si_update_last_vgt_stage_state(struct si_context *sctx,
3807 /* hw_vs refers to the last VGT stage */
3808 struct si_shader_selector *old_hw_vs,
3809 struct si_shader *old_hw_vs_variant)
3810 {
3811 struct si_shader_ctx_state *hw_vs = si_get_vs(sctx);
3812
3813 si_update_vs_viewport_state(sctx);
3814 si_update_streamout_state(sctx);
3815 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant, hw_vs->cso, hw_vs->current);
3816 si_update_rasterized_prim(sctx);
3817
3818 /* Clear kill_pointsize because we only want it to be set in the last shader before PS. */
3819 sctx->shader.vs.key.ge.opt.kill_pointsize = 0;
3820 sctx->shader.tes.key.ge.opt.kill_pointsize = 0;
3821 sctx->shader.gs.key.ge.opt.kill_pointsize = 0;
3822 si_vs_ps_key_update_rast_prim_smooth_stipple(sctx);
3823 }
3824
si_bind_vs_shader(struct pipe_context * ctx,void * state)3825 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
3826 {
3827 struct si_context *sctx = (struct si_context *)ctx;
3828 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3829 struct si_shader *old_hw_vs_variant = si_get_vs(sctx)->current;
3830 struct si_shader_selector *sel = (struct si_shader_selector*)state;
3831
3832 if (sctx->shader.vs.cso == sel)
3833 return;
3834
3835 sctx->shader.vs.cso = sel;
3836 sctx->shader.vs.current = (sel && sel->variants_count) ? sel->variants[0] : NULL;
3837 sctx->num_vs_blit_sgprs = sel ? sel->info.base.vs.blit_sgprs_amd : 0;
3838 sctx->vs_uses_draw_id = sel ? sel->info.uses_drawid : false;
3839
3840 if (si_update_ngg(sctx))
3841 si_shader_change_notify(sctx);
3842
3843 si_update_common_shader_state(sctx, sel, PIPE_SHADER_VERTEX);
3844 si_select_draw_vbo(sctx);
3845 si_update_last_vgt_stage_state(sctx, old_hw_vs, old_hw_vs_variant);
3846 si_vs_key_update_inputs(sctx);
3847
3848 if (sctx->screen->dpbb_allowed) {
3849 bool force_off = sel && sel->info.options & SI_PROFILE_VS_NO_BINNING;
3850
3851 if (force_off != sctx->dpbb_force_off_profile_vs) {
3852 sctx->dpbb_force_off_profile_vs = force_off;
3853 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3854 }
3855 }
3856 }
3857
si_update_tess_uses_prim_id(struct si_context * sctx)3858 static void si_update_tess_uses_prim_id(struct si_context *sctx)
3859 {
3860 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
3861 sctx->shader.tes.cso &&
3862 ((sctx->shader.tcs.cso && sctx->shader.tcs.cso->info.uses_primid) ||
3863 sctx->shader.tes.cso->info.uses_primid ||
3864 (sctx->shader.gs.cso && sctx->shader.gs.cso->info.uses_primid) ||
3865 (!sctx->shader.gs.cso && sctx->shader.ps.cso && sctx->shader.ps.cso->info.uses_primid));
3866 }
3867
si_update_ngg(struct si_context * sctx)3868 bool si_update_ngg(struct si_context *sctx)
3869 {
3870 if (!sctx->screen->use_ngg) {
3871 assert(!sctx->ngg);
3872 return false;
3873 }
3874
3875 bool new_ngg = true;
3876
3877 if (sctx->shader.gs.cso && sctx->shader.tes.cso && sctx->shader.gs.cso->tess_turns_off_ngg) {
3878 new_ngg = false;
3879 } else if (sctx->gfx_level < GFX11) {
3880 struct si_shader_selector *last = si_get_vs(sctx)->cso;
3881
3882 if ((last && last->info.enabled_streamout_buffer_mask) ||
3883 sctx->streamout.prims_gen_query_enabled)
3884 new_ngg = false;
3885 }
3886
3887 if (new_ngg != sctx->ngg) {
3888 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3889 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3890 * pointers are set.
3891 */
3892 if (sctx->screen->info.has_vgt_flush_ngg_legacy_bug && !new_ngg) {
3893 sctx->barrier_flags |= SI_BARRIER_EVENT_VGT_FLUSH;
3894 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
3895
3896 if (sctx->gfx_level == GFX10) {
3897 /* Workaround for https://gitlab.freedesktop.org/mesa/mesa/-/issues/2941 */
3898 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3899 }
3900 }
3901
3902 sctx->ngg = new_ngg;
3903 si_select_draw_vbo(sctx);
3904 return true;
3905 }
3906 return false;
3907 }
3908
si_bind_gs_shader(struct pipe_context * ctx,void * state)3909 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3910 {
3911 struct si_context *sctx = (struct si_context *)ctx;
3912 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3913 struct si_shader *old_hw_vs_variant = si_get_vs(sctx)->current;
3914 struct si_shader_selector *sel = (struct si_shader_selector*)state;
3915 bool enable_changed = !!sctx->shader.gs.cso != !!sel;
3916 bool ngg_changed;
3917
3918 if (sctx->shader.gs.cso == sel)
3919 return;
3920
3921 sctx->shader.gs.cso = sel;
3922 sctx->shader.gs.current = (sel && sel->variants_count) ? sel->variants[0] : NULL;
3923 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3924
3925 si_update_common_shader_state(sctx, sel, PIPE_SHADER_GEOMETRY);
3926 si_select_draw_vbo(sctx);
3927
3928 ngg_changed = si_update_ngg(sctx);
3929 if (ngg_changed || enable_changed)
3930 si_shader_change_notify(sctx);
3931 if (enable_changed) {
3932 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3933 si_update_tess_uses_prim_id(sctx);
3934 }
3935 si_update_last_vgt_stage_state(sctx, old_hw_vs, old_hw_vs_variant);
3936 }
3937
si_bind_tcs_shader(struct pipe_context * ctx,void * state)3938 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3939 {
3940 struct si_context *sctx = (struct si_context *)ctx;
3941 struct si_shader_selector *sel = (struct si_shader_selector*)state;
3942 bool enable_changed = !!sctx->shader.tcs.cso != !!sel;
3943
3944 /* Note it could happen that user shader sel is same as fixed function shader,
3945 * so we should update this field even sctx->shader.tcs.cso == sel.
3946 */
3947 sctx->is_user_tcs = !!sel;
3948
3949 if (sctx->shader.tcs.cso == sel)
3950 return;
3951
3952 sctx->shader.tcs.cso = sel;
3953 sctx->shader.tcs.current = (sel && sel->variants_count) ? sel->variants[0] : NULL;
3954 si_update_tess_uses_prim_id(sctx);
3955 si_update_tess_in_out_patch_vertices(sctx);
3956
3957 si_update_common_shader_state(sctx, sel, PIPE_SHADER_TESS_CTRL);
3958
3959 if (enable_changed)
3960 sctx->last_tcs = NULL; /* invalidate derived tess state */
3961 }
3962
si_bind_tes_shader(struct pipe_context * ctx,void * state)3963 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3964 {
3965 struct si_context *sctx = (struct si_context *)ctx;
3966 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3967 struct si_shader *old_hw_vs_variant = si_get_vs(sctx)->current;
3968 struct si_shader_selector *sel = (struct si_shader_selector*)state;
3969 bool enable_changed = !!sctx->shader.tes.cso != !!sel;
3970
3971 if (sctx->shader.tes.cso == sel)
3972 return;
3973
3974 sctx->shader.tes.cso = sel;
3975 sctx->shader.tes.current = (sel && sel->variants_count) ? sel->variants[0] : NULL;
3976 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3977 si_update_tess_uses_prim_id(sctx);
3978
3979 sctx->shader.tcs.key.ge.opt.tes_prim_mode =
3980 sel ? sel->info.base.tess._primitive_mode : 0;
3981
3982 sctx->shader.tcs.key.ge.opt.tes_reads_tess_factors =
3983 sel ? sel->info.reads_tess_factors : 0;
3984
3985 if (sel) {
3986 sctx->tcs_offchip_layout &= 0x1fffffff;
3987 sctx->tcs_offchip_layout |=
3988 (sel->info.base.tess._primitive_mode << 29) |
3989 (sel->info.reads_tess_factors << 31);
3990
3991 si_mark_atom_dirty(sctx, &sctx->atoms.s.tess_io_layout);
3992 }
3993
3994 si_update_common_shader_state(sctx, sel, PIPE_SHADER_TESS_EVAL);
3995 si_select_draw_vbo(sctx);
3996
3997 bool ngg_changed = si_update_ngg(sctx);
3998 if (ngg_changed || enable_changed)
3999 si_shader_change_notify(sctx);
4000 if (enable_changed)
4001 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
4002 si_update_last_vgt_stage_state(sctx, old_hw_vs, old_hw_vs_variant);
4003 }
4004
si_update_vrs_flat_shading(struct si_context * sctx)4005 void si_update_vrs_flat_shading(struct si_context *sctx)
4006 {
4007 if (sctx->gfx_level >= GFX10_3 && sctx->shader.ps.cso) {
4008 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
4009 struct si_shader_info *info = &sctx->shader.ps.cso->info;
4010 bool allow_flat_shading =
4011 info->allow_flat_shading && !sctx->framebuffer.disable_vrs_flat_shading &&
4012 !rs->line_smooth && !rs->poly_smooth && !rs->poly_stipple_enable &&
4013 !rs->point_smooth && (rs->flatshade || !info->uses_interp_color);
4014
4015 if (sctx->allow_flat_shading != allow_flat_shading) {
4016 sctx->allow_flat_shading = allow_flat_shading;
4017 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4018 }
4019 }
4020 }
4021
si_bind_ps_shader(struct pipe_context * ctx,void * state)4022 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
4023 {
4024 struct si_context *sctx = (struct si_context *)ctx;
4025 struct si_shader_selector *old_sel = sctx->shader.ps.cso;
4026 struct si_shader_selector *sel = (struct si_shader_selector*)state;
4027
4028 /* skip if supplied shader is one already in use */
4029 if (old_sel == sel)
4030 return;
4031
4032 sctx->shader.ps.cso = sel;
4033 sctx->shader.ps.current = (sel && sel->variants_count) ? sel->variants[0] : NULL;
4034
4035 si_update_common_shader_state(sctx, sel, PIPE_SHADER_FRAGMENT);
4036 if (sel) {
4037 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
4038 si_update_tess_uses_prim_id(sctx);
4039
4040 if (!old_sel || old_sel->info.colors_written != sel->info.colors_written)
4041 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
4042
4043 if (sctx->screen->info.has_out_of_order_rast &&
4044 (!old_sel || old_sel->info.base.writes_memory != sel->info.base.writes_memory ||
4045 old_sel->info.base.fs.early_fragment_tests !=
4046 sel->info.base.fs.early_fragment_tests))
4047 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
4048 }
4049 si_update_ps_colorbuf0_slot(sctx);
4050
4051 si_ps_key_update_framebuffer(sctx);
4052 si_ps_key_update_framebuffer_blend_dsa_rasterizer(sctx);
4053 si_ps_key_update_rasterizer(sctx);
4054 si_ps_key_update_dsa(sctx);
4055 si_ps_key_update_sample_shading(sctx);
4056 si_ps_key_update_framebuffer_rasterizer_sample_shading(sctx);
4057 si_update_ps_inputs_read_or_disabled(sctx);
4058 si_update_vrs_flat_shading(sctx);
4059
4060 if (sctx->screen->dpbb_allowed) {
4061 bool force_off = sel && sel->info.options & SI_PROFILE_GFX9_GFX10_PS_NO_BINNING &&
4062 (sctx->gfx_level >= GFX9 && sctx->gfx_level <= GFX10_3);
4063
4064 if (force_off != sctx->dpbb_force_off_profile_ps) {
4065 sctx->dpbb_force_off_profile_ps = force_off;
4066 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
4067 }
4068 }
4069 }
4070
si_delete_shader(struct si_context * sctx,struct si_shader * shader)4071 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
4072 {
4073 if (shader->is_optimized) {
4074 util_queue_drop_job(&sctx->screen->shader_compiler_queue_opt_variants, &shader->ready);
4075 }
4076
4077 util_queue_fence_destroy(&shader->ready);
4078
4079 /* If destroyed shaders were not unbound, the next compiled
4080 * shader variant could get the same pointer address and so
4081 * binding it to the same shader stage would be considered
4082 * a no-op, causing random behavior.
4083 */
4084 int state_index = -1;
4085
4086 switch (shader->selector->stage) {
4087 case MESA_SHADER_VERTEX:
4088 if (shader->key.ge.as_ls) {
4089 if (sctx->gfx_level <= GFX8)
4090 state_index = SI_STATE_IDX(ls);
4091 } else if (shader->key.ge.as_es) {
4092 if (sctx->gfx_level <= GFX8)
4093 state_index = SI_STATE_IDX(es);
4094 } else if (shader->key.ge.as_ngg) {
4095 state_index = SI_STATE_IDX(gs);
4096 } else {
4097 state_index = SI_STATE_IDX(vs);
4098 }
4099 break;
4100 case MESA_SHADER_TESS_CTRL:
4101 state_index = SI_STATE_IDX(hs);
4102 break;
4103 case MESA_SHADER_TESS_EVAL:
4104 if (shader->key.ge.as_es) {
4105 if (sctx->gfx_level <= GFX8)
4106 state_index = SI_STATE_IDX(es);
4107 } else if (shader->key.ge.as_ngg) {
4108 state_index = SI_STATE_IDX(gs);
4109 } else {
4110 state_index = SI_STATE_IDX(vs);
4111 }
4112 break;
4113 case MESA_SHADER_GEOMETRY:
4114 if (shader->is_gs_copy_shader)
4115 state_index = SI_STATE_IDX(vs);
4116 else
4117 state_index = SI_STATE_IDX(gs);
4118 break;
4119 case MESA_SHADER_FRAGMENT:
4120 state_index = SI_STATE_IDX(ps);
4121 break;
4122 default:;
4123 }
4124
4125 if (shader->gs_copy_shader)
4126 si_delete_shader(sctx, shader->gs_copy_shader);
4127
4128 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
4129 si_shader_destroy(shader);
4130 si_pm4_free_state(sctx, &shader->pm4, state_index);
4131 }
4132
si_destroy_shader_selector(struct pipe_context * ctx,void * cso)4133 static void si_destroy_shader_selector(struct pipe_context *ctx, void *cso)
4134 {
4135 struct si_context *sctx = (struct si_context *)ctx;
4136 struct si_shader_selector *sel = (struct si_shader_selector *)cso;
4137
4138 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
4139
4140 if (sctx->shaders[sel->stage].cso == sel) {
4141 sctx->shaders[sel->stage].cso = NULL;
4142 sctx->shaders[sel->stage].current = NULL;
4143 }
4144
4145 for (unsigned i = 0; i < sel->variants_count; i++) {
4146 si_delete_shader(sctx, sel->variants[i]);
4147 }
4148
4149 for (unsigned i = 0; i < 2; i++) {
4150 if (sel->main_shader_part[i])
4151 si_delete_shader(sctx, sel->main_shader_part[i]);
4152 if (sel->main_shader_part_ls[i])
4153 si_delete_shader(sctx, sel->main_shader_part_ls[i]);
4154 if (sel->main_shader_part_ngg[i])
4155 si_delete_shader(sctx, sel->main_shader_part_ngg[i]);
4156 if (sel->main_shader_part_ngg_es[i])
4157 si_delete_shader(sctx, sel->main_shader_part_ngg_es[i]);
4158 }
4159
4160 if (sel->main_shader_part_es)
4161 si_delete_shader(sctx, sel->main_shader_part_es);
4162
4163 free(sel->keys);
4164 free(sel->variants);
4165
4166 util_queue_fence_destroy(&sel->ready);
4167 simple_mtx_destroy(&sel->mutex);
4168 ralloc_free(sel->nir);
4169 free(sel->nir_binary);
4170 free(sel);
4171 }
4172
si_delete_shader_selector(struct pipe_context * ctx,void * state)4173 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
4174 {
4175 struct si_context *sctx = (struct si_context *)ctx;
4176 struct si_shader_selector *sel = (struct si_shader_selector *)state;
4177
4178 si_shader_selector_reference(sctx, &sel, NULL);
4179 }
4180
4181 /**
4182 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
4183 */
si_cs_preamble_add_vgt_flush(struct si_context * sctx,bool tmz)4184 static void si_cs_preamble_add_vgt_flush(struct si_context *sctx, bool tmz)
4185 {
4186 struct si_pm4_state *pm4 = tmz ? sctx->cs_preamble_state_tmz : sctx->cs_preamble_state;
4187 bool *has_vgt_flush = tmz ? &sctx->cs_preamble_has_vgt_flush_tmz :
4188 &sctx->cs_preamble_has_vgt_flush;
4189
4190 /* We shouldn't get here if registers are shadowed. */
4191 assert(!sctx->shadowing.registers);
4192
4193 if (*has_vgt_flush)
4194 return;
4195
4196 /* Done by Vulkan before VGT_FLUSH. */
4197 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_EVENT_WRITE, 0, 0));
4198 ac_pm4_cmd_add(&pm4->base, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
4199
4200 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
4201 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_EVENT_WRITE, 0, 0));
4202 ac_pm4_cmd_add(&pm4->base, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
4203 ac_pm4_finalize(&pm4->base);
4204
4205 *has_vgt_flush = true;
4206 }
4207
4208 /**
4209 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
4210 */
si_emit_vgt_flush(struct radeon_cmdbuf * cs)4211 static void si_emit_vgt_flush(struct radeon_cmdbuf *cs)
4212 {
4213 radeon_begin(cs);
4214
4215 /* This is required before VGT_FLUSH. */
4216 radeon_event_write(V_028A90_VS_PARTIAL_FLUSH);
4217
4218 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
4219 radeon_event_write(V_028A90_VGT_FLUSH);
4220 radeon_end();
4221 }
4222
4223 /* Initialize state related to ESGS / GSVS ring buffers */
si_update_gs_ring_buffers(struct si_context * sctx)4224 bool si_update_gs_ring_buffers(struct si_context *sctx)
4225 {
4226 assert(sctx->gfx_level < GFX11);
4227
4228 struct si_shader_selector *es =
4229 sctx->shader.tes.cso ? sctx->shader.tes.cso : sctx->shader.vs.cso;
4230 struct si_shader_selector *gs = sctx->shader.gs.cso;
4231
4232 /* Chip constants. */
4233 unsigned num_se = sctx->screen->info.max_se;
4234 unsigned wave_size = 64;
4235 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
4236 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
4237 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
4238 */
4239 unsigned gs_vertex_reuse = (sctx->gfx_level >= GFX8 ? 32 : 16) * num_se;
4240 unsigned alignment = 256 * num_se;
4241 /* The maximum size is 63.999 MB per SE. */
4242 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
4243
4244 /* Calculate the minimum size. */
4245 unsigned min_esgs_ring_size = align(es->info.esgs_vertex_stride * gs_vertex_reuse * wave_size, alignment);
4246
4247 /* These are recommended sizes, not minimum sizes. */
4248 unsigned esgs_ring_size =
4249 max_gs_waves * 2 * wave_size * es->info.esgs_vertex_stride * gs->info.gs_input_verts_per_prim;
4250 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size * gs->info.max_gsvs_emit_size;
4251
4252 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
4253 esgs_ring_size = align(esgs_ring_size, alignment);
4254 gsvs_ring_size = align(gsvs_ring_size, alignment);
4255
4256 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
4257 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
4258
4259 /* Some rings don't have to be allocated if shaders don't use them.
4260 * (e.g. no varyings between ES and GS or GS and VS)
4261 *
4262 * GFX9 doesn't have the ESGS ring.
4263 */
4264 bool update_esgs = sctx->gfx_level <= GFX8 && esgs_ring_size &&
4265 (!sctx->esgs_ring || sctx->esgs_ring->width0 < esgs_ring_size);
4266 bool update_gsvs =
4267 gsvs_ring_size && (!sctx->gsvs_ring || sctx->gsvs_ring->width0 < gsvs_ring_size);
4268
4269 if (!update_esgs && !update_gsvs)
4270 return true;
4271
4272 if (update_esgs) {
4273 pipe_resource_reference(&sctx->esgs_ring, NULL);
4274 sctx->esgs_ring =
4275 pipe_aligned_buffer_create(sctx->b.screen,
4276 PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL |
4277 SI_RESOURCE_FLAG_DISCARDABLE,
4278 PIPE_USAGE_DEFAULT,
4279 esgs_ring_size, sctx->screen->info.pte_fragment_size);
4280 if (!sctx->esgs_ring)
4281 return false;
4282 }
4283
4284 if (update_gsvs) {
4285 pipe_resource_reference(&sctx->gsvs_ring, NULL);
4286 sctx->gsvs_ring =
4287 pipe_aligned_buffer_create(sctx->b.screen,
4288 PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL |
4289 SI_RESOURCE_FLAG_DISCARDABLE,
4290 PIPE_USAGE_DEFAULT,
4291 gsvs_ring_size, sctx->screen->info.pte_fragment_size);
4292 if (!sctx->gsvs_ring)
4293 return false;
4294 }
4295
4296 /* Set ring bindings. */
4297 if (sctx->esgs_ring) {
4298 assert(sctx->gfx_level <= GFX8);
4299 si_set_ring_buffer(sctx, SI_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, false,
4300 false, 0, 0, 0);
4301 }
4302 if (sctx->gsvs_ring) {
4303 si_set_ring_buffer(sctx, SI_RING_GSVS, sctx->gsvs_ring, 0, sctx->gsvs_ring->width0, false,
4304 false, 0, 0, 0);
4305 }
4306
4307 if (sctx->shadowing.registers) {
4308 /* These registers will be shadowed, so set them only once. */
4309 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
4310
4311 assert(sctx->gfx_level >= GFX7);
4312
4313 si_emit_vgt_flush(cs);
4314
4315 radeon_begin(cs);
4316
4317 /* Set the GS registers. */
4318 if (sctx->esgs_ring) {
4319 assert(sctx->gfx_level <= GFX8);
4320 radeon_set_uconfig_reg(R_030900_VGT_ESGS_RING_SIZE,
4321 sctx->esgs_ring->width0 / 256);
4322 }
4323 if (sctx->gsvs_ring) {
4324 radeon_set_uconfig_reg(R_030904_VGT_GSVS_RING_SIZE,
4325 sctx->gsvs_ring->width0 / 256);
4326 }
4327 radeon_end();
4328 return true;
4329 }
4330
4331 /* The codepath without register shadowing. */
4332 for (unsigned tmz = 0; tmz <= 1; tmz++) {
4333 struct si_pm4_state *pm4 = tmz ? sctx->cs_preamble_state_tmz : sctx->cs_preamble_state;
4334 uint16_t *gs_ring_state_dw_offset = tmz ? &sctx->gs_ring_state_dw_offset_tmz :
4335 &sctx->gs_ring_state_dw_offset;
4336 unsigned old_ndw = 0;
4337
4338 si_cs_preamble_add_vgt_flush(sctx, tmz);
4339
4340 if (!*gs_ring_state_dw_offset) {
4341 /* We are here for the first time. The packets will be added. */
4342 *gs_ring_state_dw_offset = pm4->base.ndw;
4343 } else {
4344 /* We have been here before. Overwrite the previous packets. */
4345 old_ndw = pm4->base.ndw;
4346 pm4->base.ndw = *gs_ring_state_dw_offset;
4347 }
4348
4349 /* Unallocated rings are written to reserve the space in the pm4
4350 * (to be able to overwrite them later). */
4351 if (sctx->gfx_level >= GFX7) {
4352 if (sctx->gfx_level <= GFX8)
4353 ac_pm4_set_reg(&pm4->base, R_030900_VGT_ESGS_RING_SIZE,
4354 sctx->esgs_ring ? sctx->esgs_ring->width0 / 256 : 0);
4355 ac_pm4_set_reg(&pm4->base, R_030904_VGT_GSVS_RING_SIZE,
4356 sctx->gsvs_ring ? sctx->gsvs_ring->width0 / 256 : 0);
4357 } else {
4358 ac_pm4_set_reg(&pm4->base, R_0088C8_VGT_ESGS_RING_SIZE,
4359 sctx->esgs_ring ? sctx->esgs_ring->width0 / 256 : 0);
4360 ac_pm4_set_reg(&pm4->base, R_0088CC_VGT_GSVS_RING_SIZE,
4361 sctx->gsvs_ring ? sctx->gsvs_ring->width0 / 256 : 0);
4362 }
4363 ac_pm4_finalize(&pm4->base);
4364
4365 if (old_ndw) {
4366 pm4->base.ndw = old_ndw;
4367 pm4->base.last_opcode = 255; /* invalid opcode (we don't save the last opcode) */
4368 }
4369 }
4370
4371 /* Flush the context to re-emit both cs_preamble states. */
4372 sctx->initial_gfx_cs_size = 0; /* force flush */
4373 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
4374
4375 return true;
4376 }
4377
si_shader_lock(struct si_shader * shader)4378 static void si_shader_lock(struct si_shader *shader)
4379 {
4380 simple_mtx_lock(&shader->selector->mutex);
4381 if (shader->previous_stage_sel) {
4382 assert(shader->previous_stage_sel != shader->selector);
4383 simple_mtx_lock(&shader->previous_stage_sel->mutex);
4384 }
4385 }
4386
si_shader_unlock(struct si_shader * shader)4387 static void si_shader_unlock(struct si_shader *shader)
4388 {
4389 if (shader->previous_stage_sel)
4390 simple_mtx_unlock(&shader->previous_stage_sel->mutex);
4391 simple_mtx_unlock(&shader->selector->mutex);
4392 }
4393
4394 /**
4395 * @returns 1 if \p sel has been updated to use a new scratch buffer
4396 * 0 if not
4397 * < 0 if there was a failure
4398 */
si_update_scratch_buffer(struct si_context * sctx,struct si_shader * shader)4399 static int si_update_scratch_buffer(struct si_context *sctx, struct si_shader *shader)
4400 {
4401 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
4402
4403 if (!shader)
4404 return 0;
4405
4406 /* This shader doesn't need a scratch buffer */
4407 if (shader->config.scratch_bytes_per_wave == 0)
4408 return 0;
4409
4410 /* Prevent race conditions when updating:
4411 * - si_shader::scratch_va
4412 * - si_shader::binary::code
4413 * - si_shader::previous_stage::binary::code.
4414 */
4415 si_shader_lock(shader);
4416
4417 /* This shader is already configured to use the current
4418 * scratch buffer. */
4419 if (shader->scratch_va == scratch_va) {
4420 si_shader_unlock(shader);
4421 return 0;
4422 }
4423
4424 assert(sctx->scratch_buffer);
4425
4426 /* Replace the shader bo with a new bo that has the relocs applied. */
4427 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
4428 si_shader_unlock(shader);
4429 return -1;
4430 }
4431
4432 /* Update the shader state to use the new shader bo. */
4433 si_shader_init_pm4_state(sctx->screen, shader);
4434 shader->scratch_va = scratch_va;
4435
4436 si_shader_unlock(shader);
4437 return 1;
4438 }
4439
si_update_scratch_relocs(struct si_context * sctx)4440 static bool si_update_scratch_relocs(struct si_context *sctx)
4441 {
4442 int r;
4443
4444 /* Update the shaders, so that they are using the latest scratch.
4445 * The scratch buffer may have been changed since these shaders were
4446 * last used, so we still need to try to update them, even if they
4447 * require scratch buffers smaller than the current size.
4448 */
4449 r = si_update_scratch_buffer(sctx, sctx->shader.ps.current);
4450 if (r < 0)
4451 return false;
4452 if (r == 1)
4453 si_pm4_bind_state(sctx, ps, sctx->shader.ps.current);
4454
4455 r = si_update_scratch_buffer(sctx, sctx->shader.gs.current);
4456 if (r < 0)
4457 return false;
4458 if (r == 1)
4459 si_pm4_bind_state(sctx, gs, sctx->shader.gs.current);
4460
4461 r = si_update_scratch_buffer(sctx, sctx->shader.tcs.current);
4462 if (r < 0)
4463 return false;
4464 if (r == 1)
4465 si_pm4_bind_state(sctx, hs, sctx->shader.tcs.current);
4466
4467 /* VS can be bound as LS, ES, or VS. */
4468 r = si_update_scratch_buffer(sctx, sctx->shader.vs.current);
4469 if (r < 0)
4470 return false;
4471 if (r == 1) {
4472 if (sctx->shader.vs.current->key.ge.as_ls)
4473 si_pm4_bind_state(sctx, ls, sctx->shader.vs.current);
4474 else if (sctx->shader.vs.current->key.ge.as_es)
4475 si_pm4_bind_state(sctx, es, sctx->shader.vs.current);
4476 else if (sctx->shader.vs.current->key.ge.as_ngg)
4477 si_pm4_bind_state(sctx, gs, sctx->shader.vs.current);
4478 else
4479 si_pm4_bind_state(sctx, vs, sctx->shader.vs.current);
4480 }
4481
4482 /* TES can be bound as ES or VS. */
4483 r = si_update_scratch_buffer(sctx, sctx->shader.tes.current);
4484 if (r < 0)
4485 return false;
4486 if (r == 1) {
4487 if (sctx->shader.tes.current->key.ge.as_es)
4488 si_pm4_bind_state(sctx, es, sctx->shader.tes.current);
4489 else if (sctx->shader.tes.current->key.ge.as_ngg)
4490 si_pm4_bind_state(sctx, gs, sctx->shader.tes.current);
4491 else
4492 si_pm4_bind_state(sctx, vs, sctx->shader.tes.current);
4493 }
4494
4495 return true;
4496 }
4497
si_update_spi_tmpring_size(struct si_context * sctx,unsigned bytes)4498 bool si_update_spi_tmpring_size(struct si_context *sctx, unsigned bytes)
4499 {
4500 unsigned spi_tmpring_size;
4501 ac_get_scratch_tmpring_size(&sctx->screen->info, bytes,
4502 &sctx->max_seen_scratch_bytes_per_wave, &spi_tmpring_size);
4503
4504 unsigned scratch_needed_size = sctx->max_seen_scratch_bytes_per_wave *
4505 sctx->screen->info.max_scratch_waves;
4506
4507 if (scratch_needed_size > 0) {
4508 if (!sctx->scratch_buffer || scratch_needed_size > sctx->scratch_buffer->b.b.width0) {
4509 /* Create a bigger scratch buffer */
4510 si_resource_reference(&sctx->scratch_buffer, NULL);
4511
4512 sctx->scratch_buffer = si_aligned_buffer_create(
4513 &sctx->screen->b,
4514 PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL |
4515 SI_RESOURCE_FLAG_DISCARDABLE,
4516 PIPE_USAGE_DEFAULT, scratch_needed_size,
4517 sctx->screen->info.pte_fragment_size);
4518 if (!sctx->scratch_buffer)
4519 return false;
4520 }
4521
4522 if (!sctx->screen->info.has_scratch_base_registers && !si_update_scratch_relocs(sctx))
4523 return false;
4524 }
4525
4526 if (spi_tmpring_size != sctx->spi_tmpring_size) {
4527 sctx->spi_tmpring_size = spi_tmpring_size;
4528 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
4529 }
4530 return true;
4531 }
4532
si_init_tess_factor_ring(struct si_context * sctx)4533 void si_init_tess_factor_ring(struct si_context *sctx)
4534 {
4535 struct si_screen *sscreen = sctx->screen;
4536 assert(!sctx->has_tessellation);
4537
4538 if (sctx->has_tessellation)
4539 return;
4540
4541 simple_mtx_lock(&sscreen->tess_ring_lock);
4542
4543 if (!sscreen->tess_rings) {
4544 /* The address must be aligned to 2^19, because the shader only
4545 * receives the high 13 bits. Align it to 2MB to match the GPU page size.
4546 */
4547 sscreen->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
4548 PIPE_RESOURCE_FLAG_UNMAPPABLE |
4549 SI_RESOURCE_FLAG_32BIT |
4550 SI_RESOURCE_FLAG_DRIVER_INTERNAL |
4551 SI_RESOURCE_FLAG_DISCARDABLE,
4552 PIPE_USAGE_DEFAULT,
4553 sscreen->hs.tess_offchip_ring_size +
4554 sscreen->hs.tess_factor_ring_size,
4555 2 * 1024 * 1024);
4556 if (!sscreen->tess_rings) {
4557 simple_mtx_unlock(&sscreen->tess_ring_lock);
4558 return;
4559 }
4560
4561 if (sscreen->info.has_tmz_support) {
4562 sscreen->tess_rings_tmz = pipe_aligned_buffer_create(sctx->b.screen,
4563 PIPE_RESOURCE_FLAG_UNMAPPABLE |
4564 PIPE_RESOURCE_FLAG_ENCRYPTED |
4565 SI_RESOURCE_FLAG_32BIT |
4566 SI_RESOURCE_FLAG_DRIVER_INTERNAL |
4567 SI_RESOURCE_FLAG_DISCARDABLE,
4568 PIPE_USAGE_DEFAULT,
4569 sscreen->hs.tess_offchip_ring_size +
4570 sscreen->hs.tess_factor_ring_size,
4571 2 * 1024 * 1024);
4572 }
4573 }
4574
4575 simple_mtx_unlock(&sscreen->tess_ring_lock);
4576 sctx->has_tessellation = true;
4577
4578 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_ge_ring_state);
4579 }
4580
si_emit_vgt_pipeline_state(struct si_context * sctx,unsigned index)4581 static void si_emit_vgt_pipeline_state(struct si_context *sctx, unsigned index)
4582 {
4583 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
4584
4585 radeon_begin(cs);
4586 radeon_opt_set_context_reg(sctx->gfx_level >= GFX12 ?
4587 R_028A98_VGT_SHADER_STAGES_EN :
4588 R_028B54_VGT_SHADER_STAGES_EN,
4589 SI_TRACKED_VGT_SHADER_STAGES_EN, sctx->vgt_shader_stages_en);
4590 if (sctx->gfx_level == GFX10_3) {
4591 /* Legacy Tess+GS should disable reuse to prevent hangs on GFX10.3. */
4592 bool has_legacy_tess_gs = G_028B54_HS_EN(sctx->vgt_shader_stages_en) &&
4593 G_028B54_GS_EN(sctx->vgt_shader_stages_en) &&
4594 !G_028B54_PRIMGEN_EN(sctx->vgt_shader_stages_en); /* !NGG */
4595
4596 radeon_opt_set_context_reg(R_028AB4_VGT_REUSE_OFF, SI_TRACKED_VGT_REUSE_OFF,
4597 S_028AB4_REUSE_OFF(has_legacy_tess_gs));
4598 }
4599 radeon_end_update_context_roll();
4600
4601 if (sctx->gfx_level >= GFX10) {
4602 uint32_t ge_cntl = sctx->ge_cntl;
4603
4604 if (sctx->gfx_level < GFX11 && sctx->shader.tes.cso) {
4605 /* This must be a multiple of VGT_LS_HS_CONFIG.NUM_PATCHES. */
4606 ge_cntl |= S_03096C_PRIM_GRP_SIZE_GFX10(sctx->num_patches_per_workgroup);
4607 }
4608
4609 radeon_begin_again(cs);
4610 radeon_opt_set_uconfig_reg(R_03096C_GE_CNTL, SI_TRACKED_GE_CNTL, ge_cntl);
4611 radeon_end();
4612 }
4613 }
4614
si_emit_scratch_state(struct si_context * sctx,unsigned index)4615 static void si_emit_scratch_state(struct si_context *sctx, unsigned index)
4616 {
4617 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
4618
4619 radeon_begin(cs);
4620 if (sctx->gfx_level >= GFX11) {
4621 radeon_set_context_reg_seq(R_0286E8_SPI_TMPRING_SIZE, 3);
4622 radeon_emit(sctx->spi_tmpring_size); /* SPI_TMPRING_SIZE */
4623 radeon_emit(sctx->scratch_buffer->gpu_address >> 8); /* SPI_GFX_SCRATCH_BASE_LO */
4624 radeon_emit(sctx->scratch_buffer->gpu_address >> 40); /* SPI_GFX_SCRATCH_BASE_HI */
4625 } else {
4626 radeon_set_context_reg(R_0286E8_SPI_TMPRING_SIZE, sctx->spi_tmpring_size);
4627 }
4628 radeon_end();
4629
4630 if (sctx->scratch_buffer) {
4631 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->scratch_buffer,
4632 RADEON_USAGE_READWRITE | RADEON_PRIO_SCRATCH_BUFFER);
4633 }
4634 }
4635
4636 struct si_fixed_func_tcs_shader_key {
4637 uint64_t outputs_written;
4638 uint8_t vertices_out;
4639 };
4640
4641 DERIVE_HASH_TABLE(si_fixed_func_tcs_shader_key);
4642
si_set_tcs_to_fixed_func_shader(struct si_context * sctx)4643 bool si_set_tcs_to_fixed_func_shader(struct si_context *sctx)
4644 {
4645 if (!sctx->fixed_func_tcs_shader_cache) {
4646 sctx->fixed_func_tcs_shader_cache = si_fixed_func_tcs_shader_key_table_create(NULL);
4647 }
4648
4649 struct si_fixed_func_tcs_shader_key key;
4650 key.outputs_written = sctx->shader.vs.cso->info.ls_es_outputs_written;
4651 key.vertices_out = sctx->patch_vertices;
4652
4653 struct hash_entry *entry = _mesa_hash_table_search(
4654 sctx->fixed_func_tcs_shader_cache, &key);
4655
4656 struct si_shader_selector *tcs;
4657 if (entry)
4658 tcs = (struct si_shader_selector *)entry->data;
4659 else {
4660 tcs = (struct si_shader_selector *)si_create_passthrough_tcs(sctx);
4661 if (!tcs)
4662 return false;
4663 _mesa_hash_table_insert(sctx->fixed_func_tcs_shader_cache, &key, (void *)tcs);
4664 }
4665
4666 sctx->shader.tcs.cso = tcs;
4667 return true;
4668 }
4669
si_update_tess_in_out_patch_vertices(struct si_context * sctx)4670 static void si_update_tess_in_out_patch_vertices(struct si_context *sctx)
4671 {
4672 if (sctx->is_user_tcs) {
4673 struct si_shader_selector *tcs = sctx->shader.tcs.cso;
4674
4675 bool same_patch_vertices =
4676 sctx->gfx_level >= GFX9 &&
4677 sctx->patch_vertices == tcs->info.base.tess.tcs_vertices_out;
4678
4679 if (sctx->shader.tcs.key.ge.opt.same_patch_vertices != same_patch_vertices) {
4680 sctx->shader.tcs.key.ge.opt.same_patch_vertices = same_patch_vertices;
4681 sctx->do_update_shaders = true;
4682 }
4683 } else {
4684 /* These fields are static for fixed function TCS. So no need to set
4685 * do_update_shaders between fixed-TCS draws. As fixed-TCS to user-TCS
4686 * or opposite, do_update_shaders should already be set by bind state.
4687 */
4688 sctx->shader.tcs.key.ge.opt.same_patch_vertices = sctx->gfx_level >= GFX9;
4689
4690 /* User may only change patch vertices, needs to update fixed func TCS. */
4691 if (sctx->shader.tcs.cso &&
4692 sctx->shader.tcs.cso->info.base.tess.tcs_vertices_out != sctx->patch_vertices)
4693 sctx->do_update_shaders = true;
4694 }
4695 }
4696
si_set_patch_vertices(struct pipe_context * ctx,uint8_t patch_vertices)4697 static void si_set_patch_vertices(struct pipe_context *ctx, uint8_t patch_vertices)
4698 {
4699 struct si_context *sctx = (struct si_context *)ctx;
4700
4701 if (sctx->patch_vertices != patch_vertices) {
4702 sctx->patch_vertices = patch_vertices;
4703 si_update_tess_in_out_patch_vertices(sctx);
4704 if (sctx->shader.tcs.current) {
4705 /* Update the io layout now if possible,
4706 * otherwise make sure it's done by si_update_shaders.
4707 */
4708 if (sctx->has_tessellation)
4709 si_update_tess_io_layout_state(sctx);
4710 else
4711 sctx->do_update_shaders = true;
4712 }
4713
4714 /* Gfx12 programs patch_vertices in VGT_PRIMITIVE_TYPE.NUM_INPUT_CP. Make sure
4715 * the register is updated.
4716 */
4717 if (sctx->gfx_level >= GFX12 && sctx->last_prim == MESA_PRIM_PATCHES)
4718 sctx->last_prim = -1;
4719 }
4720 }
4721
si_shader_lshs_vertex_stride(struct si_shader * ls)4722 unsigned si_shader_lshs_vertex_stride(struct si_shader *ls)
4723 {
4724 unsigned num_slots;
4725
4726 if (ls->selector->stage == MESA_SHADER_VERTEX && !ls->next_shader) {
4727 assert(ls->key.ge.as_ls);
4728 assert(ls->selector->screen->info.gfx_level <= GFX8 || !ls->is_monolithic);
4729 num_slots = util_last_bit64(ls->selector->info.ls_es_outputs_written);
4730 } else {
4731 struct si_shader *tcs = ls->next_shader ? ls->next_shader : ls;
4732
4733 assert(tcs->selector->stage == MESA_SHADER_TESS_CTRL);
4734 assert(tcs->selector->screen->info.gfx_level >= GFX9);
4735
4736 if (tcs->is_monolithic) {
4737 uint64_t lds_inputs_read = tcs->selector->info.tcs_inputs_via_lds;
4738
4739 /* If the TCS in/out number of vertices is different, all inputs are passed via LDS. */
4740 if (!tcs->key.ge.opt.same_patch_vertices)
4741 lds_inputs_read |= tcs->selector->info.tcs_inputs_via_temp;
4742
4743 /* NIR lowering passes pack LS outputs/HS inputs if the usage masks of both are known. */
4744 num_slots = util_bitcount64(lds_inputs_read);
4745 } else {
4746 num_slots = util_last_bit64(tcs->previous_stage_sel->info.ls_es_outputs_written);
4747 }
4748 }
4749
4750 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex starts on a different LDS
4751 * bank.
4752 */
4753 return num_slots ? num_slots * 16 + 4 : 0;
4754 }
4755
4756 /**
4757 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
4758 * LS.LDS_SIZE is shared by all 3 shader stages.
4759 *
4760 * The information about LDS and other non-compile-time parameters is then
4761 * written to userdata SGPRs.
4762 *
4763 * This depends on:
4764 * - patch_vertices
4765 * - VS and the currently selected shader variant (called by si_update_shaders)
4766 * - TCS and the currently selected shader variant (called by si_update_shaders)
4767 * - tess_uses_prim_id (called by si_update_shaders)
4768 * - sh_base[TESS_EVAL] depending on GS on/off (called by si_update_shaders)
4769 */
si_update_tess_io_layout_state(struct si_context * sctx)4770 void si_update_tess_io_layout_state(struct si_context *sctx)
4771 {
4772 struct si_shader *ls_current;
4773 struct si_shader_selector *tcs = sctx->shader.tcs.cso;
4774 bool tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
4775 bool has_primid_instancing_bug = sctx->gfx_level == GFX6 && sctx->screen->info.max_se == 1;
4776 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
4777 uint8_t num_tcs_input_cp = sctx->patch_vertices;
4778
4779 assert(sctx->shader.tcs.current);
4780
4781 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
4782 if (sctx->gfx_level >= GFX9) {
4783 ls_current = sctx->shader.tcs.current;
4784 } else {
4785 ls_current = sctx->shader.vs.current;
4786
4787 if (!ls_current) {
4788 sctx->do_update_shaders = true;
4789 return;
4790 }
4791 }
4792
4793 if (sctx->last_ls == ls_current && sctx->last_tcs == tcs &&
4794 sctx->last_tes_sh_base == tes_sh_base && sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
4795 (!has_primid_instancing_bug || (sctx->last_tess_uses_primid == tess_uses_primid)))
4796 return;
4797
4798 sctx->last_ls = ls_current;
4799 sctx->last_tcs = tcs;
4800 sctx->last_tes_sh_base = tes_sh_base;
4801 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
4802 sctx->last_tess_uses_primid = tess_uses_primid;
4803
4804 /* This calculates how shader inputs and outputs among VS, TCS, and TES
4805 * are laid out in LDS and memory.
4806 */
4807 unsigned num_tcs_output_cp = tcs->info.base.tess.tcs_vertices_out;
4808 unsigned lds_input_vertex_size = si_shader_lshs_vertex_stride(ls_current);
4809 unsigned num_mem_tcs_outputs = util_last_bit64(tcs->info.tcs_outputs_written_for_tes);
4810 unsigned num_mem_tcs_patch_outputs =
4811 util_last_bit(tcs->info.patch_outputs_written_for_tes |
4812 (!ls_current->is_monolithic || ls_current->key.ge.opt.tes_reads_tess_factors ?
4813 tcs->info.tess_levels_written_for_tes : 0));
4814 unsigned num_patches, lds_size;
4815
4816 /* Compute NUM_PATCHES and LDS_SIZE. */
4817 ac_nir_compute_tess_wg_info(&sctx->screen->info, &tcs->info.base, ls_current->wave_size,
4818 tess_uses_primid, tcs->info.tessfactors_are_def_in_all_invocs,
4819 num_tcs_input_cp, lds_input_vertex_size,
4820 num_mem_tcs_outputs, num_mem_tcs_patch_outputs,
4821 &num_patches, &lds_size);
4822
4823 if (sctx->num_patches_per_workgroup != num_patches) {
4824 sctx->num_patches_per_workgroup = num_patches;
4825 si_mark_atom_dirty(sctx, &sctx->atoms.s.vgt_pipeline_state);
4826 }
4827
4828 /* Compute userdata SGPRs. */
4829 unsigned num_lds_vs_outputs = lds_input_vertex_size / 16;
4830 assert(ls_current->config.lds_size == 0);
4831 assert(num_tcs_input_cp <= 32);
4832 assert(num_tcs_output_cp <= 32);
4833 assert(num_patches <= 128);
4834 assert(num_lds_vs_outputs <= 63);
4835 assert(num_mem_tcs_outputs <= 63);
4836
4837 uint64_t ring_va =
4838 sctx->ws->cs_is_secure(&sctx->gfx_cs) ?
4839 si_resource(sctx->screen->tess_rings_tmz)->gpu_address :
4840 si_resource(sctx->screen->tess_rings)->gpu_address;
4841 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
4842
4843 sctx->tes_offchip_ring_va_sgpr = ring_va;
4844 sctx->tcs_offchip_layout &= 0xe0000000;
4845 sctx->tcs_offchip_layout |=
4846 (num_patches - 1) | ((num_tcs_output_cp - 1) << 7) | ((num_tcs_input_cp - 1) << 12) |
4847 (num_lds_vs_outputs << 17) | (num_mem_tcs_outputs << 23);
4848
4849 unsigned ls_hs_rsrc2;
4850
4851 if (sctx->gfx_level >= GFX9) {
4852 ls_hs_rsrc2 = sctx->shader.tcs.current->config.rsrc2;
4853
4854 if (sctx->gfx_level >= GFX10)
4855 ls_hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(lds_size);
4856 else
4857 ls_hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(lds_size);
4858 } else {
4859 ls_hs_rsrc2 = sctx->shader.vs.current->config.rsrc2;
4860
4861 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
4862 ls_hs_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
4863 }
4864
4865 sctx->ls_hs_rsrc2 = ls_hs_rsrc2;
4866 sctx->ls_hs_config =
4867 S_028B58_NUM_PATCHES(sctx->num_patches_per_workgroup) |
4868 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
4869
4870 if (sctx->gfx_level < GFX12)
4871 sctx->ls_hs_config |= S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp);
4872
4873 si_mark_atom_dirty(sctx, &sctx->atoms.s.tess_io_layout);
4874 }
4875
gfx6_emit_tess_io_layout_state(struct si_context * sctx,unsigned index)4876 static void gfx6_emit_tess_io_layout_state(struct si_context *sctx, unsigned index)
4877 {
4878 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
4879
4880 if (!sctx->shader.tes.cso || !sctx->shader.tcs.current)
4881 return;
4882
4883 radeon_begin(cs);
4884 if (sctx->gfx_level >= GFX12) {
4885 gfx12_opt_push_gfx_sh_reg(R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
4886 SI_TRACKED_SPI_SHADER_PGM_RSRC2_HS, sctx->ls_hs_rsrc2);
4887
4888 /* Set userdata SGPRs for merged LS-HS. */
4889 gfx12_opt_push_gfx_sh_reg(R_00B430_SPI_SHADER_USER_DATA_HS_0 +
4890 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4,
4891 SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_LAYOUT,
4892 sctx->tcs_offchip_layout);
4893 gfx12_opt_push_gfx_sh_reg(R_00B430_SPI_SHADER_USER_DATA_HS_0 +
4894 GFX9_SGPR_TCS_OFFCHIP_ADDR * 4,
4895 SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_ADDR,
4896 sctx->tes_offchip_ring_va_sgpr);
4897 } else if (sctx->screen->info.has_set_sh_pairs_packed) {
4898 gfx11_opt_push_gfx_sh_reg(R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
4899 SI_TRACKED_SPI_SHADER_PGM_RSRC2_HS, sctx->ls_hs_rsrc2);
4900
4901 /* Set userdata SGPRs for merged LS-HS. */
4902 gfx11_opt_push_gfx_sh_reg(R_00B430_SPI_SHADER_USER_DATA_HS_0 +
4903 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4,
4904 SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_LAYOUT,
4905 sctx->tcs_offchip_layout);
4906 gfx11_opt_push_gfx_sh_reg(R_00B430_SPI_SHADER_USER_DATA_HS_0 +
4907 GFX9_SGPR_TCS_OFFCHIP_ADDR * 4,
4908 SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_ADDR,
4909 sctx->tes_offchip_ring_va_sgpr);
4910 } else if (sctx->gfx_level >= GFX9) {
4911 radeon_opt_set_sh_reg(R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
4912 SI_TRACKED_SPI_SHADER_PGM_RSRC2_HS, sctx->ls_hs_rsrc2);
4913
4914 /* Set userdata SGPRs for merged LS-HS. */
4915 radeon_opt_set_sh_reg2(R_00B430_SPI_SHADER_USER_DATA_HS_0 +
4916 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4,
4917 SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_LAYOUT,
4918 sctx->tcs_offchip_layout, sctx->tes_offchip_ring_va_sgpr);
4919 } else {
4920 /* Due to a hw bug, RSRC2_LS must be written twice with another
4921 * LS register written in between. */
4922 if (sctx->gfx_level == GFX7 && sctx->family != CHIP_HAWAII)
4923 radeon_set_sh_reg(R_00B52C_SPI_SHADER_PGM_RSRC2_LS, sctx->ls_hs_rsrc2);
4924 radeon_set_sh_reg_seq(R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
4925 radeon_emit(sctx->shader.vs.current->config.rsrc1);
4926 radeon_emit(sctx->ls_hs_rsrc2);
4927
4928 /* Set userdata SGPRs for TCS. */
4929 radeon_opt_set_sh_reg3(R_00B430_SPI_SHADER_USER_DATA_HS_0 +
4930 GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4,
4931 SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_LAYOUT,
4932 sctx->tcs_offchip_layout, sctx->tes_offchip_ring_va_sgpr,
4933 sctx->current_vs_state);
4934 }
4935
4936 /* Set userdata SGPRs for TES. */
4937 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
4938 assert(tes_sh_base);
4939
4940 /* TES (as ES or VS) reuses the BaseVertex and DrawID user SGPRs that are used when
4941 * tessellation is disabled. We can do that because those user SGPRs are only set in LS
4942 * for tessellation and are unused in TES.
4943 */
4944 if (sctx->screen->info.has_set_sh_pairs_packed) {
4945 gfx11_opt_push_gfx_sh_reg(tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4,
4946 SI_TRACKED_SPI_SHADER_USER_DATA_ES__BASE_VERTEX,
4947 sctx->tcs_offchip_layout);
4948 gfx11_opt_push_gfx_sh_reg(tes_sh_base + SI_SGPR_TES_OFFCHIP_ADDR * 4,
4949 SI_TRACKED_SPI_SHADER_USER_DATA_ES__DRAWID,
4950 sctx->tes_offchip_ring_va_sgpr);
4951 } else {
4952 bool has_gs = sctx->ngg || sctx->shader.gs.cso;
4953
4954 radeon_opt_set_sh_reg2(tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4,
4955 has_gs ? SI_TRACKED_SPI_SHADER_USER_DATA_ES__BASE_VERTEX
4956 : SI_TRACKED_SPI_SHADER_USER_DATA_VS__BASE_VERTEX,
4957 sctx->tcs_offchip_layout, sctx->tes_offchip_ring_va_sgpr);
4958 }
4959 radeon_end();
4960
4961 radeon_begin_again(cs);
4962 if (sctx->gfx_level >= GFX7) {
4963 radeon_opt_set_context_reg_idx(R_028B58_VGT_LS_HS_CONFIG,
4964 SI_TRACKED_VGT_LS_HS_CONFIG, 2, sctx->ls_hs_config);
4965 } else {
4966 radeon_opt_set_context_reg(R_028B58_VGT_LS_HS_CONFIG,
4967 SI_TRACKED_VGT_LS_HS_CONFIG, sctx->ls_hs_config);
4968 }
4969 radeon_end_update_context_roll();
4970 }
4971
gfx12_emit_tess_io_layout_state(struct si_context * sctx,unsigned index)4972 static void gfx12_emit_tess_io_layout_state(struct si_context *sctx, unsigned index)
4973 {
4974 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
4975
4976 if (!sctx->shader.tes.cso || !sctx->shader.tcs.current)
4977 return;
4978
4979 gfx12_opt_push_gfx_sh_reg(R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
4980 SI_TRACKED_SPI_SHADER_PGM_RSRC2_HS, sctx->ls_hs_rsrc2);
4981 /* Set userdata SGPRs for merged LS-HS. */
4982 gfx12_opt_push_gfx_sh_reg(R_00B430_SPI_SHADER_USER_DATA_HS_0 +
4983 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4,
4984 SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_LAYOUT,
4985 sctx->tcs_offchip_layout);
4986 gfx12_opt_push_gfx_sh_reg(R_00B430_SPI_SHADER_USER_DATA_HS_0 +
4987 GFX9_SGPR_TCS_OFFCHIP_ADDR * 4,
4988 SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_ADDR,
4989 sctx->tes_offchip_ring_va_sgpr);
4990
4991 /* Set userdata SGPRs for TES. */
4992 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
4993 assert(tes_sh_base);
4994
4995 /* TES (as ES or VS) reuses the BaseVertex and DrawID user SGPRs that are used when
4996 * tessellation is disabled. We can do that because those user SGPRs are only set in LS
4997 * for tessellation and are unused in TES.
4998 */
4999 gfx12_opt_push_gfx_sh_reg(tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4,
5000 SI_TRACKED_SPI_SHADER_USER_DATA_ES__BASE_VERTEX,
5001 sctx->tcs_offchip_layout);
5002 gfx12_opt_push_gfx_sh_reg(tes_sh_base + SI_SGPR_TES_OFFCHIP_ADDR * 4,
5003 SI_TRACKED_SPI_SHADER_USER_DATA_ES__DRAWID,
5004 sctx->tes_offchip_ring_va_sgpr);
5005
5006 radeon_begin(cs);
5007 radeon_opt_set_context_reg_idx(R_028B58_VGT_LS_HS_CONFIG,
5008 SI_TRACKED_VGT_LS_HS_CONFIG, 2, sctx->ls_hs_config);
5009 radeon_end(); /* don't track context rolls on GFX12 */
5010 }
5011
si_init_screen_live_shader_cache(struct si_screen * sscreen)5012 void si_init_screen_live_shader_cache(struct si_screen *sscreen)
5013 {
5014 util_live_shader_cache_init(&sscreen->live_shader_cache, si_create_shader_selector,
5015 si_destroy_shader_selector);
5016 }
5017
5018 template<int NUM_INTERP>
si_emit_spi_map(struct si_context * sctx,unsigned index)5019 static void si_emit_spi_map(struct si_context *sctx, unsigned index)
5020 {
5021 struct si_shader *ps = sctx->shader.ps.current;
5022 struct si_shader *vs = si_get_vs(sctx)->current;
5023 unsigned spi_ps_input_cntl[NUM_INTERP];
5024
5025 STATIC_ASSERT(NUM_INTERP >= 0 && NUM_INTERP <= 32);
5026
5027 if (sctx->gfx_level >= GFX12) {
5028 gfx12_opt_push_gfx_sh_reg(R_00B0C4_SPI_SHADER_GS_OUT_CONFIG_PS,
5029 SI_TRACKED_SPI_SHADER_GS_OUT_CONFIG_PS,
5030 vs->ngg.spi_vs_out_config | ps->ps.spi_gs_out_config_ps);
5031 }
5032
5033 if (!NUM_INTERP)
5034 return;
5035
5036 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
5037
5038 for (unsigned i = 0; i < NUM_INTERP; i++) {
5039 union si_input_info input = ps->info.ps_inputs[i];
5040 unsigned ps_input_cntl = vs->info.vs_output_ps_input_cntl[input.semantic];
5041 bool non_default_val = G_028644_OFFSET(ps_input_cntl) != 0x20;
5042
5043 if (non_default_val) {
5044 if (input.interpolate == INTERP_MODE_FLAT ||
5045 (input.interpolate == INTERP_MODE_COLOR && rs->flatshade))
5046 ps_input_cntl |= S_028644_FLAT_SHADE(1);
5047
5048 if (input.fp16_lo_hi_valid) {
5049 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
5050 S_028644_ATTR0_VALID(1) | /* this must be set if FP16_INTERP_MODE is set */
5051 S_028644_ATTR1_VALID(!!(input.fp16_lo_hi_valid & 0x2));
5052 }
5053 }
5054
5055 if (input.semantic == VARYING_SLOT_PNTC ||
5056 (input.semantic >= VARYING_SLOT_TEX0 && input.semantic <= VARYING_SLOT_TEX7 &&
5057 rs->sprite_coord_enable & (1 << (input.semantic - VARYING_SLOT_TEX0)))) {
5058 /* Overwrite the whole value (except OFFSET) for sprite coordinates. */
5059 ps_input_cntl &= ~C_028644_OFFSET;
5060 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
5061 if (input.fp16_lo_hi_valid & 0x1) {
5062 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
5063 S_028644_ATTR0_VALID(1);
5064 }
5065 }
5066
5067 spi_ps_input_cntl[i] = ps_input_cntl;
5068 }
5069
5070 /* Performance notes:
5071 * Dota 2: Only ~16% of SPI map updates set different values.
5072 * Talos: Only ~9% of SPI map updates set different values.
5073 */
5074 if (sctx->gfx_level >= GFX12) {
5075 radeon_begin(&sctx->gfx_cs);
5076 radeon_opt_set_context_regn(R_028664_SPI_PS_INPUT_CNTL_0, spi_ps_input_cntl,
5077 sctx->tracked_regs.spi_ps_input_cntl, NUM_INTERP);
5078 radeon_end(); /* don't track context rolls on GFX12 */
5079 } else {
5080 radeon_begin(&sctx->gfx_cs);
5081 radeon_opt_set_context_regn(R_028644_SPI_PS_INPUT_CNTL_0, spi_ps_input_cntl,
5082 sctx->tracked_regs.spi_ps_input_cntl, NUM_INTERP);
5083 radeon_end_update_context_roll();
5084 }
5085 }
5086
si_emit_spi_ge_ring_state(struct si_context * sctx,unsigned index)5087 static void si_emit_spi_ge_ring_state(struct si_context *sctx, unsigned index)
5088 {
5089 struct si_screen *sscreen = sctx->screen;
5090
5091 if (sctx->has_tessellation) {
5092 struct pipe_resource *tf_ring =
5093 sctx->ws->cs_is_secure(&sctx->gfx_cs) ? sscreen->tess_rings_tmz : sscreen->tess_rings;
5094 uint64_t factor_va = si_resource(tf_ring)->gpu_address +
5095 sscreen->hs.tess_offchip_ring_size;
5096
5097 unsigned tf_ring_size_field = sscreen->hs.tess_factor_ring_size / 4;
5098 if (sctx->gfx_level >= GFX11)
5099 tf_ring_size_field /= sscreen->info.max_se;
5100
5101 assert((tf_ring_size_field & C_030938_SIZE) == 0);
5102
5103 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(tf_ring),
5104 RADEON_USAGE_READWRITE | RADEON_PRIO_SHADER_RINGS);
5105
5106 radeon_begin(&sctx->gfx_cs);
5107 /* Required before writing tessellation config registers. */
5108 radeon_event_write(V_028A90_VS_PARTIAL_FLUSH);
5109 radeon_event_write(V_028A90_VGT_FLUSH);
5110
5111 if (sctx->gfx_level >= GFX7) {
5112 radeon_set_uconfig_reg_seq(R_030938_VGT_TF_RING_SIZE, 3);
5113 radeon_emit(S_030938_SIZE(tf_ring_size_field)); /* R_030938_VGT_TF_RING_SIZE */
5114 radeon_emit(sscreen->hs.hs_offchip_param); /* R_03093C_VGT_HS_OFFCHIP_PARAM */
5115 radeon_emit(factor_va >> 8); /* R_030940_VGT_TF_MEMORY_BASE */
5116
5117 if (sctx->gfx_level >= GFX12)
5118 radeon_set_uconfig_reg(R_03099C_VGT_TF_MEMORY_BASE_HI, S_03099C_BASE_HI(factor_va >> 40));
5119 else if (sctx->gfx_level >= GFX10)
5120 radeon_set_uconfig_reg(R_030984_VGT_TF_MEMORY_BASE_HI, S_030984_BASE_HI(factor_va >> 40));
5121 else if (sctx->gfx_level == GFX9)
5122 radeon_set_uconfig_reg(R_030944_VGT_TF_MEMORY_BASE_HI, S_030944_BASE_HI(factor_va >> 40));
5123 } else {
5124 radeon_set_config_reg(R_008988_VGT_TF_RING_SIZE, S_008988_SIZE(tf_ring_size_field));
5125 radeon_set_config_reg(R_0089B8_VGT_TF_MEMORY_BASE, factor_va >> 8);
5126 radeon_set_config_reg(R_0089B0_VGT_HS_OFFCHIP_PARAM, sscreen->hs.hs_offchip_param);
5127 }
5128 radeon_end();
5129 }
5130
5131 if (sctx->gfx_level >= GFX11) {
5132 /* We must wait for idle using an EOP event before changing the attribute ring registers.
5133 * Use the bottom-of-pipe EOP event, but use the PWS TS counter instead of the counter
5134 * in memory.
5135 */
5136 si_cp_release_acquire_mem_pws(sctx, &sctx->gfx_cs, V_028A90_BOTTOM_OF_PIPE_TS, 0,
5137 V_580_CP_ME, 0);
5138
5139 uint64_t attr_address = sscreen->attribute_pos_prim_ring->gpu_address;
5140 assert((attr_address >> 32) == sscreen->info.address32_hi);
5141
5142 radeon_begin(&sctx->gfx_cs);
5143 radeon_set_uconfig_reg_seq(R_031110_SPI_GS_THROTTLE_CNTL1, 4);
5144 radeon_emit(0x12355123); /* SPI_GS_THROTTLE_CNTL1 */
5145 radeon_emit(0x1544D); /* SPI_GS_THROTTLE_CNTL2 */
5146 radeon_emit(attr_address >> 16); /* SPI_ATTRIBUTE_RING_BASE */
5147 radeon_emit(S_03111C_MEM_SIZE((sscreen->info.attribute_ring_size_per_se >> 16) - 1) |
5148 S_03111C_BIG_PAGE(sscreen->info.discardable_allows_big_page) |
5149 S_03111C_L1_POLICY(1)); /* SPI_ATTRIBUTE_RING_SIZE */
5150
5151 if (sctx->gfx_level >= GFX12) {
5152 uint64_t pos_address = attr_address + sscreen->info.pos_ring_offset;
5153 uint64_t prim_address = attr_address + sscreen->info.prim_ring_offset;
5154
5155 /* When one of these 4 registers is updated, all 4 must be updated. */
5156 radeon_set_uconfig_reg_seq(R_0309A0_GE_POS_RING_BASE, 4);
5157 radeon_emit(pos_address >> 16); /* R_0309A0_GE_POS_RING_BASE */
5158 radeon_emit(S_0309A4_MEM_SIZE(sscreen->info.pos_ring_size_per_se >> 5)); /* R_0309A4_GE_POS_RING_SIZE */
5159 radeon_emit(prim_address >> 16); /* R_0309A8_GE_PRIM_RING_BASE */
5160 radeon_emit(S_0309AC_MEM_SIZE(sscreen->info.prim_ring_size_per_se >> 5) |
5161 S_0309AC_SCOPE(gfx12_scope_device) |
5162 S_0309AC_PAF_TEMPORAL(gfx12_store_high_temporal_stay_dirty) |
5163 S_0309AC_PAB_TEMPORAL(gfx12_load_last_use_discard) |
5164 S_0309AC_SPEC_DATA_READ(gfx12_spec_read_auto) |
5165 S_0309AC_FORCE_SE_SCOPE(1) |
5166 S_0309AC_PAB_NOFILL(1)); /* R_0309AC_GE_PRIM_RING_SIZE */
5167 }
5168 radeon_end();
5169 }
5170 }
5171
si_init_shader_functions(struct si_context * sctx)5172 void si_init_shader_functions(struct si_context *sctx)
5173 {
5174 sctx->atoms.s.vgt_pipeline_state.emit = si_emit_vgt_pipeline_state;
5175 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
5176 sctx->atoms.s.spi_ge_ring_state.emit = si_emit_spi_ge_ring_state;
5177
5178 if (sctx->gfx_level >= GFX12)
5179 sctx->atoms.s.tess_io_layout.emit = gfx12_emit_tess_io_layout_state;
5180 else
5181 sctx->atoms.s.tess_io_layout.emit = gfx6_emit_tess_io_layout_state;
5182
5183 sctx->b.create_vs_state = si_create_shader;
5184 sctx->b.create_tcs_state = si_create_shader;
5185 sctx->b.create_tes_state = si_create_shader;
5186 sctx->b.create_gs_state = si_create_shader;
5187 sctx->b.create_fs_state = si_create_shader;
5188
5189 sctx->b.bind_vs_state = si_bind_vs_shader;
5190 sctx->b.bind_tcs_state = si_bind_tcs_shader;
5191 sctx->b.bind_tes_state = si_bind_tes_shader;
5192 sctx->b.bind_gs_state = si_bind_gs_shader;
5193 sctx->b.bind_fs_state = si_bind_ps_shader;
5194
5195 sctx->b.delete_vs_state = si_delete_shader_selector;
5196 sctx->b.delete_tcs_state = si_delete_shader_selector;
5197 sctx->b.delete_tes_state = si_delete_shader_selector;
5198 sctx->b.delete_gs_state = si_delete_shader_selector;
5199 sctx->b.delete_fs_state = si_delete_shader_selector;
5200
5201 sctx->b.set_patch_vertices = si_set_patch_vertices;
5202
5203 /* This unrolls the loops in si_emit_spi_map and inlines memcmp and memcpys.
5204 * It improves performance for viewperf/snx.
5205 */
5206 sctx->emit_spi_map[0] = si_emit_spi_map<0>;
5207 sctx->emit_spi_map[1] = si_emit_spi_map<1>;
5208 sctx->emit_spi_map[2] = si_emit_spi_map<2>;
5209 sctx->emit_spi_map[3] = si_emit_spi_map<3>;
5210 sctx->emit_spi_map[4] = si_emit_spi_map<4>;
5211 sctx->emit_spi_map[5] = si_emit_spi_map<5>;
5212 sctx->emit_spi_map[6] = si_emit_spi_map<6>;
5213 sctx->emit_spi_map[7] = si_emit_spi_map<7>;
5214 sctx->emit_spi_map[8] = si_emit_spi_map<8>;
5215 sctx->emit_spi_map[9] = si_emit_spi_map<9>;
5216 sctx->emit_spi_map[10] = si_emit_spi_map<10>;
5217 sctx->emit_spi_map[11] = si_emit_spi_map<11>;
5218 sctx->emit_spi_map[12] = si_emit_spi_map<12>;
5219 sctx->emit_spi_map[13] = si_emit_spi_map<13>;
5220 sctx->emit_spi_map[14] = si_emit_spi_map<14>;
5221 sctx->emit_spi_map[15] = si_emit_spi_map<15>;
5222 sctx->emit_spi_map[16] = si_emit_spi_map<16>;
5223 sctx->emit_spi_map[17] = si_emit_spi_map<17>;
5224 sctx->emit_spi_map[18] = si_emit_spi_map<18>;
5225 sctx->emit_spi_map[19] = si_emit_spi_map<19>;
5226 sctx->emit_spi_map[20] = si_emit_spi_map<20>;
5227 sctx->emit_spi_map[21] = si_emit_spi_map<21>;
5228 sctx->emit_spi_map[22] = si_emit_spi_map<22>;
5229 sctx->emit_spi_map[23] = si_emit_spi_map<23>;
5230 sctx->emit_spi_map[24] = si_emit_spi_map<24>;
5231 sctx->emit_spi_map[25] = si_emit_spi_map<25>;
5232 sctx->emit_spi_map[26] = si_emit_spi_map<26>;
5233 sctx->emit_spi_map[27] = si_emit_spi_map<27>;
5234 sctx->emit_spi_map[28] = si_emit_spi_map<28>;
5235 sctx->emit_spi_map[29] = si_emit_spi_map<29>;
5236 sctx->emit_spi_map[30] = si_emit_spi_map<30>;
5237 sctx->emit_spi_map[31] = si_emit_spi_map<31>;
5238 sctx->emit_spi_map[32] = si_emit_spi_map<32>;
5239 }
5240