1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
7 #include "si_build_pm4.h"
8 #include "si_query.h"
9 #include "si_shader_internal.h"
10 #include "sid.h"
11 #include "util/fast_idiv_by_const.h"
12 #include "util/format/u_format.h"
13 #include "util/format/u_format_s3tc.h"
14 #include "util/hash_table.h"
15 #include "util/u_dual_blend.h"
16 #include "util/u_helpers.h"
17 #include "util/u_memory.h"
18 #include "util/u_resource.h"
19 #include "util/u_upload_mgr.h"
20 #include "util/u_blend.h"
21
22 #include "ac_cmdbuf.h"
23 #include "ac_descriptors.h"
24 #include "ac_formats.h"
25 #include "gfx10_format_table.h"
26
27 /* 12.4 fixed-point */
si_pack_float_12p4(float x)28 static unsigned si_pack_float_12p4(float x)
29 {
30 return x <= 0 ? 0 : x >= 4096 ? 0xffff : x * 16;
31 }
32
33 /*
34 * Inferred framebuffer and blender state.
35 *
36 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
37 * if there is not enough PS outputs.
38 */
si_emit_cb_render_state(struct si_context * sctx,unsigned index)39 static void si_emit_cb_render_state(struct si_context *sctx, unsigned index)
40 {
41 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
42 struct si_state_blend *blend = sctx->queued.named.blend;
43 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
44 * but you never know. */
45 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit & blend->cb_target_mask;
46 unsigned i;
47
48 /* Avoid a hang that happens when dual source blending is enabled
49 * but there is not enough color outputs. This is undefined behavior,
50 * so disable color writes completely.
51 *
52 * Reproducible with Unigine Heaven 4.0 and drirc missing.
53 */
54 if (blend->dual_src_blend && sctx->shader.ps.cso &&
55 (sctx->shader.ps.cso->info.colors_written & 0x3) != 0x3)
56 cb_target_mask = 0;
57
58 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
59 * I think we don't have to do anything between IBs.
60 */
61 if (sctx->screen->dpbb_allowed && sctx->last_cb_target_mask != cb_target_mask &&
62 sctx->screen->pbb_context_states_per_bin > 1) {
63 sctx->last_cb_target_mask = cb_target_mask;
64
65 radeon_begin(cs);
66 radeon_event_write(V_028A90_BREAK_BATCH);
67 radeon_end();
68 }
69
70 uint32_t cb_dcc_control = 0;
71
72 if (sctx->gfx_level >= GFX8 && sctx->gfx_level < GFX12) {
73 /* DCC MSAA workaround.
74 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
75 * COMBINER_DISABLE, but that would be more complicated.
76 */
77 bool oc_disable =
78 blend->dcc_msaa_corruption_4bit & cb_target_mask && sctx->framebuffer.nr_samples >= 2;
79
80 if (sctx->gfx_level >= GFX11) {
81 cb_dcc_control =
82 S_028424_SAMPLE_MASK_TRACKER_DISABLE(oc_disable) |
83 S_028424_SAMPLE_MASK_TRACKER_WATERMARK(sctx->screen->info.has_dedicated_vram ? 0 : 15);
84 } else {
85 cb_dcc_control =
86 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx->gfx_level <= GFX9) |
87 S_028424_OVERWRITE_COMBINER_WATERMARK(sctx->gfx_level >= GFX10 ? 6 : 4) |
88 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
89 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->gfx_level < GFX11 &&
90 sctx->screen->info.has_dcc_constant_encode);
91 }
92 }
93
94 uint32_t sx_ps_downconvert = 0;
95 uint32_t sx_blend_opt_epsilon = 0;
96 uint32_t sx_blend_opt_control = 0;
97
98 /* RB+ register settings. */
99 if (sctx->screen->info.rbplus_allowed) {
100 unsigned spi_shader_col_format =
101 sctx->shader.ps.cso ? sctx->shader.ps.current->key.ps.part.epilog.spi_shader_col_format
102 : 0;
103 unsigned num_cbufs = util_last_bit(sctx->framebuffer.colorbuf_enabled_4bit &
104 blend->cb_target_enabled_4bit) / 4;
105
106 for (i = 0; i < num_cbufs; i++) {
107 struct si_surface *surf = (struct si_surface *)sctx->framebuffer.state.cbufs[i];
108 unsigned format, swap, spi_format, colormask;
109 bool has_alpha, has_rgb;
110
111 if (!surf) {
112 /* If the color buffer is not set, the driver sets 32_R
113 * as the SPI color format, because the hw doesn't allow
114 * holes between color outputs, so also set this to
115 * enable RB+.
116 */
117 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
118 continue;
119 }
120
121 format = sctx->gfx_level >= GFX11 ? G_028C70_FORMAT_GFX11(surf->cb.cb_color_info):
122 G_028C70_FORMAT_GFX6(surf->cb.cb_color_info);
123 swap = G_028C70_COMP_SWAP(surf->cb.cb_color_info);
124 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
125 colormask = (cb_target_mask >> (i * 4)) & 0xf;
126
127 /* Set if RGB and A are present. */
128 has_alpha = !(sctx->gfx_level >= GFX11 ? G_028C74_FORCE_DST_ALPHA_1_GFX11(surf->cb.cb_color_attrib):
129 G_028C74_FORCE_DST_ALPHA_1_GFX6(surf->cb.cb_color_attrib));
130
131 if (format == V_028C70_COLOR_8 || format == V_028C70_COLOR_16 ||
132 format == V_028C70_COLOR_32)
133 has_rgb = !has_alpha;
134 else
135 has_rgb = true;
136
137 /* Check the colormask and export format. */
138 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
139 has_rgb = false;
140 if (!(colormask & PIPE_MASK_A))
141 has_alpha = false;
142
143 if (spi_format == V_028714_SPI_SHADER_ZERO) {
144 has_rgb = false;
145 has_alpha = false;
146 }
147
148 /* Disable value checking for disabled channels. */
149 if (!has_rgb)
150 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
151 if (!has_alpha)
152 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
153
154 /* Enable down-conversion for 32bpp and smaller formats. */
155 switch (format) {
156 case V_028C70_COLOR_8:
157 case V_028C70_COLOR_8_8:
158 case V_028C70_COLOR_8_8_8_8:
159 /* For 1 and 2-channel formats, use the superset thereof. */
160 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
161 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
162 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
163 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
164 if (G_028C70_NUMBER_TYPE(surf->cb.cb_color_info) != V_028C70_NUMBER_SRGB)
165 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT_0_5 << (i * 4);
166 }
167 break;
168
169 case V_028C70_COLOR_5_6_5:
170 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
171 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
172 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT_0_5 << (i * 4);
173 }
174 break;
175
176 case V_028C70_COLOR_1_5_5_5:
177 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
178 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
179 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT_0_5 << (i * 4);
180 }
181 break;
182
183 case V_028C70_COLOR_4_4_4_4:
184 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
186 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT_0_5 << (i * 4);
187 }
188 break;
189
190 case V_028C70_COLOR_32:
191 if (swap == V_028C70_SWAP_STD && spi_format == V_028714_SPI_SHADER_32_R)
192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
193 else if (swap == V_028C70_SWAP_ALT_REV && spi_format == V_028714_SPI_SHADER_32_AR)
194 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
195 break;
196
197 case V_028C70_COLOR_16:
198 case V_028C70_COLOR_16_16:
199 /* For 1-channel formats, use the superset thereof. */
200 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
201 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
202 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
203 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
204 if (swap == V_028C70_SWAP_STD || swap == V_028C70_SWAP_STD_REV)
205 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
206 else
207 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_10_11_11:
212 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR)
213 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
214 break;
215
216 case V_028C70_COLOR_2_10_10_10:
217 case V_028C70_COLOR_10_10_10_2:
218 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
219 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
220 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT_0_5 << (i * 4);
221 }
222 break;
223
224 case V_028C70_COLOR_5_9_9_9:
225 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR)
226 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_9_9_9_E5 << (i * 4);
227 break;
228 }
229 }
230
231 /* If there are no color outputs, the first color export is
232 * always enabled as 32_R, so also set this to enable RB+.
233 */
234 if (!sx_ps_downconvert)
235 sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_R;
236 }
237
238 if (sctx->gfx_level >= GFX12) {
239 /* GFX12 doesn't have CB_FDCC_CONTROL. */
240 assert(cb_dcc_control == 0);
241
242 radeon_begin(cs);
243 gfx12_begin_context_regs();
244 gfx12_opt_set_context_reg(R_028850_CB_TARGET_MASK, SI_TRACKED_CB_TARGET_MASK,
245 cb_target_mask);
246 gfx12_opt_set_context_reg(R_028754_SX_PS_DOWNCONVERT, SI_TRACKED_SX_PS_DOWNCONVERT,
247 sx_ps_downconvert);
248 gfx12_opt_set_context_reg(R_028758_SX_BLEND_OPT_EPSILON, SI_TRACKED_SX_BLEND_OPT_EPSILON,
249 sx_blend_opt_epsilon);
250 gfx12_opt_set_context_reg(R_02875C_SX_BLEND_OPT_CONTROL, SI_TRACKED_SX_BLEND_OPT_CONTROL,
251 sx_blend_opt_control);
252 gfx12_end_context_regs();
253 radeon_end(); /* don't track context rolls on GFX12 */
254 } else if (sctx->screen->info.has_set_context_pairs_packed) {
255 radeon_begin(cs);
256 gfx11_begin_packed_context_regs();
257 gfx11_opt_set_context_reg(R_028238_CB_TARGET_MASK, SI_TRACKED_CB_TARGET_MASK,
258 cb_target_mask);
259 gfx11_opt_set_context_reg(R_028424_CB_DCC_CONTROL, SI_TRACKED_CB_DCC_CONTROL,
260 cb_dcc_control);
261 gfx11_opt_set_context_reg(R_028754_SX_PS_DOWNCONVERT, SI_TRACKED_SX_PS_DOWNCONVERT,
262 sx_ps_downconvert);
263 gfx11_opt_set_context_reg(R_028758_SX_BLEND_OPT_EPSILON, SI_TRACKED_SX_BLEND_OPT_EPSILON,
264 sx_blend_opt_epsilon);
265 gfx11_opt_set_context_reg(R_02875C_SX_BLEND_OPT_CONTROL, SI_TRACKED_SX_BLEND_OPT_CONTROL,
266 sx_blend_opt_control);
267 gfx11_end_packed_context_regs();
268 radeon_end(); /* don't track context rolls on GFX11 */
269 } else {
270 radeon_begin(cs);
271 radeon_opt_set_context_reg(R_028238_CB_TARGET_MASK, SI_TRACKED_CB_TARGET_MASK,
272 cb_target_mask);
273 if (sctx->gfx_level >= GFX8) {
274 radeon_opt_set_context_reg(R_028424_CB_DCC_CONTROL, SI_TRACKED_CB_DCC_CONTROL,
275 cb_dcc_control);
276 }
277 if (sctx->screen->info.rbplus_allowed) {
278 radeon_opt_set_context_reg3(R_028754_SX_PS_DOWNCONVERT, SI_TRACKED_SX_PS_DOWNCONVERT,
279 sx_ps_downconvert, sx_blend_opt_epsilon, sx_blend_opt_control);
280 }
281 radeon_end_update_context_roll();
282 }
283 }
284
285 /*
286 * Blender functions
287 */
288
si_translate_blend_function(int blend_func)289 static uint32_t si_translate_blend_function(int blend_func)
290 {
291 switch (blend_func) {
292 case PIPE_BLEND_ADD:
293 return V_028780_COMB_DST_PLUS_SRC;
294 case PIPE_BLEND_SUBTRACT:
295 return V_028780_COMB_SRC_MINUS_DST;
296 case PIPE_BLEND_REVERSE_SUBTRACT:
297 return V_028780_COMB_DST_MINUS_SRC;
298 case PIPE_BLEND_MIN:
299 return V_028780_COMB_MIN_DST_SRC;
300 case PIPE_BLEND_MAX:
301 return V_028780_COMB_MAX_DST_SRC;
302 default:
303 PRINT_ERR("Unknown blend function %d\n", blend_func);
304 assert(0);
305 break;
306 }
307 return 0;
308 }
309
si_translate_blend_factor(enum amd_gfx_level gfx_level,int blend_fact)310 static uint32_t si_translate_blend_factor(enum amd_gfx_level gfx_level, int blend_fact)
311 {
312 switch (blend_fact) {
313 case PIPE_BLENDFACTOR_ONE:
314 return V_028780_BLEND_ONE;
315 case PIPE_BLENDFACTOR_SRC_COLOR:
316 return V_028780_BLEND_SRC_COLOR;
317 case PIPE_BLENDFACTOR_SRC_ALPHA:
318 return V_028780_BLEND_SRC_ALPHA;
319 case PIPE_BLENDFACTOR_DST_ALPHA:
320 return V_028780_BLEND_DST_ALPHA;
321 case PIPE_BLENDFACTOR_DST_COLOR:
322 return V_028780_BLEND_DST_COLOR;
323 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
324 return V_028780_BLEND_SRC_ALPHA_SATURATE;
325 case PIPE_BLENDFACTOR_CONST_COLOR:
326 return gfx_level >= GFX11 ? V_028780_BLEND_CONSTANT_COLOR_GFX11:
327 V_028780_BLEND_CONSTANT_COLOR_GFX6;
328 case PIPE_BLENDFACTOR_CONST_ALPHA:
329 return gfx_level >= GFX11 ? V_028780_BLEND_CONSTANT_ALPHA_GFX11 :
330 V_028780_BLEND_CONSTANT_ALPHA_GFX6;
331 case PIPE_BLENDFACTOR_ZERO:
332 return V_028780_BLEND_ZERO;
333 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
334 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
335 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
336 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
337 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
338 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
339 case PIPE_BLENDFACTOR_INV_DST_COLOR:
340 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
341 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
342 return gfx_level >= GFX11 ? V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR_GFX11:
343 V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR_GFX6;
344 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
345 return gfx_level >= GFX11 ? V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA_GFX11:
346 V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA_GFX6;
347 case PIPE_BLENDFACTOR_SRC1_COLOR:
348 return gfx_level >= GFX11 ? V_028780_BLEND_SRC1_COLOR_GFX11:
349 V_028780_BLEND_SRC1_COLOR_GFX6;
350 case PIPE_BLENDFACTOR_SRC1_ALPHA:
351 return gfx_level >= GFX11 ? V_028780_BLEND_SRC1_ALPHA_GFX11:
352 V_028780_BLEND_SRC1_ALPHA_GFX6;
353 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
354 return gfx_level >= GFX11 ? V_028780_BLEND_INV_SRC1_COLOR_GFX11:
355 V_028780_BLEND_INV_SRC1_COLOR_GFX6;
356 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
357 return gfx_level >= GFX11 ? V_028780_BLEND_INV_SRC1_ALPHA_GFX11:
358 V_028780_BLEND_INV_SRC1_ALPHA_GFX6;
359 default:
360 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
361 assert(0);
362 break;
363 }
364 return 0;
365 }
366
si_translate_blend_opt_function(int blend_func)367 static uint32_t si_translate_blend_opt_function(int blend_func)
368 {
369 switch (blend_func) {
370 case PIPE_BLEND_ADD:
371 return V_028760_OPT_COMB_ADD;
372 case PIPE_BLEND_SUBTRACT:
373 return V_028760_OPT_COMB_SUBTRACT;
374 case PIPE_BLEND_REVERSE_SUBTRACT:
375 return V_028760_OPT_COMB_REVSUBTRACT;
376 case PIPE_BLEND_MIN:
377 return V_028760_OPT_COMB_MIN;
378 case PIPE_BLEND_MAX:
379 return V_028760_OPT_COMB_MAX;
380 default:
381 return V_028760_OPT_COMB_BLEND_DISABLED;
382 }
383 }
384
si_translate_blend_opt_factor(int blend_fact,bool is_alpha)385 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
386 {
387 switch (blend_fact) {
388 case PIPE_BLENDFACTOR_ZERO:
389 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
390 case PIPE_BLENDFACTOR_ONE:
391 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
392 case PIPE_BLENDFACTOR_SRC_COLOR:
393 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
394 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
395 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
396 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
397 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
398 case PIPE_BLENDFACTOR_SRC_ALPHA:
399 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
400 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
401 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
402 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
403 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
404 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
405 default:
406 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
407 }
408 }
409
si_blend_check_commutativity(struct si_screen * sscreen,struct si_state_blend * blend,enum pipe_blend_func func,enum pipe_blendfactor src,enum pipe_blendfactor dst,unsigned chanmask)410 static void si_blend_check_commutativity(struct si_screen *sscreen, struct si_state_blend *blend,
411 enum pipe_blend_func func, enum pipe_blendfactor src,
412 enum pipe_blendfactor dst, unsigned chanmask)
413 {
414 /* Src factor is allowed when it does not depend on Dst */
415 static const uint32_t src_allowed =
416 (1u << PIPE_BLENDFACTOR_ONE) | (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
417 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) | (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
418 (1u << PIPE_BLENDFACTOR_CONST_COLOR) | (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
419 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) | (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
420 (1u << PIPE_BLENDFACTOR_ZERO) | (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
421 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) | (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
422 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) | (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
423 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
424
425 if (dst == PIPE_BLENDFACTOR_ONE && (src_allowed & (1u << src)) &&
426 (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN))
427 blend->commutative_4bit |= chanmask;
428 }
429
430 /**
431 * Get rid of DST in the blend factors by commuting the operands:
432 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
433 */
si_blend_remove_dst(unsigned * func,unsigned * src_factor,unsigned * dst_factor,unsigned expected_dst,unsigned replacement_src)434 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor, unsigned *dst_factor,
435 unsigned expected_dst, unsigned replacement_src)
436 {
437 if (*src_factor == expected_dst && *dst_factor == PIPE_BLENDFACTOR_ZERO) {
438 *src_factor = PIPE_BLENDFACTOR_ZERO;
439 *dst_factor = replacement_src;
440
441 /* Commuting the operands requires reversing subtractions. */
442 if (*func == PIPE_BLEND_SUBTRACT)
443 *func = PIPE_BLEND_REVERSE_SUBTRACT;
444 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
445 *func = PIPE_BLEND_SUBTRACT;
446 }
447 }
448
si_create_blend_state_mode(struct pipe_context * ctx,const struct pipe_blend_state * state,unsigned mode)449 static void *si_create_blend_state_mode(struct pipe_context *ctx,
450 const struct pipe_blend_state *state, unsigned mode)
451 {
452 struct si_context *sctx = (struct si_context *)ctx;
453 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
454 struct si_pm4_state *pm4 = &blend->pm4;
455 uint32_t sx_mrt_blend_opt[8] = {0};
456 uint32_t color_control = 0;
457 bool logicop_enable = state->logicop_enable && state->logicop_func != PIPE_LOGICOP_COPY;
458
459 if (!blend)
460 return NULL;
461
462 si_pm4_clear_state(pm4, sctx->screen, false);
463
464 blend->alpha_to_coverage = state->alpha_to_coverage;
465 blend->alpha_to_one = state->alpha_to_one;
466 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
467 blend->logicop_enable = logicop_enable;
468 blend->allows_noop_optimization =
469 state->rt[0].rgb_func == PIPE_BLEND_ADD &&
470 state->rt[0].alpha_func == PIPE_BLEND_ADD &&
471 state->rt[0].rgb_src_factor == PIPE_BLENDFACTOR_DST_COLOR &&
472 state->rt[0].alpha_src_factor == PIPE_BLENDFACTOR_DST_COLOR &&
473 state->rt[0].rgb_dst_factor == PIPE_BLENDFACTOR_ZERO &&
474 state->rt[0].alpha_dst_factor == PIPE_BLENDFACTOR_ZERO &&
475 mode == V_028808_CB_NORMAL;
476
477 unsigned num_shader_outputs = state->max_rt + 1; /* estimate */
478 if (blend->dual_src_blend)
479 num_shader_outputs = MAX2(num_shader_outputs, 2);
480
481 if (logicop_enable) {
482 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
483 } else {
484 color_control |= S_028808_ROP3(0xcc);
485 }
486
487 unsigned db_alpha_to_mask;
488 if (state->alpha_to_coverage && state->alpha_to_coverage_dither) {
489 db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
490 S_028B70_ALPHA_TO_MASK_OFFSET0(3) | S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
491 S_028B70_ALPHA_TO_MASK_OFFSET2(0) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
492 S_028B70_OFFSET_ROUND(1);
493 } else {
494 db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
495 S_028B70_ALPHA_TO_MASK_OFFSET0(2) | S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
496 S_028B70_ALPHA_TO_MASK_OFFSET2(2) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
497 S_028B70_OFFSET_ROUND(0);
498 }
499
500 if (sctx->gfx_level >= GFX12)
501 ac_pm4_set_reg(&pm4->base, R_02807C_DB_ALPHA_TO_MASK, db_alpha_to_mask);
502 else
503 ac_pm4_set_reg(&pm4->base, R_028B70_DB_ALPHA_TO_MASK, db_alpha_to_mask);
504
505 blend->cb_target_mask = 0;
506 blend->cb_target_enabled_4bit = 0;
507
508 unsigned last_blend_cntl;
509
510 for (int i = 0; i < num_shader_outputs; i++) {
511 /* state->rt entries > 0 only written if independent blending */
512 const int j = state->independent_blend_enable ? i : 0;
513
514 unsigned eqRGB = state->rt[j].rgb_func;
515 unsigned srcRGB = state->rt[j].rgb_src_factor;
516 unsigned dstRGB = state->rt[j].rgb_dst_factor;
517 unsigned eqA = state->rt[j].alpha_func;
518 unsigned srcA = state->rt[j].alpha_src_factor;
519 unsigned dstA = state->rt[j].alpha_dst_factor;
520
521 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
522 unsigned blend_cntl = 0;
523
524 sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
525 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
526
527 /* Only set dual source blending for MRT0 to avoid a hang. */
528 if (i >= 1 && blend->dual_src_blend) {
529 if (i == 1) {
530 if (sctx->gfx_level >= GFX11)
531 blend_cntl = last_blend_cntl;
532 else
533 blend_cntl = S_028780_ENABLE(1);
534 }
535
536 ac_pm4_set_reg(&pm4->base, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
537 continue;
538 }
539
540 /* Only addition and subtraction equations are supported with
541 * dual source blending.
542 */
543 if (blend->dual_src_blend && (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
544 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
545 assert(!"Unsupported equation for dual source blending");
546 ac_pm4_set_reg(&pm4->base, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
547 continue;
548 }
549
550 /* cb_render_state will disable unused ones */
551 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
552 if (state->rt[j].colormask)
553 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
554
555 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
556 ac_pm4_set_reg(&pm4->base, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
557 continue;
558 }
559
560 si_blend_check_commutativity(sctx->screen, blend, eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
561 si_blend_check_commutativity(sctx->screen, blend, eqA, srcA, dstA, 0x8 << (4 * i));
562
563 /* Blending optimizations for RB+.
564 * These transformations don't change the behavior.
565 *
566 * First, get rid of DST in the blend factors:
567 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
568 */
569 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB, PIPE_BLENDFACTOR_DST_COLOR,
570 PIPE_BLENDFACTOR_SRC_COLOR);
571 si_blend_remove_dst(&eqA, &srcA, &dstA, PIPE_BLENDFACTOR_DST_COLOR,
572 PIPE_BLENDFACTOR_SRC_COLOR);
573 si_blend_remove_dst(&eqA, &srcA, &dstA, PIPE_BLENDFACTOR_DST_ALPHA,
574 PIPE_BLENDFACTOR_SRC_ALPHA);
575
576 /* Look up the ideal settings from tables. */
577 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
578 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
579 srcA_opt = si_translate_blend_opt_factor(srcA, true);
580 dstA_opt = si_translate_blend_opt_factor(dstA, true);
581
582 /* Handle interdependencies. */
583 if (util_blend_factor_uses_dest(srcRGB, false))
584 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
585 if (util_blend_factor_uses_dest(srcA, false))
586 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
587
588 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
589 (dstRGB == PIPE_BLENDFACTOR_ZERO || dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
590 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
591 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
592
593 /* Set the final value. */
594 sx_mrt_blend_opt[i] = S_028760_COLOR_SRC_OPT(srcRGB_opt) |
595 S_028760_COLOR_DST_OPT(dstRGB_opt) |
596 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
597 S_028760_ALPHA_SRC_OPT(srcA_opt) | S_028760_ALPHA_DST_OPT(dstA_opt) |
598 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
599
600 /* Alpha-to-coverage with blending enabled, depth writes enabled, and having no MRTZ export
601 * should disable SX blend optimizations.
602 *
603 * TODO: Add a piglit test for this. It should fail on gfx11 without this.
604 */
605 if (sctx->gfx_level >= GFX11 && state->alpha_to_coverage && i == 0) {
606 sx_mrt_blend_opt[0] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
607 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
608 }
609
610 /* Set blend state. */
611 blend_cntl |= S_028780_ENABLE(1);
612 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
613 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(sctx->gfx_level, srcRGB));
614 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(sctx->gfx_level, dstRGB));
615
616 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
617 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
618 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
619 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(sctx->gfx_level, srcA));
620 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(sctx->gfx_level, dstA));
621 }
622 ac_pm4_set_reg(&pm4->base, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
623 last_blend_cntl = blend_cntl;
624
625 blend->blend_enable_4bit |= 0xfu << (i * 4);
626
627 if (sctx->gfx_level >= GFX8 && sctx->gfx_level <= GFX10)
628 blend->dcc_msaa_corruption_4bit |= 0xfu << (i * 4);
629
630 /* This is only important for formats without alpha. */
631 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
632 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
633 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
634 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
635 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
636 }
637
638 if (sctx->gfx_level >= GFX8 && sctx->gfx_level <= GFX10 && logicop_enable)
639 blend->dcc_msaa_corruption_4bit |= blend->cb_target_enabled_4bit;
640
641 if (blend->cb_target_mask) {
642 color_control |= S_028808_MODE(mode);
643 } else {
644 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
645 }
646
647 if (sctx->screen->info.rbplus_allowed) {
648 /* Disable RB+ blend optimizations for dual source blending.
649 * Vulkan does this.
650 */
651 if (blend->dual_src_blend) {
652 for (int i = 0; i < num_shader_outputs; i++) {
653 sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
654 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
655 }
656 }
657
658 for (int i = 0; i < num_shader_outputs; i++)
659 ac_pm4_set_reg(&pm4->base, R_028760_SX_MRT0_BLEND_OPT + i * 4, sx_mrt_blend_opt[i]);
660
661 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
662 if (blend->dual_src_blend || logicop_enable || mode == V_028808_CB_RESOLVE ||
663 /* Disabling RB+ improves blending performance in synthetic tests on GFX11. */
664 (sctx->gfx_level == GFX11 && blend->blend_enable_4bit))
665 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
666 }
667
668 if (sctx->gfx_level >= GFX12)
669 ac_pm4_set_reg(&pm4->base, R_028858_CB_COLOR_CONTROL, color_control);
670 else
671 ac_pm4_set_reg(&pm4->base, R_028808_CB_COLOR_CONTROL, color_control);
672
673 ac_pm4_finalize(&pm4->base);
674 return blend;
675 }
676
si_create_blend_state(struct pipe_context * ctx,const struct pipe_blend_state * state)677 static void *si_create_blend_state(struct pipe_context *ctx, const struct pipe_blend_state *state)
678 {
679 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
680 }
681
si_check_blend_dst_sampler_noop(struct si_context * sctx)682 static bool si_check_blend_dst_sampler_noop(struct si_context *sctx)
683 {
684 if (sctx->framebuffer.state.nr_cbufs == 1) {
685 struct si_shader_selector *sel = sctx->shader.ps.cso;
686
687 if (unlikely(sel->info.writes_1_if_tex_is_1 == 0xff)) {
688 /* Wait for the shader to be ready. */
689 util_queue_fence_wait(&sel->ready);
690 assert(sel->nir_binary);
691
692 struct nir_shader *nir = si_deserialize_shader(sel);
693
694 /* Determine if this fragment shader always writes vec4(1) if a specific texture
695 * is all 1s.
696 */
697 float in[4] = { 1.0, 1.0, 1.0, 1.0 };
698 float out[4];
699 int texunit;
700 if (si_nir_is_output_const_if_tex_is_const(nir, in, out, &texunit) &&
701 !memcmp(in, out, 4 * sizeof(float))) {
702 sel->info.writes_1_if_tex_is_1 = 1 + texunit;
703 } else {
704 sel->info.writes_1_if_tex_is_1 = 0;
705 }
706
707 ralloc_free(nir);
708 }
709
710 if (sel->info.writes_1_if_tex_is_1 &&
711 sel->info.writes_1_if_tex_is_1 != 0xff) {
712 /* Now check if the texture is cleared to 1 */
713 int unit = sctx->shader.ps.cso->info.writes_1_if_tex_is_1 - 1;
714 struct si_samplers *samp = &sctx->samplers[PIPE_SHADER_FRAGMENT];
715 if ((1u << unit) & samp->enabled_mask) {
716 struct si_texture* tex = (struct si_texture*) samp->views[unit]->texture;
717 if (tex->is_depth &&
718 tex->depth_cleared_level_mask & BITFIELD_BIT(samp->views[unit]->u.tex.first_level) &&
719 tex->depth_clear_value[0] == 1) {
720 return false;
721 }
722 /* TODO: handle color textures */
723 }
724 }
725 }
726
727 return true;
728 }
729
si_draw_blend_dst_sampler_noop(struct pipe_context * ctx,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws)730 static void si_draw_blend_dst_sampler_noop(struct pipe_context *ctx,
731 const struct pipe_draw_info *info,
732 unsigned drawid_offset,
733 const struct pipe_draw_indirect_info *indirect,
734 const struct pipe_draw_start_count_bias *draws,
735 unsigned num_draws) {
736 struct si_context *sctx = (struct si_context *)ctx;
737
738 if (!si_check_blend_dst_sampler_noop(sctx))
739 return;
740
741 sctx->real_draw_vbo(ctx, info, drawid_offset, indirect, draws, num_draws);
742 }
743
si_draw_vstate_blend_dst_sampler_noop(struct pipe_context * ctx,struct pipe_vertex_state * state,uint32_t partial_velem_mask,struct pipe_draw_vertex_state_info info,const struct pipe_draw_start_count_bias * draws,unsigned num_draws)744 static void si_draw_vstate_blend_dst_sampler_noop(struct pipe_context *ctx,
745 struct pipe_vertex_state *state,
746 uint32_t partial_velem_mask,
747 struct pipe_draw_vertex_state_info info,
748 const struct pipe_draw_start_count_bias *draws,
749 unsigned num_draws) {
750 struct si_context *sctx = (struct si_context *)ctx;
751
752 if (!si_check_blend_dst_sampler_noop(sctx))
753 return;
754
755 sctx->real_draw_vertex_state(ctx, state, partial_velem_mask, info, draws, num_draws);
756 }
757
si_bind_blend_state(struct pipe_context * ctx,void * state)758 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
759 {
760 struct si_context *sctx = (struct si_context *)ctx;
761 struct si_state_blend *old_blend = sctx->queued.named.blend;
762 struct si_state_blend *blend = (struct si_state_blend *)state;
763
764 if (!blend)
765 blend = (struct si_state_blend *)sctx->noop_blend;
766
767 si_pm4_bind_state(sctx, blend, blend);
768
769 if (old_blend->cb_target_mask != blend->cb_target_mask ||
770 old_blend->dual_src_blend != blend->dual_src_blend ||
771 (old_blend->dcc_msaa_corruption_4bit != blend->dcc_msaa_corruption_4bit &&
772 sctx->framebuffer.has_dcc_msaa))
773 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
774
775 if ((sctx->screen->info.has_export_conflict_bug &&
776 old_blend->blend_enable_4bit != blend->blend_enable_4bit) ||
777 (sctx->occlusion_query_mode == SI_OCCLUSION_QUERY_MODE_PRECISE_BOOLEAN &&
778 !!old_blend->cb_target_mask != !!blend->cb_target_enabled_4bit))
779 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
780
781 if (old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
782 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
783 old_blend->alpha_to_one != blend->alpha_to_one ||
784 old_blend->dual_src_blend != blend->dual_src_blend ||
785 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
786 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
787 si_ps_key_update_framebuffer_blend_dsa_rasterizer(sctx);
788
789 if (old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
790 old_blend->alpha_to_coverage != blend->alpha_to_coverage)
791 si_update_ps_inputs_read_or_disabled(sctx);
792
793 if (sctx->screen->dpbb_allowed &&
794 (old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
795 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
796 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
797 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
798
799 if (sctx->screen->info.has_out_of_order_rast &&
800 ((old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
801 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
802 old_blend->commutative_4bit != blend->commutative_4bit ||
803 old_blend->logicop_enable != blend->logicop_enable)))
804 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
805
806 /* RB+ depth-only rendering. See the comment where we set rbplus_depth_only_opt for more
807 * information.
808 */
809 if (sctx->screen->info.rbplus_allowed &&
810 !!old_blend->cb_target_mask != !!blend->cb_target_mask) {
811 sctx->framebuffer.dirty_cbufs |= BITFIELD_BIT(0);
812 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
813 }
814
815 if (likely(!radeon_uses_secure_bos(sctx->ws))) {
816 if (unlikely(blend->allows_noop_optimization)) {
817 si_install_draw_wrapper(sctx, si_draw_blend_dst_sampler_noop,
818 si_draw_vstate_blend_dst_sampler_noop);
819 } else {
820 si_install_draw_wrapper(sctx, NULL, NULL);
821 }
822 }
823 }
824
si_delete_blend_state(struct pipe_context * ctx,void * state)825 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
826 {
827 struct si_context *sctx = (struct si_context *)ctx;
828
829 if (sctx->queued.named.blend == state)
830 si_bind_blend_state(ctx, sctx->noop_blend);
831
832 si_pm4_free_state(sctx, (struct si_pm4_state*)state, SI_STATE_IDX(blend));
833 }
834
si_set_blend_color(struct pipe_context * ctx,const struct pipe_blend_color * state)835 static void si_set_blend_color(struct pipe_context *ctx, const struct pipe_blend_color *state)
836 {
837 struct si_context *sctx = (struct si_context *)ctx;
838 static const struct pipe_blend_color zeros;
839
840 sctx->blend_color = *state;
841 sctx->blend_color_any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
842 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
843 }
844
si_emit_blend_color(struct si_context * sctx,unsigned index)845 static void si_emit_blend_color(struct si_context *sctx, unsigned index)
846 {
847 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
848
849 radeon_begin(cs);
850 radeon_set_context_reg_seq(R_028414_CB_BLEND_RED, 4);
851 radeon_emit_array((uint32_t *)sctx->blend_color.color, 4);
852 radeon_end();
853 }
854
855 /*
856 * Clipping
857 */
858
si_set_clip_state(struct pipe_context * ctx,const struct pipe_clip_state * state)859 static void si_set_clip_state(struct pipe_context *ctx, const struct pipe_clip_state *state)
860 {
861 struct si_context *sctx = (struct si_context *)ctx;
862 struct pipe_constant_buffer cb;
863 static const struct pipe_clip_state zeros;
864
865 if (memcmp(&sctx->clip_state, state, sizeof(*state)) == 0)
866 return;
867
868 sctx->clip_state = *state;
869 sctx->clip_state_any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
870 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
871
872 cb.buffer = NULL;
873 cb.user_buffer = state->ucp;
874 cb.buffer_offset = 0;
875 cb.buffer_size = 4 * 4 * 8;
876 si_set_internal_const_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
877 }
878
si_emit_clip_state(struct si_context * sctx,unsigned index)879 static void si_emit_clip_state(struct si_context *sctx, unsigned index)
880 {
881 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
882
883 radeon_begin(cs);
884 if (sctx->gfx_level >= GFX12)
885 radeon_set_context_reg_seq(R_0282D0_PA_CL_UCP_0_X, 6 * 4);
886 else
887 radeon_set_context_reg_seq(R_0285BC_PA_CL_UCP_0_X, 6 * 4);
888 radeon_emit_array((uint32_t *)sctx->clip_state.ucp, 6 * 4);
889 radeon_end();
890 }
891
si_emit_clip_regs(struct si_context * sctx,unsigned index)892 static void si_emit_clip_regs(struct si_context *sctx, unsigned index)
893 {
894 struct si_shader *vs = si_get_vs(sctx)->current;
895 struct si_shader_selector *vs_sel = vs->selector;
896 struct si_shader_info *info = &vs_sel->info;
897 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
898 bool window_space = vs_sel->stage == MESA_SHADER_VERTEX ?
899 info->base.vs.window_space_position : 0;
900 unsigned clipdist_mask = vs_sel->info.clipdist_mask;
901 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SI_USER_CLIP_PLANE_MASK;
902 unsigned culldist_mask = vs_sel->info.culldist_mask;
903
904 /* Clip distances on points have no effect, so need to be implemented
905 * as cull distances. This applies for the clipvertex case as well.
906 *
907 * Setting this for primitives other than points should have no adverse
908 * effects.
909 */
910 clipdist_mask &= rs->clip_plane_enable;
911 culldist_mask |= clipdist_mask;
912
913 unsigned pa_cl_cntl = S_02881C_BYPASS_VTX_RATE_COMBINER(sctx->gfx_level >= GFX10_3 &&
914 !sctx->screen->options.vrs2x2) |
915 S_02881C_BYPASS_PRIM_RATE_COMBINER(sctx->gfx_level >= GFX10_3) |
916 clipdist_mask | (culldist_mask << 8);
917
918 unsigned pa_cl_clip_cntl = rs->pa_cl_clip_cntl | ucp_mask |
919 S_028810_CLIP_DISABLE(window_space);
920 unsigned pa_cl_vs_out_cntl = pa_cl_cntl | vs->pa_cl_vs_out_cntl;
921
922 if (sctx->gfx_level >= GFX12) {
923 radeon_begin(&sctx->gfx_cs);
924 gfx12_begin_context_regs();
925 gfx12_opt_set_context_reg(R_028810_PA_CL_CLIP_CNTL, SI_TRACKED_PA_CL_CLIP_CNTL,
926 pa_cl_clip_cntl);
927 gfx12_opt_set_context_reg(R_028818_PA_CL_VS_OUT_CNTL, SI_TRACKED_PA_CL_VS_OUT_CNTL,
928 pa_cl_vs_out_cntl);
929 gfx12_end_context_regs();
930 radeon_end(); /* don't track context rolls on GFX12 */
931 } else if (sctx->screen->info.has_set_context_pairs_packed) {
932 radeon_begin(&sctx->gfx_cs);
933 gfx11_begin_packed_context_regs();
934 gfx11_opt_set_context_reg(R_028810_PA_CL_CLIP_CNTL, SI_TRACKED_PA_CL_CLIP_CNTL,
935 pa_cl_clip_cntl);
936 gfx11_opt_set_context_reg(R_02881C_PA_CL_VS_OUT_CNTL, SI_TRACKED_PA_CL_VS_OUT_CNTL,
937 pa_cl_vs_out_cntl);
938 gfx11_end_packed_context_regs();
939 radeon_end(); /* don't track context rolls on GFX11 */
940 } else {
941 radeon_begin(&sctx->gfx_cs);
942 radeon_opt_set_context_reg(R_028810_PA_CL_CLIP_CNTL, SI_TRACKED_PA_CL_CLIP_CNTL,
943 pa_cl_clip_cntl);
944 radeon_opt_set_context_reg(R_02881C_PA_CL_VS_OUT_CNTL, SI_TRACKED_PA_CL_VS_OUT_CNTL,
945 pa_cl_vs_out_cntl);
946 radeon_end_update_context_roll();
947 }
948 }
949
950 /*
951 * Rasterizer
952 */
953
si_translate_fill(uint32_t func)954 static uint32_t si_translate_fill(uint32_t func)
955 {
956 switch (func) {
957 case PIPE_POLYGON_MODE_FILL:
958 return V_028814_X_DRAW_TRIANGLES;
959 case PIPE_POLYGON_MODE_LINE:
960 return V_028814_X_DRAW_LINES;
961 case PIPE_POLYGON_MODE_POINT:
962 return V_028814_X_DRAW_POINTS;
963 default:
964 assert(0);
965 return V_028814_X_DRAW_POINTS;
966 }
967 }
968
si_create_rs_state(struct pipe_context * ctx,const struct pipe_rasterizer_state * state)969 static void *si_create_rs_state(struct pipe_context *ctx, const struct pipe_rasterizer_state *state)
970 {
971 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
972 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
973
974 if (!rs) {
975 return NULL;
976 }
977
978 rs->scissor_enable = state->scissor;
979 rs->clip_halfz = state->clip_halfz;
980 rs->two_side = state->light_twoside;
981 rs->multisample_enable = state->multisample;
982 rs->force_persample_interp = state->force_persample_interp;
983 rs->clip_plane_enable = state->clip_plane_enable;
984 rs->half_pixel_center = state->half_pixel_center;
985 rs->line_stipple_enable = state->line_stipple_enable;
986 rs->poly_stipple_enable = state->poly_stipple_enable;
987 rs->line_smooth = state->line_smooth;
988 rs->line_width = state->line_width;
989 rs->poly_smooth = state->poly_smooth;
990 rs->point_smooth = state->point_smooth;
991 rs->uses_poly_offset = state->offset_point || state->offset_line || state->offset_tri;
992 rs->clamp_fragment_color = state->clamp_fragment_color;
993 rs->clamp_vertex_color = state->clamp_vertex_color;
994 rs->flatshade = state->flatshade;
995 rs->flatshade_first = state->flatshade_first;
996 rs->sprite_coord_enable = state->sprite_coord_enable;
997 rs->rasterizer_discard = state->rasterizer_discard;
998 rs->bottom_edge_rule = state->bottom_edge_rule;
999 rs->polygon_mode_is_lines =
1000 (state->fill_front == PIPE_POLYGON_MODE_LINE && !(state->cull_face & PIPE_FACE_FRONT)) ||
1001 (state->fill_back == PIPE_POLYGON_MODE_LINE && !(state->cull_face & PIPE_FACE_BACK));
1002 rs->polygon_mode_is_points =
1003 (state->fill_front == PIPE_POLYGON_MODE_POINT && !(state->cull_face & PIPE_FACE_FRONT)) ||
1004 (state->fill_back == PIPE_POLYGON_MODE_POINT && !(state->cull_face & PIPE_FACE_BACK));
1005 rs->pa_sc_line_stipple = state->line_stipple_enable ?
1006 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
1007 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
1008 /* TODO: implement line stippling with perpendicular end caps. */
1009 /* Line width > 2 is an internal recommendation. */
1010 rs->perpendicular_end_caps = state->multisample &&
1011 state->line_width > 2 && !state->line_stipple_enable;
1012
1013 rs->pa_cl_clip_cntl = S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
1014 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
1015 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
1016 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
1017 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1018
1019 rs->ngg_cull_flags_tris = SI_NGG_CULL_CLIP_PLANE_ENABLE(state->clip_plane_enable);
1020 rs->ngg_cull_flags_lines = (!rs->perpendicular_end_caps ? SI_NGG_CULL_SMALL_LINES_DIAMOND_EXIT : 0) |
1021 SI_NGG_CULL_CLIP_PLANE_ENABLE(state->clip_plane_enable);
1022
1023 if (!state->front_ccw) {
1024 rs->ngg_cull_front = state->cull_face & PIPE_FACE_FRONT || rs->rasterizer_discard;
1025 rs->ngg_cull_back = state->cull_face & PIPE_FACE_BACK || rs->rasterizer_discard;
1026 } else {
1027 rs->ngg_cull_front = state->cull_face & PIPE_FACE_BACK || rs->rasterizer_discard;
1028 rs->ngg_cull_back = state->cull_face & PIPE_FACE_FRONT || rs->rasterizer_discard;
1029 }
1030
1031 /* Force gl_FrontFacing to true or false if the other face is culled. */
1032 if (util_bitcount(state->cull_face) == 1) {
1033 if (state->cull_face & PIPE_FACE_FRONT)
1034 rs->force_front_face_input = -1;
1035 else
1036 rs->force_front_face_input = 1;
1037 }
1038
1039 rs->spi_interp_control_0 = S_0286D4_FLAT_SHADE_ENA(1) |
1040 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
1041 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1042 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1043 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1044 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1045 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode !=
1046 PIPE_SPRITE_COORD_UPPER_LEFT);
1047
1048 /* point size 12.4 fixed point */
1049 float psize_min, psize_max;
1050 unsigned tmp = (unsigned)(state->point_size * 8.0);
1051 rs->pa_su_point_size = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
1052
1053 if (state->point_size_per_vertex) {
1054 psize_min = util_get_min_point_size(state);
1055 psize_max = SI_MAX_POINT_SIZE;
1056 } else {
1057 /* Force the point size to be as if the vertex output was disabled. */
1058 psize_min = state->point_size;
1059 psize_max = state->point_size;
1060 }
1061 rs->max_point_size = psize_max;
1062
1063 /* Divide by two, because 0.5 = 1 pixel. */
1064 rs->pa_su_point_minmax = S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min / 2)) |
1065 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max / 2));
1066 rs->pa_su_line_cntl = S_028A08_WIDTH(si_pack_float_12p4(state->line_width / 2));
1067
1068 rs->pa_sc_mode_cntl_0 = S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
1069 S_028A48_MSAA_ENABLE(state->multisample || state->poly_smooth ||
1070 state->line_smooth) |
1071 S_028A48_VPORT_SCISSOR_ENABLE(1) |
1072 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.gfx_level >= GFX9);
1073
1074 bool polygon_mode_enabled =
1075 (state->fill_front != PIPE_POLYGON_MODE_FILL && !(state->cull_face & PIPE_FACE_FRONT)) ||
1076 (state->fill_back != PIPE_POLYGON_MODE_FILL && !(state->cull_face & PIPE_FACE_BACK));
1077
1078 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
1079 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
1080 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
1081 S_028814_FACE(!state->front_ccw) |
1082 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
1083 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
1084 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
1085 S_028814_POLY_MODE(polygon_mode_enabled) |
1086 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
1087 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)) |
1088 /* this must be set if POLY_MODE or PERPENDICULAR_ENDCAP_ENA is set */
1089 S_028814_KEEP_TOGETHER_ENABLE(sscreen->info.gfx_level >= GFX10 &&
1090 sscreen->info.gfx_level < GFX12 ?
1091 polygon_mode_enabled ||
1092 rs->perpendicular_end_caps : 0);
1093 if (sscreen->info.gfx_level >= GFX10) {
1094 rs->pa_cl_ngg_cntl = S_028838_INDEX_BUF_EDGE_FLAG_ENA(rs->polygon_mode_is_points ||
1095 rs->polygon_mode_is_lines) |
1096 S_028838_VERTEX_REUSE_DEPTH(sscreen->info.gfx_level >= GFX10_3 ? 30 : 0);
1097 }
1098
1099 if (state->bottom_edge_rule) {
1100 /* OpenGL windows should set this. */
1101 rs->pa_sc_edgerule = S_028230_ER_TRI(0xA) |
1102 S_028230_ER_POINT(0x5) |
1103 S_028230_ER_RECT(0x9) |
1104 S_028230_ER_LINE_LR(0x2A) |
1105 S_028230_ER_LINE_RL(0x2A) |
1106 S_028230_ER_LINE_TB(0xA) |
1107 S_028230_ER_LINE_BT(0xA);
1108 } else {
1109 /* OpenGL FBOs and Direct3D should set this. */
1110 rs->pa_sc_edgerule = S_028230_ER_TRI(0xA) |
1111 S_028230_ER_POINT(0x6) |
1112 S_028230_ER_RECT(0xA) |
1113 S_028230_ER_LINE_LR(0x19) |
1114 S_028230_ER_LINE_RL(0x25) |
1115 S_028230_ER_LINE_TB(0xA) |
1116 S_028230_ER_LINE_BT(0xA);
1117 }
1118
1119 if (rs->uses_poly_offset) {
1120 /* Calculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
1121 rs->pa_su_poly_offset_clamp = fui(state->offset_clamp);
1122 rs->pa_su_poly_offset_frontback_scale = fui(state->offset_scale * 16);
1123
1124 if (!state->offset_units_unscaled) {
1125 /* 16-bit zbuffer */
1126 rs->pa_su_poly_offset_db_fmt_cntl[0] = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1127 rs->pa_su_poly_offset_frontback_offset[0] = fui(state->offset_units * 4);
1128
1129 /* 24-bit zbuffer */
1130 rs->pa_su_poly_offset_db_fmt_cntl[1] = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1131 rs->pa_su_poly_offset_frontback_offset[1] = fui(state->offset_units * 2);
1132
1133 /* 32-bit zbuffer */
1134 rs->pa_su_poly_offset_db_fmt_cntl[2] = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1135 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1136 rs->pa_su_poly_offset_frontback_offset[2] = fui(state->offset_units);
1137 } else {
1138 rs->pa_su_poly_offset_frontback_offset[0] = fui(state->offset_units);
1139 rs->pa_su_poly_offset_frontback_offset[1] = fui(state->offset_units);
1140 rs->pa_su_poly_offset_frontback_offset[2] = fui(state->offset_units);
1141 }
1142 }
1143
1144 return rs;
1145 }
1146
si_pm4_emit_rasterizer(struct si_context * sctx,unsigned index)1147 static void si_pm4_emit_rasterizer(struct si_context *sctx, unsigned index)
1148 {
1149 struct si_state_rasterizer *state = sctx->queued.named.rasterizer;
1150
1151 if (sctx->screen->info.gfx_level >= GFX12) {
1152 radeon_begin(&sctx->gfx_cs);
1153 gfx12_begin_context_regs();
1154 if (state->line_stipple_enable) {
1155 gfx12_opt_set_context_reg(R_028A0C_PA_SC_LINE_STIPPLE, SI_TRACKED_PA_SC_LINE_STIPPLE,
1156 state->pa_sc_line_stipple);
1157 }
1158
1159 gfx12_opt_set_context_reg(R_028644_SPI_INTERP_CONTROL_0, SI_TRACKED_SPI_INTERP_CONTROL_0,
1160 state->spi_interp_control_0);
1161 gfx12_opt_set_context_reg(R_028A00_PA_SU_POINT_SIZE, SI_TRACKED_PA_SU_POINT_SIZE,
1162 state->pa_su_point_size);
1163 gfx12_opt_set_context_reg(R_028A04_PA_SU_POINT_MINMAX, SI_TRACKED_PA_SU_POINT_MINMAX,
1164 state->pa_su_point_minmax);
1165 gfx12_opt_set_context_reg(R_028A08_PA_SU_LINE_CNTL, SI_TRACKED_PA_SU_LINE_CNTL,
1166 state->pa_su_line_cntl);
1167 gfx12_opt_set_context_reg(R_028A48_PA_SC_MODE_CNTL_0, SI_TRACKED_PA_SC_MODE_CNTL_0,
1168 state->pa_sc_mode_cntl_0);
1169 gfx12_opt_set_context_reg(R_02881C_PA_SU_SC_MODE_CNTL, SI_TRACKED_PA_SU_SC_MODE_CNTL,
1170 state->pa_su_sc_mode_cntl);
1171 gfx12_opt_set_context_reg(R_028838_PA_CL_NGG_CNTL, SI_TRACKED_PA_CL_NGG_CNTL,
1172 state->pa_cl_ngg_cntl);
1173 gfx12_opt_set_context_reg(R_028230_PA_SC_EDGERULE, SI_TRACKED_PA_SC_EDGERULE,
1174 state->pa_sc_edgerule);
1175
1176 if (state->uses_poly_offset && sctx->framebuffer.state.zsbuf) {
1177 unsigned db_format_index =
1178 ((struct si_surface *)sctx->framebuffer.state.zsbuf)->db_format_index;
1179
1180 gfx12_opt_set_context_reg(R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1181 SI_TRACKED_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1182 state->pa_su_poly_offset_db_fmt_cntl[db_format_index]);
1183 gfx12_opt_set_context_reg(R_028B7C_PA_SU_POLY_OFFSET_CLAMP,
1184 SI_TRACKED_PA_SU_POLY_OFFSET_CLAMP,
1185 state->pa_su_poly_offset_clamp);
1186 gfx12_opt_set_context_reg(R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1187 SI_TRACKED_PA_SU_POLY_OFFSET_FRONT_SCALE,
1188 state->pa_su_poly_offset_frontback_scale);
1189 gfx12_opt_set_context_reg(R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1190 SI_TRACKED_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1191 state->pa_su_poly_offset_frontback_offset[db_format_index]);
1192 gfx12_opt_set_context_reg(R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1193 SI_TRACKED_PA_SU_POLY_OFFSET_BACK_SCALE,
1194 state->pa_su_poly_offset_frontback_scale);
1195 gfx12_opt_set_context_reg(R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1196 SI_TRACKED_PA_SU_POLY_OFFSET_BACK_OFFSET,
1197 state->pa_su_poly_offset_frontback_offset[db_format_index]);
1198 }
1199 gfx12_end_context_regs();
1200 radeon_end(); /* don't track context rolls on GFX12 */
1201 } else if (sctx->screen->info.has_set_context_pairs_packed) {
1202 radeon_begin(&sctx->gfx_cs);
1203 gfx11_begin_packed_context_regs();
1204 gfx11_opt_set_context_reg(R_0286D4_SPI_INTERP_CONTROL_0, SI_TRACKED_SPI_INTERP_CONTROL_0,
1205 state->spi_interp_control_0);
1206 gfx11_opt_set_context_reg(R_028A00_PA_SU_POINT_SIZE, SI_TRACKED_PA_SU_POINT_SIZE,
1207 state->pa_su_point_size);
1208 gfx11_opt_set_context_reg(R_028A04_PA_SU_POINT_MINMAX, SI_TRACKED_PA_SU_POINT_MINMAX,
1209 state->pa_su_point_minmax);
1210 gfx11_opt_set_context_reg(R_028A08_PA_SU_LINE_CNTL, SI_TRACKED_PA_SU_LINE_CNTL,
1211 state->pa_su_line_cntl);
1212 gfx11_opt_set_context_reg(R_028A48_PA_SC_MODE_CNTL_0, SI_TRACKED_PA_SC_MODE_CNTL_0,
1213 state->pa_sc_mode_cntl_0);
1214 gfx11_opt_set_context_reg(R_028814_PA_SU_SC_MODE_CNTL, SI_TRACKED_PA_SU_SC_MODE_CNTL,
1215 state->pa_su_sc_mode_cntl);
1216 gfx11_opt_set_context_reg(R_028838_PA_CL_NGG_CNTL, SI_TRACKED_PA_CL_NGG_CNTL,
1217 state->pa_cl_ngg_cntl);
1218 gfx11_opt_set_context_reg(R_028230_PA_SC_EDGERULE, SI_TRACKED_PA_SC_EDGERULE,
1219 state->pa_sc_edgerule);
1220
1221 if (state->uses_poly_offset && sctx->framebuffer.state.zsbuf) {
1222 unsigned db_format_index =
1223 ((struct si_surface *)sctx->framebuffer.state.zsbuf)->db_format_index;
1224
1225 gfx11_opt_set_context_reg(R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1226 SI_TRACKED_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1227 state->pa_su_poly_offset_db_fmt_cntl[db_format_index]);
1228 gfx11_opt_set_context_reg(R_028B7C_PA_SU_POLY_OFFSET_CLAMP,
1229 SI_TRACKED_PA_SU_POLY_OFFSET_CLAMP,
1230 state->pa_su_poly_offset_clamp);
1231 gfx11_opt_set_context_reg(R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1232 SI_TRACKED_PA_SU_POLY_OFFSET_FRONT_SCALE,
1233 state->pa_su_poly_offset_frontback_scale);
1234 gfx11_opt_set_context_reg(R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1235 SI_TRACKED_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1236 state->pa_su_poly_offset_frontback_offset[db_format_index]);
1237 gfx11_opt_set_context_reg(R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1238 SI_TRACKED_PA_SU_POLY_OFFSET_BACK_SCALE,
1239 state->pa_su_poly_offset_frontback_scale);
1240 gfx11_opt_set_context_reg(R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1241 SI_TRACKED_PA_SU_POLY_OFFSET_BACK_OFFSET,
1242 state->pa_su_poly_offset_frontback_offset[db_format_index]);
1243 }
1244 gfx11_end_packed_context_regs();
1245 radeon_end(); /* don't track context rolls on GFX11 */
1246 } else {
1247 radeon_begin(&sctx->gfx_cs);
1248 radeon_opt_set_context_reg(R_0286D4_SPI_INTERP_CONTROL_0,
1249 SI_TRACKED_SPI_INTERP_CONTROL_0,
1250 state->spi_interp_control_0);
1251 radeon_opt_set_context_reg(R_028A00_PA_SU_POINT_SIZE, SI_TRACKED_PA_SU_POINT_SIZE,
1252 state->pa_su_point_size);
1253 radeon_opt_set_context_reg(R_028A04_PA_SU_POINT_MINMAX, SI_TRACKED_PA_SU_POINT_MINMAX,
1254 state->pa_su_point_minmax);
1255 radeon_opt_set_context_reg(R_028A08_PA_SU_LINE_CNTL, SI_TRACKED_PA_SU_LINE_CNTL,
1256 state->pa_su_line_cntl);
1257 radeon_opt_set_context_reg(R_028A48_PA_SC_MODE_CNTL_0, SI_TRACKED_PA_SC_MODE_CNTL_0,
1258 state->pa_sc_mode_cntl_0);
1259 radeon_opt_set_context_reg(R_028814_PA_SU_SC_MODE_CNTL,
1260 SI_TRACKED_PA_SU_SC_MODE_CNTL, state->pa_su_sc_mode_cntl);
1261 if (sctx->gfx_level >= GFX10) {
1262 radeon_opt_set_context_reg(R_028838_PA_CL_NGG_CNTL, SI_TRACKED_PA_CL_NGG_CNTL,
1263 state->pa_cl_ngg_cntl);
1264 }
1265 radeon_opt_set_context_reg(R_028230_PA_SC_EDGERULE, SI_TRACKED_PA_SC_EDGERULE,
1266 state->pa_sc_edgerule);
1267
1268 if (state->uses_poly_offset && sctx->framebuffer.state.zsbuf) {
1269 unsigned db_format_index =
1270 ((struct si_surface *)sctx->framebuffer.state.zsbuf)->db_format_index;
1271
1272 radeon_opt_set_context_reg6(R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1273 SI_TRACKED_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1274 state->pa_su_poly_offset_db_fmt_cntl[db_format_index],
1275 state->pa_su_poly_offset_clamp,
1276 state->pa_su_poly_offset_frontback_scale,
1277 state->pa_su_poly_offset_frontback_offset[db_format_index],
1278 state->pa_su_poly_offset_frontback_scale,
1279 state->pa_su_poly_offset_frontback_offset[db_format_index]);
1280 }
1281 radeon_end_update_context_roll();
1282 }
1283
1284 sctx->emitted.named.rasterizer = state;
1285 }
1286
si_bind_rs_state(struct pipe_context * ctx,void * state)1287 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1288 {
1289 struct si_context *sctx = (struct si_context *)ctx;
1290 struct si_state_rasterizer *old_rs = (struct si_state_rasterizer *)sctx->queued.named.rasterizer;
1291 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1292
1293 if (!rs)
1294 rs = (struct si_state_rasterizer *)sctx->discard_rasterizer_state;
1295
1296 if (old_rs->multisample_enable != rs->multisample_enable) {
1297 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1298
1299 /* Update the small primitive filter workaround if necessary. */
1300 if (sctx->screen->info.has_small_prim_filter_sample_loc_bug && sctx->framebuffer.nr_samples > 1)
1301 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_locations);
1302
1303 /* NGG cull state uses multisample_enable. */
1304 if (sctx->screen->use_ngg_culling)
1305 si_mark_atom_dirty(sctx, &sctx->atoms.s.ngg_cull_state);
1306 }
1307
1308 if (old_rs->perpendicular_end_caps != rs->perpendicular_end_caps)
1309 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1310
1311 if (sctx->screen->use_ngg_culling &&
1312 (old_rs->half_pixel_center != rs->half_pixel_center ||
1313 old_rs->line_width != rs->line_width))
1314 si_mark_atom_dirty(sctx, &sctx->atoms.s.ngg_cull_state);
1315
1316 SET_FIELD(sctx->current_vs_state, VS_STATE_CLAMP_VERTEX_COLOR, rs->clamp_vertex_color);
1317
1318 si_pm4_bind_state(sctx, rasterizer, rs);
1319 si_update_ngg_cull_face_state(sctx);
1320
1321 if (old_rs->scissor_enable != rs->scissor_enable)
1322 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1323
1324 /* This never changes for OpenGL. */
1325 if (old_rs->half_pixel_center != rs->half_pixel_center)
1326 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1327
1328 if (util_prim_is_lines(sctx->current_rast_prim))
1329 si_set_clip_discard_distance(sctx, rs->line_width);
1330 else if (sctx->current_rast_prim == MESA_PRIM_POINTS)
1331 si_set_clip_discard_distance(sctx, rs->max_point_size);
1332
1333 if (old_rs->clip_halfz != rs->clip_halfz)
1334 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1335
1336 if (old_rs->clip_plane_enable != rs->clip_plane_enable ||
1337 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1338 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1339
1340 if (old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1341 old_rs->flatshade != rs->flatshade)
1342 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
1343
1344 if (sctx->screen->dpbb_allowed && (old_rs->bottom_edge_rule != rs->bottom_edge_rule))
1345 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1346
1347 if (old_rs->multisample_enable != rs->multisample_enable)
1348 si_ps_key_update_framebuffer_blend_dsa_rasterizer(sctx);
1349
1350 if (old_rs->flatshade != rs->flatshade ||
1351 old_rs->clamp_fragment_color != rs->clamp_fragment_color)
1352 si_ps_key_update_rasterizer(sctx);
1353
1354 if (old_rs->flatshade != rs->flatshade ||
1355 old_rs->force_persample_interp != rs->force_persample_interp ||
1356 old_rs->multisample_enable != rs->multisample_enable)
1357 si_ps_key_update_framebuffer_rasterizer_sample_shading(sctx);
1358
1359 if (old_rs->rasterizer_discard != rs->rasterizer_discard ||
1360 old_rs->two_side != rs->two_side ||
1361 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1362 old_rs->point_smooth != rs->point_smooth)
1363 si_update_ps_inputs_read_or_disabled(sctx);
1364
1365 if (old_rs->point_smooth != rs->point_smooth ||
1366 old_rs->line_smooth != rs->line_smooth ||
1367 old_rs->poly_smooth != rs->poly_smooth ||
1368 old_rs->polygon_mode_is_points != rs->polygon_mode_is_points ||
1369 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1370 old_rs->two_side != rs->two_side ||
1371 old_rs->force_front_face_input != rs->force_front_face_input)
1372 si_vs_ps_key_update_rast_prim_smooth_stipple(sctx);
1373
1374 /* Used by si_get_vs_key_outputs in si_update_shaders: */
1375 if (old_rs->clip_plane_enable != rs->clip_plane_enable)
1376 sctx->do_update_shaders = true;
1377
1378 if (old_rs->line_smooth != rs->line_smooth ||
1379 old_rs->poly_smooth != rs->poly_smooth ||
1380 old_rs->point_smooth != rs->point_smooth ||
1381 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1382 old_rs->flatshade != rs->flatshade)
1383 si_update_vrs_flat_shading(sctx);
1384
1385 if (old_rs->flatshade_first != rs->flatshade_first)
1386 si_update_ngg_sgpr_state_provoking_vtx(sctx, si_get_vs(sctx)->current, sctx->ngg);
1387 }
1388
si_delete_rs_state(struct pipe_context * ctx,void * state)1389 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1390 {
1391 struct si_context *sctx = (struct si_context *)ctx;
1392 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1393
1394 if (sctx->queued.named.rasterizer == state)
1395 si_bind_rs_state(ctx, sctx->discard_rasterizer_state);
1396
1397 si_pm4_free_state(sctx, &rs->pm4, SI_STATE_IDX(rasterizer));
1398 }
1399
1400 /*
1401 * inferred state between dsa and stencil ref
1402 */
si_emit_stencil_ref(struct si_context * sctx,unsigned index)1403 static void si_emit_stencil_ref(struct si_context *sctx, unsigned index)
1404 {
1405 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1406
1407 if (sctx->gfx_level >= GFX12) {
1408 radeon_begin(&sctx->gfx_cs);
1409 radeon_set_context_reg(R_028088_DB_STENCIL_REF,
1410 S_028088_TESTVAL(ref->ref_value[0]) |
1411 S_028088_TESTVAL_BF(ref->ref_value[1]));
1412 radeon_end();
1413 } else {
1414 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1415
1416 radeon_begin(&sctx->gfx_cs);
1417 radeon_set_context_reg_seq(R_028430_DB_STENCILREFMASK, 2);
1418 radeon_emit(S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1419 S_028430_STENCILMASK(dsa->valuemask[0]) |
1420 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1421 S_028430_STENCILOPVAL(1));
1422 radeon_emit(S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1423 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1424 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1425 S_028434_STENCILOPVAL_BF(1));
1426 radeon_end();
1427 }
1428 }
1429
si_set_stencil_ref(struct pipe_context * ctx,const struct pipe_stencil_ref state)1430 static void si_set_stencil_ref(struct pipe_context *ctx, const struct pipe_stencil_ref state)
1431 {
1432 struct si_context *sctx = (struct si_context *)ctx;
1433
1434 if (memcmp(&sctx->stencil_ref.state, &state, sizeof(state)) == 0)
1435 return;
1436
1437 sctx->stencil_ref.state = state;
1438 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1439 }
1440
1441 /*
1442 * DSA
1443 */
1444
si_translate_stencil_op(int s_op)1445 static uint32_t si_translate_stencil_op(int s_op)
1446 {
1447 switch (s_op) {
1448 case PIPE_STENCIL_OP_KEEP:
1449 return V_02842C_STENCIL_KEEP;
1450 case PIPE_STENCIL_OP_ZERO:
1451 return V_02842C_STENCIL_ZERO;
1452 case PIPE_STENCIL_OP_REPLACE:
1453 return V_02842C_STENCIL_REPLACE_TEST;
1454 case PIPE_STENCIL_OP_INCR:
1455 return V_02842C_STENCIL_ADD_CLAMP;
1456 case PIPE_STENCIL_OP_DECR:
1457 return V_02842C_STENCIL_SUB_CLAMP;
1458 case PIPE_STENCIL_OP_INCR_WRAP:
1459 return V_02842C_STENCIL_ADD_WRAP;
1460 case PIPE_STENCIL_OP_DECR_WRAP:
1461 return V_02842C_STENCIL_SUB_WRAP;
1462 case PIPE_STENCIL_OP_INVERT:
1463 return V_02842C_STENCIL_INVERT;
1464 default:
1465 PRINT_ERR("Unknown stencil op %d", s_op);
1466 assert(0);
1467 break;
1468 }
1469 return 0;
1470 }
1471
si_order_invariant_stencil_op(enum pipe_stencil_op op)1472 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1473 {
1474 /* REPLACE is normally order invariant, except when the stencil
1475 * reference value is written by the fragment shader. Tracking this
1476 * interaction does not seem worth the effort, so be conservative. */
1477 return op != PIPE_STENCIL_OP_INCR && op != PIPE_STENCIL_OP_DECR && op != PIPE_STENCIL_OP_REPLACE;
1478 }
1479
1480 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1481 * invariant in the sense that the set of passing fragments as well as the
1482 * final stencil buffer result does not depend on the order of fragments. */
si_order_invariant_stencil_state(const struct pipe_stencil_state * state)1483 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1484 {
1485 return !state->enabled || !state->writemask ||
1486 /* The following assumes that Z writes are disabled. */
1487 (state->func == PIPE_FUNC_ALWAYS && si_order_invariant_stencil_op(state->zpass_op) &&
1488 si_order_invariant_stencil_op(state->zfail_op)) ||
1489 (state->func == PIPE_FUNC_NEVER && si_order_invariant_stencil_op(state->fail_op));
1490 }
1491
si_create_dsa_state(struct pipe_context * ctx,const struct pipe_depth_stencil_alpha_state * state)1492 static void *si_create_dsa_state(struct pipe_context *ctx,
1493 const struct pipe_depth_stencil_alpha_state *state)
1494 {
1495 struct si_context *sctx = (struct si_context *)ctx;
1496 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1497 if (!dsa) {
1498 return NULL;
1499 }
1500
1501 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1502 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1503 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1504 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1505
1506 dsa->db_depth_control =
1507 S_028800_Z_ENABLE(state->depth_enabled) | S_028800_Z_WRITE_ENABLE(state->depth_writemask) |
1508 S_028800_ZFUNC(state->depth_func) | S_028800_DEPTH_BOUNDS_ENABLE(state->depth_bounds_test);
1509
1510 /* stencil */
1511 if (state->stencil[0].enabled) {
1512 dsa->db_depth_control |= S_028800_STENCIL_ENABLE(1);
1513 dsa->db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1514 dsa->db_stencil_control |=
1515 S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1516 dsa->db_stencil_control |=
1517 S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1518 dsa->db_stencil_control |=
1519 S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1520
1521 if (state->stencil[1].enabled) {
1522 dsa->db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1523 dsa->db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1524 dsa->db_stencil_control |=
1525 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1526 dsa->db_stencil_control |=
1527 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1528 dsa->db_stencil_control |=
1529 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1530 }
1531 }
1532
1533 dsa->db_depth_bounds_min = fui(state->depth_bounds_min);
1534 dsa->db_depth_bounds_max = fui(state->depth_bounds_max);
1535
1536 /* alpha */
1537 if (state->alpha_enabled) {
1538 dsa->alpha_func = state->alpha_func;
1539 dsa->spi_shader_user_data_ps_alpha_ref = fui(state->alpha_ref_value);
1540 } else {
1541 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1542 }
1543
1544 dsa->depth_enabled = state->depth_enabled &&
1545 (state->depth_writemask || state->depth_func != PIPE_FUNC_ALWAYS);
1546 dsa->depth_write_enabled = state->depth_enabled && state->depth_writemask;
1547 dsa->stencil_enabled = state->stencil[0].enabled;
1548 dsa->stencil_write_enabled =
1549 (util_writes_stencil(&state->stencil[0]) || util_writes_stencil(&state->stencil[1]));
1550 dsa->db_can_write = dsa->depth_write_enabled || dsa->stencil_write_enabled;
1551 dsa->depth_bounds_enabled = state->depth_bounds_test;
1552
1553 if (sctx->gfx_level >= GFX12) {
1554 dsa->db_stencil_read_mask = S_028090_TESTMASK(state->stencil[0].valuemask) |
1555 S_028090_TESTMASK_BF(state->stencil[1].valuemask);
1556 dsa->db_stencil_write_mask = S_028094_WRITEMASK(state->stencil[0].writemask) |
1557 S_028094_WRITEMASK_BF(state->stencil[1].writemask);
1558
1559 bool force_s_valid = state->stencil[0].zpass_op != state->stencil[0].zfail_op ||
1560 (state->stencil[1].enabled &&
1561 state->stencil[1].zpass_op != state->stencil[1].zfail_op);
1562 dsa->db_render_override = S_02800C_FORCE_STENCIL_READ(1) |
1563 S_02800C_FORCE_STENCIL_VALID(force_s_valid);
1564 }
1565
1566 bool zfunc_is_ordered =
1567 state->depth_func == PIPE_FUNC_NEVER || state->depth_func == PIPE_FUNC_LESS ||
1568 state->depth_func == PIPE_FUNC_LEQUAL || state->depth_func == PIPE_FUNC_GREATER ||
1569 state->depth_func == PIPE_FUNC_GEQUAL;
1570
1571 bool nozwrite_and_order_invariant_stencil =
1572 !dsa->db_can_write ||
1573 (!dsa->depth_write_enabled && si_order_invariant_stencil_state(&state->stencil[0]) &&
1574 si_order_invariant_stencil_state(&state->stencil[1]));
1575
1576 dsa->order_invariance[1].zs =
1577 nozwrite_and_order_invariant_stencil || (!dsa->stencil_write_enabled && zfunc_is_ordered);
1578 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1579
1580 dsa->order_invariance[1].pass_set =
1581 nozwrite_and_order_invariant_stencil ||
1582 (!dsa->stencil_write_enabled &&
1583 (state->depth_func == PIPE_FUNC_ALWAYS || state->depth_func == PIPE_FUNC_NEVER));
1584 dsa->order_invariance[0].pass_set =
1585 !dsa->depth_write_enabled ||
1586 (state->depth_func == PIPE_FUNC_ALWAYS || state->depth_func == PIPE_FUNC_NEVER);
1587
1588 return dsa;
1589 }
1590
si_pm4_emit_dsa(struct si_context * sctx,unsigned index)1591 static void si_pm4_emit_dsa(struct si_context *sctx, unsigned index)
1592 {
1593 struct si_state_dsa *state = sctx->queued.named.dsa;
1594 assert(state && state != sctx->emitted.named.dsa);
1595
1596 if (sctx->gfx_level >= GFX12) {
1597 radeon_begin(&sctx->gfx_cs);
1598 gfx12_begin_context_regs();
1599 gfx12_opt_set_context_reg(R_02800C_DB_RENDER_OVERRIDE, SI_TRACKED_DB_RENDER_OVERRIDE,
1600 state->db_render_override);
1601 gfx12_opt_set_context_reg(R_028070_DB_DEPTH_CONTROL, SI_TRACKED_DB_DEPTH_CONTROL,
1602 state->db_depth_control);
1603 if (state->stencil_enabled) {
1604 gfx12_opt_set_context_reg(R_028074_DB_STENCIL_CONTROL, SI_TRACKED_DB_STENCIL_CONTROL,
1605 state->db_stencil_control);
1606 gfx12_opt_set_context_reg(R_028090_DB_STENCIL_READ_MASK, SI_TRACKED_DB_STENCIL_READ_MASK,
1607 state->db_stencil_read_mask);
1608 gfx12_opt_set_context_reg(R_028094_DB_STENCIL_WRITE_MASK, SI_TRACKED_DB_STENCIL_WRITE_MASK,
1609 state->db_stencil_write_mask);
1610 }
1611 if (state->depth_bounds_enabled) {
1612 gfx12_opt_set_context_reg(R_028050_DB_DEPTH_BOUNDS_MIN, SI_TRACKED_DB_DEPTH_BOUNDS_MIN,
1613 state->db_depth_bounds_min);
1614 gfx12_opt_set_context_reg(R_028054_DB_DEPTH_BOUNDS_MAX, SI_TRACKED_DB_DEPTH_BOUNDS_MAX,
1615 state->db_depth_bounds_max);
1616 }
1617 gfx12_end_context_regs();
1618 radeon_end(); /* don't track context rolls on GFX12 */
1619
1620 gfx12_opt_push_gfx_sh_reg(R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_ALPHA_REF * 4,
1621 SI_TRACKED_SPI_SHADER_USER_DATA_PS__ALPHA_REF,
1622 state->spi_shader_user_data_ps_alpha_ref);
1623 } else if (sctx->screen->info.has_set_context_pairs_packed) {
1624 radeon_begin(&sctx->gfx_cs);
1625 gfx11_begin_packed_context_regs();
1626 gfx11_opt_set_context_reg(R_028800_DB_DEPTH_CONTROL, SI_TRACKED_DB_DEPTH_CONTROL,
1627 state->db_depth_control);
1628 if (state->stencil_enabled) {
1629 gfx11_opt_set_context_reg(R_02842C_DB_STENCIL_CONTROL, SI_TRACKED_DB_STENCIL_CONTROL,
1630 state->db_stencil_control);
1631 }
1632 if (state->depth_bounds_enabled) {
1633 gfx11_opt_set_context_reg(R_028020_DB_DEPTH_BOUNDS_MIN, SI_TRACKED_DB_DEPTH_BOUNDS_MIN,
1634 state->db_depth_bounds_min);
1635 gfx11_opt_set_context_reg(R_028024_DB_DEPTH_BOUNDS_MAX, SI_TRACKED_DB_DEPTH_BOUNDS_MAX,
1636 state->db_depth_bounds_max);
1637 }
1638 gfx11_end_packed_context_regs();
1639
1640 if (state->alpha_func != PIPE_FUNC_ALWAYS) {
1641 if (sctx->screen->info.has_set_sh_pairs_packed) {
1642 gfx11_opt_push_gfx_sh_reg(R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_ALPHA_REF * 4,
1643 SI_TRACKED_SPI_SHADER_USER_DATA_PS__ALPHA_REF,
1644 state->spi_shader_user_data_ps_alpha_ref);
1645 } else {
1646 radeon_opt_set_sh_reg(R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_ALPHA_REF * 4,
1647 SI_TRACKED_SPI_SHADER_USER_DATA_PS__ALPHA_REF,
1648 state->spi_shader_user_data_ps_alpha_ref);
1649 }
1650 }
1651 radeon_end(); /* don't track context rolls on GFX11 */
1652 } else {
1653 radeon_begin(&sctx->gfx_cs);
1654 radeon_opt_set_context_reg(R_028800_DB_DEPTH_CONTROL, SI_TRACKED_DB_DEPTH_CONTROL,
1655 state->db_depth_control);
1656 if (state->stencil_enabled) {
1657 radeon_opt_set_context_reg(R_02842C_DB_STENCIL_CONTROL, SI_TRACKED_DB_STENCIL_CONTROL,
1658 state->db_stencil_control);
1659 }
1660 if (state->depth_bounds_enabled) {
1661 radeon_opt_set_context_reg2(R_028020_DB_DEPTH_BOUNDS_MIN,
1662 SI_TRACKED_DB_DEPTH_BOUNDS_MIN,
1663 state->db_depth_bounds_min,
1664 state->db_depth_bounds_max);
1665 }
1666 radeon_end_update_context_roll();
1667
1668 if (state->alpha_func != PIPE_FUNC_ALWAYS) {
1669 radeon_begin(&sctx->gfx_cs);
1670 radeon_opt_set_sh_reg(R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_ALPHA_REF * 4,
1671 SI_TRACKED_SPI_SHADER_USER_DATA_PS__ALPHA_REF,
1672 state->spi_shader_user_data_ps_alpha_ref);
1673 radeon_end();
1674 }
1675 }
1676
1677 sctx->emitted.named.dsa = state;
1678 }
1679
si_bind_dsa_state(struct pipe_context * ctx,void * state)1680 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1681 {
1682 struct si_context *sctx = (struct si_context *)ctx;
1683 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1684 struct si_state_dsa *dsa = state;
1685
1686 if (!dsa)
1687 dsa = (struct si_state_dsa *)sctx->noop_dsa;
1688
1689 si_pm4_bind_state(sctx, dsa, dsa);
1690
1691 /* Gfx12 doesn't need to combine a DSA state with a stencil ref state. */
1692 if (sctx->gfx_level < GFX12 &&
1693 memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1694 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1695 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1696 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1697 }
1698
1699 struct pipe_surface *zssurf = sctx->framebuffer.state.zsbuf;
1700 struct si_texture *zstex = (struct si_texture*)(zssurf ? zssurf->texture : NULL);
1701
1702 if (sctx->gfx_level == GFX12 && !sctx->screen->options.alt_hiz_logic &&
1703 sctx->framebuffer.has_stencil && dsa->stencil_enabled && !zstex->force_disable_hiz_his) {
1704 zstex->force_disable_hiz_his = true;
1705 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1706
1707 if (sctx->framebuffer.has_hiz_his) {
1708 sctx->framebuffer.has_hiz_his = false;
1709 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1710 }
1711 }
1712
1713 if (old_dsa->alpha_func != dsa->alpha_func) {
1714 si_ps_key_update_dsa(sctx);
1715 si_update_ps_inputs_read_or_disabled(sctx);
1716 sctx->do_update_shaders = true;
1717 }
1718
1719 if (old_dsa->depth_enabled != dsa->depth_enabled ||
1720 old_dsa->stencil_enabled != dsa->stencil_enabled) {
1721 si_ps_key_update_framebuffer_blend_dsa_rasterizer(sctx);
1722 sctx->do_update_shaders = true;
1723 }
1724
1725 if (sctx->occlusion_query_mode == SI_OCCLUSION_QUERY_MODE_PRECISE_BOOLEAN &&
1726 (old_dsa->depth_enabled != dsa->depth_enabled ||
1727 old_dsa->depth_write_enabled != dsa->depth_write_enabled))
1728 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1729
1730 if (sctx->screen->dpbb_allowed && ((old_dsa->depth_enabled != dsa->depth_enabled ||
1731 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1732 old_dsa->db_can_write != dsa->db_can_write)))
1733 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1734
1735 if (sctx->screen->info.has_out_of_order_rast &&
1736 (memcmp(old_dsa->order_invariance, dsa->order_invariance,
1737 sizeof(old_dsa->order_invariance))))
1738 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1739 }
1740
si_delete_dsa_state(struct pipe_context * ctx,void * state)1741 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1742 {
1743 struct si_context *sctx = (struct si_context *)ctx;
1744
1745 if (sctx->queued.named.dsa == state)
1746 si_bind_dsa_state(ctx, sctx->noop_dsa);
1747
1748 si_pm4_free_state(sctx, (struct si_pm4_state*)state, SI_STATE_IDX(dsa));
1749 }
1750
si_create_db_flush_dsa(struct si_context * sctx)1751 static void *si_create_db_flush_dsa(struct si_context *sctx)
1752 {
1753 struct pipe_depth_stencil_alpha_state dsa = {};
1754
1755 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1756 }
1757
1758 /* DB RENDER STATE */
1759
si_set_active_query_state(struct pipe_context * ctx,bool enable)1760 static void si_set_active_query_state(struct pipe_context *ctx, bool enable)
1761 {
1762 struct si_context *sctx = (struct si_context *)ctx;
1763
1764 /* Pipeline stat & streamout queries. */
1765 if (enable) {
1766 /* Disable pipeline stats if there are no active queries. */
1767 if (sctx->num_hw_pipestat_streamout_queries) {
1768 sctx->barrier_flags &= ~SI_BARRIER_EVENT_PIPELINESTAT_STOP;
1769 sctx->barrier_flags |= SI_BARRIER_EVENT_PIPELINESTAT_START;
1770 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
1771 }
1772 } else {
1773 if (sctx->num_hw_pipestat_streamout_queries) {
1774 sctx->barrier_flags &= ~SI_BARRIER_EVENT_PIPELINESTAT_START;
1775 sctx->barrier_flags |= SI_BARRIER_EVENT_PIPELINESTAT_STOP;
1776 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
1777 }
1778 }
1779
1780 /* Occlusion queries. */
1781 if (sctx->occlusion_queries_disabled != !enable) {
1782 sctx->occlusion_queries_disabled = !enable;
1783 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1784 }
1785 }
1786
si_save_qbo_state(struct si_context * sctx,struct si_qbo_state * st)1787 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1788 {
1789 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1790 }
1791
si_restore_qbo_state(struct si_context * sctx,struct si_qbo_state * st)1792 void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1793 {
1794 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, true, &st->saved_const0);
1795 }
1796
si_emit_db_render_state(struct si_context * sctx,unsigned index)1797 static void si_emit_db_render_state(struct si_context *sctx, unsigned index)
1798 {
1799 unsigned db_shader_control = 0, db_render_control = 0, db_count_control = 0, vrs_override_cntl = 0;
1800
1801 /* DB_RENDER_CONTROL */
1802 /* Program OREO_MODE optimally for GFX11+. */
1803 if (sctx->gfx_level >= GFX11) {
1804 bool z_export = G_02880C_Z_EXPORT_ENABLE(sctx->ps_db_shader_control);
1805 db_render_control |= S_028000_OREO_MODE(z_export ? V_028000_OMODE_BLEND : V_028000_OMODE_O_THEN_B);
1806 }
1807
1808 if (sctx->gfx_level >= GFX12) {
1809 assert(!sctx->dbcb_depth_copy_enabled && !sctx->dbcb_stencil_copy_enabled);
1810 assert(!sctx->db_flush_depth_inplace && !sctx->db_flush_stencil_inplace);
1811 assert(!sctx->db_depth_clear && !sctx->db_stencil_clear);
1812 } else {
1813 if (sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled) {
1814 db_render_control |= S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1815 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1816 S_028000_COPY_CENTROID(1) | S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1817 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1818 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1819 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1820 } else {
1821 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1822 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1823 }
1824
1825 if (sctx->gfx_level >= GFX11) {
1826 unsigned max_allowed_tiles_in_wave;
1827
1828 if (sctx->screen->info.has_dedicated_vram) {
1829 if (sctx->framebuffer.nr_samples == 8)
1830 max_allowed_tiles_in_wave = 6;
1831 else if (sctx->framebuffer.nr_samples == 4)
1832 max_allowed_tiles_in_wave = 13;
1833 else
1834 max_allowed_tiles_in_wave = 0;
1835 } else {
1836 if (sctx->framebuffer.nr_samples == 8)
1837 max_allowed_tiles_in_wave = 7;
1838 else if (sctx->framebuffer.nr_samples == 4)
1839 max_allowed_tiles_in_wave = 15;
1840 else
1841 max_allowed_tiles_in_wave = 0;
1842 }
1843
1844 db_render_control |= S_028000_MAX_ALLOWED_TILES_IN_WAVE(max_allowed_tiles_in_wave);
1845 }
1846 }
1847
1848 /* DB_COUNT_CONTROL (occlusion queries) */
1849 if (sctx->occlusion_query_mode == SI_OCCLUSION_QUERY_MODE_DISABLE ||
1850 sctx->occlusion_queries_disabled) {
1851 /* Occlusion queries disabled. */
1852 if (sctx->gfx_level >= GFX7)
1853 db_count_control |= S_028004_ZPASS_ENABLE(0);
1854 else
1855 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
1856 } else {
1857 /* Occlusion queries enabled. */
1858 if (sctx->gfx_level < GFX12)
1859 db_count_control |= S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1860
1861 if (sctx->gfx_level >= GFX7) {
1862 db_count_control |= S_028004_ZPASS_ENABLE(1) |
1863 S_028004_SLICE_EVEN_ENABLE(1) |
1864 S_028004_SLICE_ODD_ENABLE(1);
1865 }
1866
1867 if (sctx->occlusion_query_mode == SI_OCCLUSION_QUERY_MODE_PRECISE_INTEGER ||
1868 /* Boolean occlusion queries must set PERFECT_ZPASS_COUNTS for depth-only rendering
1869 * without depth writes or when depth testing is disabled. */
1870 (sctx->occlusion_query_mode == SI_OCCLUSION_QUERY_MODE_PRECISE_BOOLEAN &&
1871 (!sctx->queued.named.dsa->depth_enabled ||
1872 (!sctx->queued.named.blend->cb_target_mask &&
1873 !sctx->queued.named.dsa->depth_write_enabled))))
1874 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1875
1876 if (sctx->gfx_level >= GFX10 &&
1877 sctx->occlusion_query_mode != SI_OCCLUSION_QUERY_MODE_CONSERVATIVE_BOOLEAN)
1878 db_count_control |= S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(1);
1879 }
1880
1881 /* This should always be set on GFX11. */
1882 if (sctx->gfx_level >= GFX11)
1883 db_count_control |= S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(1);
1884
1885 db_shader_control |= sctx->ps_db_shader_control;
1886
1887 if (sctx->screen->info.has_export_conflict_bug &&
1888 sctx->queued.named.blend->blend_enable_4bit &&
1889 si_get_num_coverage_samples(sctx) == 1) {
1890 db_shader_control |= S_02880C_OVERRIDE_INTRINSIC_RATE_ENABLE(1) |
1891 S_02880C_OVERRIDE_INTRINSIC_RATE(2);
1892 }
1893
1894 if (sctx->gfx_level >= GFX10_3) {
1895 /* Variable rate shading. */
1896 unsigned mode, log_rate_x, log_rate_y;
1897
1898 if (sctx->allow_flat_shading) {
1899 mode = V_028064_SC_VRS_COMB_MODE_OVERRIDE;
1900 log_rate_x = log_rate_y = 1; /* 2x2 VRS (log2(2) == 1) */
1901 } else {
1902 /* If the shader is using discard, turn off coarse shading because discarding at 2x2 pixel
1903 * granularity degrades quality too much.
1904 *
1905 * The shader writes the VRS rate and we either pass it through or do MIN(shader, 1x1)
1906 * to disable coarse shading.
1907 */
1908 mode = sctx->screen->options.vrs2x2 && G_02880C_KILL_ENABLE(db_shader_control) ?
1909 V_028064_SC_VRS_COMB_MODE_MIN : V_028064_SC_VRS_COMB_MODE_PASSTHRU;
1910 log_rate_x = log_rate_y = 0; /* 1x1 VRS (log2(1) == 0) */
1911 }
1912
1913 if (sctx->gfx_level >= GFX11) {
1914 vrs_override_cntl = S_0283D0_VRS_OVERRIDE_RATE_COMBINER_MODE(mode) |
1915 S_0283D0_VRS_RATE(log_rate_x * 4 + log_rate_y);
1916 } else {
1917 vrs_override_cntl = S_028064_VRS_OVERRIDE_RATE_COMBINER_MODE(mode) |
1918 S_028064_VRS_OVERRIDE_RATE_X(log_rate_x) |
1919 S_028064_VRS_OVERRIDE_RATE_Y(log_rate_y);
1920 }
1921 }
1922
1923 unsigned db_render_override2 =
1924 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1925 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1926 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4) |
1927 S_028010_CENTROID_COMPUTATION_MODE(sctx->gfx_level >= GFX10_3 ? 1 : 0);
1928
1929 if (sctx->gfx_level >= GFX12) {
1930 radeon_begin(&sctx->gfx_cs);
1931 gfx12_begin_context_regs();
1932 gfx12_opt_set_context_reg(R_028000_DB_RENDER_CONTROL, SI_TRACKED_DB_RENDER_CONTROL,
1933 db_render_control);
1934 gfx12_opt_set_context_reg(R_028010_DB_RENDER_OVERRIDE2, SI_TRACKED_DB_RENDER_OVERRIDE2,
1935 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4) |
1936 S_028010_CENTROID_COMPUTATION_MODE(1));
1937 gfx12_opt_set_context_reg(R_028060_DB_COUNT_CONTROL, SI_TRACKED_DB_COUNT_CONTROL,
1938 db_count_control);
1939 gfx12_opt_set_context_reg(R_02806C_DB_SHADER_CONTROL, SI_TRACKED_DB_SHADER_CONTROL,
1940 db_shader_control);
1941 gfx12_opt_set_context_reg(R_0283D0_PA_SC_VRS_OVERRIDE_CNTL,
1942 SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL, vrs_override_cntl);
1943 gfx12_end_context_regs();
1944 radeon_end(); /* don't track context rolls on GFX12 */
1945 } else if (sctx->screen->info.has_set_context_pairs_packed) {
1946 radeon_begin(&sctx->gfx_cs);
1947 gfx11_begin_packed_context_regs();
1948 gfx11_opt_set_context_reg(R_028000_DB_RENDER_CONTROL, SI_TRACKED_DB_RENDER_CONTROL,
1949 db_render_control);
1950 gfx11_opt_set_context_reg(R_028004_DB_COUNT_CONTROL, SI_TRACKED_DB_COUNT_CONTROL,
1951 db_count_control);
1952 gfx11_opt_set_context_reg(R_028010_DB_RENDER_OVERRIDE2, SI_TRACKED_DB_RENDER_OVERRIDE2,
1953 db_render_override2);
1954 gfx11_opt_set_context_reg(R_02880C_DB_SHADER_CONTROL, SI_TRACKED_DB_SHADER_CONTROL,
1955 db_shader_control);
1956 gfx11_opt_set_context_reg(R_0283D0_PA_SC_VRS_OVERRIDE_CNTL,
1957 SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL, vrs_override_cntl);
1958 gfx11_end_packed_context_regs();
1959 radeon_end(); /* don't track context rolls on GFX11 */
1960 } else {
1961 radeon_begin(&sctx->gfx_cs);
1962 radeon_opt_set_context_reg2(R_028000_DB_RENDER_CONTROL, SI_TRACKED_DB_RENDER_CONTROL,
1963 db_render_control, db_count_control);
1964 radeon_opt_set_context_reg(R_028010_DB_RENDER_OVERRIDE2,
1965 SI_TRACKED_DB_RENDER_OVERRIDE2, db_render_override2);
1966 radeon_opt_set_context_reg(R_02880C_DB_SHADER_CONTROL, SI_TRACKED_DB_SHADER_CONTROL,
1967 db_shader_control);
1968
1969 if (sctx->gfx_level >= GFX11) {
1970 radeon_opt_set_context_reg(R_0283D0_PA_SC_VRS_OVERRIDE_CNTL,
1971 SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL, vrs_override_cntl);
1972 } else if (sctx->gfx_level >= GFX10_3) {
1973 radeon_opt_set_context_reg(R_028064_DB_VRS_OVERRIDE_CNTL,
1974 SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL, vrs_override_cntl);
1975 }
1976 radeon_end_update_context_roll();
1977 }
1978 }
1979
1980 /*
1981 * Texture translation
1982 */
1983
si_translate_texformat(struct pipe_screen * screen,enum pipe_format format,const struct util_format_description * desc,int first_non_void)1984 static uint32_t si_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
1985 const struct util_format_description *desc,
1986 int first_non_void)
1987 {
1988 struct si_screen *sscreen = (struct si_screen *)screen;
1989
1990 assert(sscreen->info.gfx_level <= GFX9);
1991
1992 return ac_translate_tex_dataformat(&sscreen->info, desc, first_non_void);
1993 }
1994
is_wrap_mode_legal(struct si_screen * screen,unsigned wrap)1995 static unsigned is_wrap_mode_legal(struct si_screen *screen, unsigned wrap)
1996 {
1997 if (!screen->info.has_3d_cube_border_color_mipmap) {
1998 switch (wrap) {
1999 case PIPE_TEX_WRAP_CLAMP:
2000 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2001 case PIPE_TEX_WRAP_MIRROR_CLAMP:
2002 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
2003 return false;
2004 }
2005 }
2006 return true;
2007 }
2008
si_tex_wrap(unsigned wrap)2009 static unsigned si_tex_wrap(unsigned wrap)
2010 {
2011 switch (wrap) {
2012 default:
2013 case PIPE_TEX_WRAP_REPEAT:
2014 return V_008F30_SQ_TEX_WRAP;
2015 case PIPE_TEX_WRAP_CLAMP:
2016 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
2017 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2018 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
2019 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2020 return V_008F30_SQ_TEX_CLAMP_BORDER;
2021 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2022 return V_008F30_SQ_TEX_MIRROR;
2023 case PIPE_TEX_WRAP_MIRROR_CLAMP:
2024 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
2025 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
2026 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2027 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
2028 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
2029 }
2030 }
2031
si_tex_mipfilter(unsigned filter)2032 static unsigned si_tex_mipfilter(unsigned filter)
2033 {
2034 switch (filter) {
2035 case PIPE_TEX_MIPFILTER_NEAREST:
2036 return V_008F38_SQ_TEX_Z_FILTER_POINT;
2037 case PIPE_TEX_MIPFILTER_LINEAR:
2038 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
2039 default:
2040 case PIPE_TEX_MIPFILTER_NONE:
2041 return V_008F38_SQ_TEX_Z_FILTER_NONE;
2042 }
2043 }
2044
si_tex_compare(unsigned mode,unsigned compare)2045 static unsigned si_tex_compare(unsigned mode, unsigned compare)
2046 {
2047 if (mode == PIPE_TEX_COMPARE_NONE)
2048 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
2049
2050 switch (compare) {
2051 default:
2052 case PIPE_FUNC_NEVER:
2053 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
2054 case PIPE_FUNC_LESS:
2055 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
2056 case PIPE_FUNC_EQUAL:
2057 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
2058 case PIPE_FUNC_LEQUAL:
2059 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2060 case PIPE_FUNC_GREATER:
2061 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
2062 case PIPE_FUNC_NOTEQUAL:
2063 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2064 case PIPE_FUNC_GEQUAL:
2065 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2066 case PIPE_FUNC_ALWAYS:
2067 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2068 }
2069 }
2070
si_tex_dim(struct si_screen * sscreen,struct si_texture * tex,unsigned view_target,unsigned nr_samples)2071 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex, unsigned view_target,
2072 unsigned nr_samples)
2073 {
2074 unsigned res_target = tex->buffer.b.b.target;
2075
2076 if (view_target == PIPE_TEXTURE_CUBE || view_target == PIPE_TEXTURE_CUBE_ARRAY)
2077 res_target = view_target;
2078 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
2079 else if (res_target == PIPE_TEXTURE_CUBE || res_target == PIPE_TEXTURE_CUBE_ARRAY)
2080 res_target = PIPE_TEXTURE_2D_ARRAY;
2081
2082 /* GFX9 allocates 1D textures as 2D. */
2083 if ((res_target == PIPE_TEXTURE_1D || res_target == PIPE_TEXTURE_1D_ARRAY) &&
2084 sscreen->info.gfx_level == GFX9 &&
2085 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
2086 if (res_target == PIPE_TEXTURE_1D)
2087 res_target = PIPE_TEXTURE_2D;
2088 else
2089 res_target = PIPE_TEXTURE_2D_ARRAY;
2090 }
2091
2092 switch (res_target) {
2093 default:
2094 case PIPE_TEXTURE_1D:
2095 return V_008F1C_SQ_RSRC_IMG_1D;
2096 case PIPE_TEXTURE_1D_ARRAY:
2097 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
2098 case PIPE_TEXTURE_2D:
2099 case PIPE_TEXTURE_RECT:
2100 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA : V_008F1C_SQ_RSRC_IMG_2D;
2101 case PIPE_TEXTURE_2D_ARRAY:
2102 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2103 case PIPE_TEXTURE_3D:
2104 return V_008F1C_SQ_RSRC_IMG_3D;
2105 case PIPE_TEXTURE_CUBE:
2106 case PIPE_TEXTURE_CUBE_ARRAY:
2107 return V_008F1C_SQ_RSRC_IMG_CUBE;
2108 }
2109 }
2110
2111 /*
2112 * Format support testing
2113 */
2114
si_is_sampler_format_supported(struct pipe_screen * screen,enum pipe_format format)2115 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
2116 {
2117 struct si_screen *sscreen = (struct si_screen *)screen;
2118 const struct util_format_description *desc = util_format_description(format);
2119
2120 /* Samplers don't support 64 bits per channel. */
2121 if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN &&
2122 desc->channel[0].size == 64)
2123 return false;
2124
2125 if (sscreen->info.gfx_level >= GFX10) {
2126 const struct gfx10_format *fmt = &ac_get_gfx10_format_table(sscreen->info.gfx_level)[format];
2127 if (!fmt->img_format || fmt->buffers_only)
2128 return false;
2129 return true;
2130 }
2131
2132 const int first_non_void = util_format_get_first_non_void_channel(format);
2133
2134 if (si_translate_texformat(screen, format, desc, first_non_void) == ~0U)
2135 return false;
2136
2137 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB &&
2138 desc->nr_channels != 4 && desc->nr_channels != 1)
2139 return false;
2140
2141 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC && !sscreen->info.has_etc_support)
2142 return false;
2143
2144 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED &&
2145 (desc->format == PIPE_FORMAT_G8B8_G8R8_UNORM ||
2146 desc->format == PIPE_FORMAT_B8G8_R8G8_UNORM))
2147 return false;
2148
2149 /* Other "OTHER" layouts are unsupported. */
2150 if (desc->layout == UTIL_FORMAT_LAYOUT_OTHER &&
2151 desc->format != PIPE_FORMAT_R11G11B10_FLOAT &&
2152 desc->format != PIPE_FORMAT_R9G9B9E5_FLOAT)
2153 return false;
2154
2155 /* This must be before using first_non_void. */
2156 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
2157 return true;
2158
2159 if (first_non_void < 0 || first_non_void > 3)
2160 return false;
2161
2162 /* Reject SCALED formats because we don't implement them for CB and do the same for texturing. */
2163 if ((desc->channel[first_non_void].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2164 desc->channel[first_non_void].type == UTIL_FORMAT_TYPE_SIGNED) &&
2165 !desc->channel[first_non_void].normalized &&
2166 !desc->channel[first_non_void].pure_integer)
2167 return false;
2168
2169 /* Reject unsupported 32_*NORM and FIXED formats. */
2170 if (desc->channel[first_non_void].size == 32 &&
2171 (desc->channel[first_non_void].normalized ||
2172 desc->channel[first_non_void].type == UTIL_FORMAT_TYPE_FIXED))
2173 return false;
2174
2175 /* Luminace-alpha formats fail tests on Tahiti. */
2176 if (sscreen->info.gfx_level == GFX6 && util_format_is_luminance_alpha(format))
2177 return false;
2178
2179 /* This format fails on Gfx8/Carrizo´. */
2180 if (sscreen->info.family == CHIP_CARRIZO && format == PIPE_FORMAT_A8R8_UNORM)
2181 return false;
2182
2183 /* Reject unsupported 3x 32-bit formats for CB. */
2184 if (desc->nr_channels == 3 && desc->channel[0].size == 32 && desc->channel[1].size == 32 &&
2185 desc->channel[2].size == 32)
2186 return false;
2187
2188 /* Reject all 64-bit formats. */
2189 if (desc->channel[first_non_void].size == 64)
2190 return false;
2191
2192 return true;
2193 }
2194
si_translate_buffer_dataformat(struct pipe_screen * screen,const struct util_format_description * desc,int first_non_void)2195 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
2196 const struct util_format_description *desc,
2197 int first_non_void)
2198 {
2199 assert(((struct si_screen *)screen)->info.gfx_level <= GFX9);
2200
2201 return ac_translate_buffer_dataformat(desc, first_non_void);
2202 }
2203
si_is_vertex_format_supported(struct pipe_screen * screen,enum pipe_format format,unsigned usage)2204 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format,
2205 unsigned usage)
2206 {
2207 struct si_screen *sscreen = (struct si_screen *)screen;
2208 const struct util_format_description *desc;
2209 int first_non_void;
2210 unsigned data_format;
2211
2212 assert((usage & ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_VERTEX_BUFFER)) ==
2213 0);
2214
2215 desc = util_format_description(format);
2216
2217 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2218 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2219 * for read-only access (with caveats surrounding bounds checks), but
2220 * obviously fails for write access which we have to implement for
2221 * shader images. Luckily, OpenGL doesn't expect this to be supported
2222 * anyway, and so the only impact is on PBO uploads / downloads, which
2223 * shouldn't be expected to be fast for GL_RGB anyway.
2224 */
2225 if (desc->block.bits == 3 * 8 || desc->block.bits == 3 * 16) {
2226 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2227 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2228 if (!usage)
2229 return 0;
2230 }
2231 }
2232
2233 if (sscreen->info.gfx_level >= GFX10) {
2234 const struct gfx10_format *fmt = &ac_get_gfx10_format_table(sscreen->info.gfx_level)[format];
2235 unsigned first_image_only_format = sscreen->info.gfx_level >= GFX11 ? 64 : 128;
2236
2237 if (!fmt->img_format || fmt->img_format >= first_image_only_format)
2238 return 0;
2239 return usage;
2240 }
2241
2242 first_non_void = util_format_get_first_non_void_channel(format);
2243 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2244 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2245 return 0;
2246
2247 return usage;
2248 }
2249
si_is_zs_format_supported(enum pipe_format format)2250 static bool si_is_zs_format_supported(enum pipe_format format)
2251 {
2252 if (format == PIPE_FORMAT_Z16_UNORM_S8_UINT)
2253 return false;
2254
2255 return ac_is_zs_format_supported(format);
2256 }
2257
si_is_reduction_mode_supported(struct pipe_screen * screen,enum pipe_format format)2258 static bool si_is_reduction_mode_supported(struct pipe_screen *screen, enum pipe_format format)
2259 {
2260 struct si_screen *sscreen = (struct si_screen *)screen;
2261
2262 return ac_is_reduction_mode_supported(&sscreen->info, format, true);
2263 }
2264
si_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned usage)2265 static bool si_is_format_supported(struct pipe_screen *screen, enum pipe_format format,
2266 enum pipe_texture_target target, unsigned sample_count,
2267 unsigned storage_sample_count, unsigned usage)
2268 {
2269 struct si_screen *sscreen = (struct si_screen *)screen;
2270 unsigned retval = 0;
2271
2272 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2273 PRINT_ERR("radeonsi: unsupported texture type %d\n", target);
2274 return false;
2275 }
2276
2277 /* Require PIPE_BIND_SAMPLER_VIEW support when PIPE_BIND_RENDER_TARGET
2278 * is requested.
2279 */
2280 if (usage & PIPE_BIND_RENDER_TARGET)
2281 usage |= PIPE_BIND_SAMPLER_VIEW;
2282
2283 if ((target == PIPE_TEXTURE_3D || target == PIPE_TEXTURE_CUBE) &&
2284 !sscreen->info.has_3d_cube_border_color_mipmap)
2285 return false;
2286
2287 if (util_format_get_num_planes(format) >= 2)
2288 return false;
2289
2290 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2291 return false;
2292
2293 if (sample_count > 1) {
2294 if (!screen->caps.texture_multisample)
2295 return false;
2296
2297 /* Only power-of-two sample counts are supported. */
2298 if (!util_is_power_of_two_or_zero(sample_count) ||
2299 !util_is_power_of_two_or_zero(storage_sample_count))
2300 return false;
2301
2302 /* Chips with 1 RB don't increment occlusion queries at 16x MSAA sample rate,
2303 * so don't expose 16 samples there.
2304 *
2305 * EQAA also uses max 8 samples because our FMASK fetches only load 32 bits and
2306 * would need to be changed to 64 bits for 16 samples.
2307 */
2308 const unsigned max_samples = 8;
2309
2310 /* MSAA support without framebuffer attachments. */
2311 if (format == PIPE_FORMAT_NONE && sample_count <= max_samples)
2312 return true;
2313
2314 if (!sscreen->info.has_eqaa_surface_allocator || util_format_is_depth_or_stencil(format)) {
2315 /* Color without EQAA or depth/stencil. */
2316 if (sample_count > max_samples || sample_count != storage_sample_count)
2317 return false;
2318 } else {
2319 /* Color with EQAA. */
2320 if (sample_count > max_samples || storage_sample_count > max_samples)
2321 return false;
2322 }
2323 }
2324
2325 if (usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE)) {
2326 if (target == PIPE_BUFFER) {
2327 retval |= si_is_vertex_format_supported(
2328 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE));
2329 } else {
2330 if (si_is_sampler_format_supported(screen, format))
2331 retval |= usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE);
2332 }
2333 }
2334
2335 if ((usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT |
2336 PIPE_BIND_SHARED | PIPE_BIND_BLENDABLE)) &&
2337 ac_is_colorbuffer_format_supported(sscreen->info.gfx_level, format)) {
2338 retval |= usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT |
2339 PIPE_BIND_SHARED);
2340 if (!util_format_is_pure_integer(format) && !util_format_is_depth_or_stencil(format))
2341 retval |= usage & PIPE_BIND_BLENDABLE;
2342 }
2343
2344 if ((usage & PIPE_BIND_DEPTH_STENCIL) && si_is_zs_format_supported(format)) {
2345 retval |= PIPE_BIND_DEPTH_STENCIL;
2346 }
2347
2348 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2349 retval |= si_is_vertex_format_supported(screen, format, PIPE_BIND_VERTEX_BUFFER);
2350 }
2351
2352 if (usage & PIPE_BIND_INDEX_BUFFER) {
2353 if (format == PIPE_FORMAT_R8_UINT ||
2354 format == PIPE_FORMAT_R16_UINT ||
2355 format == PIPE_FORMAT_R32_UINT)
2356 retval |= PIPE_BIND_INDEX_BUFFER;
2357 }
2358
2359 if ((usage & PIPE_BIND_LINEAR) && !util_format_is_compressed(format) &&
2360 !(usage & PIPE_BIND_DEPTH_STENCIL))
2361 retval |= PIPE_BIND_LINEAR;
2362
2363 if ((usage & PIPE_BIND_SAMPLER_REDUCTION_MINMAX) &&
2364 screen->caps.sampler_reduction_minmax &&
2365 si_is_reduction_mode_supported(screen, format))
2366 retval |= PIPE_BIND_SAMPLER_REDUCTION_MINMAX;
2367
2368 return retval == usage;
2369 }
2370
2371 /*
2372 * framebuffer handling
2373 */
2374
si_choose_spi_color_formats(struct si_surface * surf,unsigned format,unsigned swap,unsigned ntype,bool is_depth)2375 static void si_choose_spi_color_formats(struct si_surface *surf, unsigned format, unsigned swap,
2376 unsigned ntype, bool is_depth)
2377 {
2378 struct ac_spi_color_formats formats = {};
2379
2380 ac_choose_spi_color_formats(format, swap, ntype, is_depth, true, &formats);
2381
2382 surf->spi_shader_col_format = formats.normal;
2383 surf->spi_shader_col_format_alpha = formats.alpha;
2384 surf->spi_shader_col_format_blend = formats.blend;
2385 surf->spi_shader_col_format_blend_alpha = formats.blend_alpha;
2386 }
2387
si_initialize_color_surface(struct si_context * sctx,struct si_surface * surf)2388 static void si_initialize_color_surface(struct si_context *sctx, struct si_surface *surf)
2389 {
2390 struct si_texture *tex = (struct si_texture *)surf->base.texture;
2391 unsigned format, swap, ntype;//, endian;
2392
2393 ntype = ac_get_cb_number_type(surf->base.format);
2394 format = ac_get_cb_format(sctx->gfx_level, surf->base.format);
2395
2396 if (format == V_028C70_COLOR_INVALID) {
2397 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2398 }
2399 assert(format != V_028C70_COLOR_INVALID);
2400 swap = ac_translate_colorswap(sctx->gfx_level, surf->base.format, false);
2401
2402 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2403 if (format == V_028C70_COLOR_8 || format == V_028C70_COLOR_8_8 ||
2404 format == V_028C70_COLOR_8_8_8_8)
2405 surf->color_is_int8 = true;
2406 else if (format == V_028C70_COLOR_10_10_10_2 || format == V_028C70_COLOR_2_10_10_10)
2407 surf->color_is_int10 = true;
2408 }
2409
2410 const struct ac_cb_state cb_state = {
2411 .surf = &tex->surface,
2412 .format = surf->base.format,
2413 .width = surf->width0,
2414 .height = surf->height0,
2415 .first_layer = surf->base.u.tex.first_layer,
2416 .last_layer = surf->base.u.tex.last_layer,
2417 .num_layers = util_max_layer(&tex->buffer.b.b, 0),
2418 .num_samples = tex->buffer.b.b.nr_samples,
2419 .num_storage_samples = tex->buffer.b.b.nr_storage_samples,
2420 .base_level = surf->base.u.tex.level,
2421 .num_levels = tex->buffer.b.b.last_level + 1,
2422 };
2423
2424 ac_init_cb_surface(&sctx->screen->info, &cb_state, &surf->cb);
2425
2426 /* Determine pixel shader export format */
2427 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2428
2429 surf->color_initialized = true;
2430 }
2431
si_init_depth_surface(struct si_context * sctx,struct si_surface * surf)2432 static void si_init_depth_surface(struct si_context *sctx, struct si_surface *surf)
2433 {
2434 struct si_texture *tex = (struct si_texture *)surf->base.texture;
2435 unsigned level = surf->base.u.tex.level;
2436 unsigned format;
2437
2438 format = ac_translate_dbformat(tex->db_render_format);
2439
2440 assert(format != V_028040_Z_24 || sctx->gfx_level < GFX12);
2441 assert(format != V_028040_Z_INVALID);
2442
2443 if (format == V_028040_Z_INVALID)
2444 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2445
2446 /* Use the original Z format, not db_render_format, so that the polygon offset behaves as
2447 * expected by applications.
2448 */
2449 switch (tex->buffer.b.b.format) {
2450 case PIPE_FORMAT_Z16_UNORM:
2451 surf->db_format_index = 0;
2452 break;
2453 default: /* 24-bit */
2454 surf->db_format_index = 1;
2455 break;
2456 case PIPE_FORMAT_Z32_FLOAT:
2457 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2458 surf->db_format_index = 2;
2459 break;
2460 }
2461
2462 const struct ac_ds_state ds_state = {
2463 .surf = &tex->surface,
2464 .va = tex->buffer.gpu_address,
2465 .format = tex->db_render_format,
2466 .width = tex->buffer.b.b.width0,
2467 .height = tex->buffer.b.b.height0,
2468 .level = level,
2469 .num_levels = tex->buffer.b.b.last_level + 1,
2470 .num_samples = tex->buffer.b.b.nr_samples,
2471 .first_layer = surf->base.u.tex.first_layer,
2472 .last_layer = surf->base.u.tex.last_layer,
2473 .allow_expclear = true,
2474 .htile_enabled = sctx->gfx_level < GFX12 && si_htile_enabled(tex, level, PIPE_MASK_ZS),
2475 .htile_stencil_disabled = tex->htile_stencil_disabled,
2476 };
2477
2478 ac_init_ds_surface(&sctx->screen->info, &ds_state, &surf->ds);
2479
2480 surf->depth_initialized = true;
2481 }
2482
si_dec_framebuffer_counters(const struct pipe_framebuffer_state * state)2483 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2484 {
2485 for (int i = 0; i < state->nr_cbufs; ++i) {
2486 struct si_surface *surf = NULL;
2487 struct si_texture *tex;
2488
2489 if (!state->cbufs[i])
2490 continue;
2491 surf = (struct si_surface *)state->cbufs[i];
2492 tex = (struct si_texture *)surf->base.texture;
2493
2494 p_atomic_dec(&tex->framebuffers_bound);
2495 }
2496 }
2497
si_mark_display_dcc_dirty(struct si_context * sctx,struct si_texture * tex)2498 void si_mark_display_dcc_dirty(struct si_context *sctx, struct si_texture *tex)
2499 {
2500 assert(sctx->gfx_level < GFX12);
2501
2502 if (!tex->surface.display_dcc_offset || tex->displayable_dcc_dirty)
2503 return;
2504
2505 if (!(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) {
2506 struct hash_entry *entry = _mesa_hash_table_search(sctx->dirty_implicit_resources, tex);
2507 if (!entry) {
2508 struct pipe_resource *dummy = NULL;
2509 pipe_resource_reference(&dummy, &tex->buffer.b.b);
2510 _mesa_hash_table_insert(sctx->dirty_implicit_resources, tex, tex);
2511 }
2512 }
2513 tex->displayable_dcc_dirty = true;
2514 }
2515
si_update_display_dcc_dirty(struct si_context * sctx)2516 static void si_update_display_dcc_dirty(struct si_context *sctx)
2517 {
2518 const struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2519
2520 for (unsigned i = 0; i < state->nr_cbufs; i++) {
2521 if (state->cbufs[i])
2522 si_mark_display_dcc_dirty(sctx, (struct si_texture *)state->cbufs[i]->texture);
2523 }
2524 }
2525
si_set_framebuffer_state(struct pipe_context * ctx,const struct pipe_framebuffer_state * state)2526 static void si_set_framebuffer_state(struct pipe_context *ctx,
2527 const struct pipe_framebuffer_state *state)
2528 {
2529 struct si_context *sctx = (struct si_context *)ctx;
2530 struct si_surface *surf = NULL;
2531 struct si_texture *tex;
2532 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2533 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2534 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2535 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2536 bool old_has_stencil =
2537 old_has_zsbuf &&
2538 ((struct si_texture *)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2539 uint8_t old_db_format_index =
2540 old_has_zsbuf ?
2541 ((struct si_surface *)sctx->framebuffer.state.zsbuf)->db_format_index : -1;
2542 bool old_has_hiz_his = sctx->framebuffer.has_hiz_his;
2543 int i;
2544
2545 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2546 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2547 * We could implement the full workaround here, but it's a useless case.
2548 */
2549 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2550 unreachable("the framebuffer shouldn't have zero area");
2551 return;
2552 }
2553
2554 si_fb_barrier_after_rendering(sctx, SI_FB_BARRIER_SYNC_ALL);
2555
2556 /* Disable DCC if the formats are incompatible. */
2557 if (sctx->gfx_level >= GFX8 && sctx->gfx_level < GFX11) {
2558 for (i = 0; i < state->nr_cbufs; i++) {
2559 if (!state->cbufs[i])
2560 continue;
2561
2562 surf = (struct si_surface *)state->cbufs[i];
2563 tex = (struct si_texture *)surf->base.texture;
2564
2565 if (!surf->dcc_incompatible)
2566 continue;
2567
2568 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2569 if (!si_texture_disable_dcc(sctx, tex))
2570 si_decompress_dcc(sctx, tex);
2571
2572 surf->dcc_incompatible = false;
2573 }
2574 }
2575
2576 /* Take the maximum of the old and new count. If the new count is lower,
2577 * dirtying is needed to disable the unbound colorbuffers.
2578 */
2579 sctx->framebuffer.dirty_cbufs |=
2580 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2581 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2582
2583 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2584 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2585
2586 /* The framebuffer state must be set before the barrier. */
2587 si_fb_barrier_before_rendering(sctx);
2588
2589 /* Recompute layers because frontends and utils might not set it. */
2590 sctx->framebuffer.state.layers = util_framebuffer_get_num_layers(state);
2591
2592 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2593 sctx->framebuffer.spi_shader_col_format = 0;
2594 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2595 sctx->framebuffer.spi_shader_col_format_blend = 0;
2596 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2597 sctx->framebuffer.color_is_int8 = 0;
2598 sctx->framebuffer.color_is_int10 = 0;
2599
2600 sctx->framebuffer.compressed_cb_mask = 0;
2601 sctx->framebuffer.uncompressed_cb_mask = 0;
2602 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2603 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2604 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2605 sctx->framebuffer.any_dst_linear = false;
2606 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2607 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2608 sctx->framebuffer.all_DCC_pipe_aligned = true;
2609 sctx->framebuffer.has_dcc_msaa = false;
2610 sctx->framebuffer.min_bytes_per_pixel = 0;
2611 sctx->framebuffer.disable_vrs_flat_shading = false;
2612 sctx->framebuffer.has_stencil = false;
2613 sctx->framebuffer.has_hiz_his = false;
2614
2615 for (i = 0; i < state->nr_cbufs; i++) {
2616 if (!state->cbufs[i])
2617 continue;
2618
2619 surf = (struct si_surface *)state->cbufs[i];
2620 tex = (struct si_texture *)surf->base.texture;
2621
2622 if (!surf->color_initialized) {
2623 si_initialize_color_surface(sctx, surf);
2624 }
2625
2626 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2627 sctx->framebuffer.spi_shader_col_format |= surf->spi_shader_col_format << (i * 4);
2628 sctx->framebuffer.spi_shader_col_format_alpha |= surf->spi_shader_col_format_alpha << (i * 4);
2629 sctx->framebuffer.spi_shader_col_format_blend |= surf->spi_shader_col_format_blend << (i * 4);
2630 sctx->framebuffer.spi_shader_col_format_blend_alpha |= surf->spi_shader_col_format_blend_alpha
2631 << (i * 4);
2632
2633 if (surf->color_is_int8)
2634 sctx->framebuffer.color_is_int8 |= 1 << i;
2635 if (surf->color_is_int10)
2636 sctx->framebuffer.color_is_int10 |= 1 << i;
2637
2638 if (tex->surface.fmask_offset)
2639 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2640 else
2641 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2642
2643 /* Don't update nr_color_samples for non-AA buffers.
2644 * (e.g. destination of MSAA resolve)
2645 */
2646 if (tex->buffer.b.b.nr_samples >= 2 &&
2647 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
2648 sctx->framebuffer.nr_color_samples =
2649 MIN2(sctx->framebuffer.nr_color_samples, tex->buffer.b.b.nr_storage_samples);
2650 sctx->framebuffer.nr_color_samples = MAX2(1, sctx->framebuffer.nr_color_samples);
2651 }
2652
2653 if (tex->surface.is_linear)
2654 sctx->framebuffer.any_dst_linear = true;
2655
2656 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
2657 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2658
2659 if (sctx->gfx_level >= GFX9 && sctx->gfx_level < GFX12 &&
2660 !tex->surface.u.gfx9.color.dcc.pipe_aligned)
2661 sctx->framebuffer.all_DCC_pipe_aligned = false;
2662
2663 if (tex->buffer.b.b.nr_storage_samples >= 2)
2664 sctx->framebuffer.has_dcc_msaa = true;
2665 }
2666
2667 p_atomic_inc(&tex->framebuffers_bound);
2668
2669 /* Update the minimum but don't keep 0. */
2670 if (!sctx->framebuffer.min_bytes_per_pixel ||
2671 tex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
2672 sctx->framebuffer.min_bytes_per_pixel = tex->surface.bpe;
2673
2674 /* Disable VRS flat shading where it decreases performance.
2675 * This gives the best results for slow clears for AMD_TEST=blitperf on Navi31.
2676 */
2677 if ((sctx->framebuffer.nr_samples == 8 && tex->surface.bpe != 2) ||
2678 (tex->surface.thick_tiling && tex->surface.bpe == 4 &&
2679 util_format_get_nr_components(surf->base.format) == 4))
2680 sctx->framebuffer.disable_vrs_flat_shading = true;
2681 }
2682
2683 struct si_texture *zstex = NULL;
2684
2685 if (state->zsbuf) {
2686 surf = (struct si_surface *)state->zsbuf;
2687 zstex = (struct si_texture *)surf->base.texture;
2688
2689 if (!surf->depth_initialized) {
2690 si_init_depth_surface(sctx, surf);
2691 }
2692
2693 if (sctx->gfx_level < GFX12 &&
2694 vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level, PIPE_MASK_ZS))
2695 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2696
2697 /* Update the minimum but don't keep 0. */
2698 if (!sctx->framebuffer.min_bytes_per_pixel ||
2699 zstex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
2700 sctx->framebuffer.min_bytes_per_pixel = zstex->surface.bpe;
2701
2702 /* Update polygon offset based on the Z format. */
2703 if (sctx->queued.named.rasterizer->uses_poly_offset &&
2704 surf->db_format_index != old_db_format_index)
2705 sctx->dirty_atoms |= SI_STATE_BIT(rasterizer);
2706
2707 if (util_format_has_stencil(util_format_description(zstex->buffer.b.b.format)))
2708 sctx->framebuffer.has_stencil = true;
2709
2710 if (sctx->gfx_level == GFX12 && !sctx->screen->options.alt_hiz_logic &&
2711 sctx->framebuffer.has_stencil && sctx->queued.named.dsa->stencil_enabled)
2712 zstex->force_disable_hiz_his = true;
2713
2714 if (sctx->gfx_level >= GFX12) {
2715 sctx->framebuffer.has_hiz_his = (zstex->surface.u.gfx9.zs.hiz.offset ||
2716 zstex->surface.u.gfx9.zs.his.offset) &&
2717 !zstex->force_disable_hiz_his;
2718 }
2719 }
2720
2721 si_update_ps_colorbuf0_slot(sctx);
2722 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2723 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2724
2725 /* NGG cull state uses the sample count. */
2726 if (sctx->screen->use_ngg_culling)
2727 si_mark_atom_dirty(sctx, &sctx->atoms.s.ngg_cull_state);
2728
2729 if (sctx->screen->dpbb_allowed)
2730 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2731
2732 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear ||
2733 sctx->framebuffer.has_hiz_his != old_has_hiz_his)
2734 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2735
2736 if (sctx->screen->info.has_out_of_order_rast &&
2737 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2738 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2739 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2740 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2741
2742 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2743 struct pipe_constant_buffer constbuf = {0};
2744
2745 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2746 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
2747
2748 if (!sctx->sample_pos_buffer) {
2749 sctx->sample_pos_buffer = pipe_buffer_create_with_data(&sctx->b, 0, PIPE_USAGE_DEFAULT,
2750 sizeof(sctx->sample_positions),
2751 &sctx->sample_positions);
2752 }
2753 constbuf.buffer = sctx->sample_pos_buffer;
2754
2755 /* Set sample locations as fragment shader constants. */
2756 switch (sctx->framebuffer.nr_samples) {
2757 case 1:
2758 constbuf.buffer_offset = 0;
2759 break;
2760 case 2:
2761 constbuf.buffer_offset =
2762 (uint8_t *)sctx->sample_positions.x2 - (uint8_t *)sctx->sample_positions.x1;
2763 break;
2764 case 4:
2765 constbuf.buffer_offset =
2766 (uint8_t *)sctx->sample_positions.x4 - (uint8_t *)sctx->sample_positions.x1;
2767 break;
2768 case 8:
2769 constbuf.buffer_offset =
2770 (uint8_t *)sctx->sample_positions.x8 - (uint8_t *)sctx->sample_positions.x1;
2771 break;
2772 case 16:
2773 constbuf.buffer_offset =
2774 (uint8_t *)sctx->sample_positions.x16 - (uint8_t *)sctx->sample_positions.x1;
2775 break;
2776 default:
2777 PRINT_ERR("Requested an invalid number of samples %i.\n", sctx->framebuffer.nr_samples);
2778 assert(0);
2779 }
2780 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2781 si_set_internal_const_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2782
2783 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_locations);
2784 }
2785
2786 si_ps_key_update_framebuffer(sctx);
2787 si_ps_key_update_framebuffer_blend_dsa_rasterizer(sctx);
2788 si_ps_key_update_framebuffer_rasterizer_sample_shading(sctx);
2789 si_vs_ps_key_update_rast_prim_smooth_stipple(sctx);
2790 si_update_ps_inputs_read_or_disabled(sctx);
2791 si_update_vrs_flat_shading(sctx);
2792 sctx->do_update_shaders = true;
2793
2794 if (sctx->gfx_level < GFX12 && !sctx->decompression_enabled) {
2795 /* Prevent textures decompression when the framebuffer state
2796 * changes come from the decompression passes themselves.
2797 */
2798 sctx->need_check_render_feedback = true;
2799 }
2800 }
2801
gfx6_emit_framebuffer_state(struct si_context * sctx,unsigned index)2802 static void gfx6_emit_framebuffer_state(struct si_context *sctx, unsigned index)
2803 {
2804 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
2805 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2806 unsigned i, nr_cbufs = state->nr_cbufs;
2807 struct si_texture *tex = NULL;
2808 struct si_surface *cb = NULL;
2809 bool is_msaa_resolve = state->nr_cbufs == 2 &&
2810 state->cbufs[0] && state->cbufs[0]->texture->nr_samples > 1 &&
2811 state->cbufs[1] && state->cbufs[1]->texture->nr_samples <= 1;
2812
2813 /* CB can't do MSAA resolve on gfx11. */
2814 assert(!is_msaa_resolve || sctx->gfx_level < GFX11);
2815
2816 radeon_begin(cs);
2817
2818 /* Colorbuffers. */
2819 for (i = 0; i < nr_cbufs; i++) {
2820 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2821 continue;
2822
2823 /* RB+ depth-only rendering. See the comment where we set rbplus_depth_only_opt for more
2824 * information.
2825 */
2826 if (i == 0 &&
2827 sctx->screen->info.rbplus_allowed &&
2828 !sctx->queued.named.blend->cb_target_mask) {
2829 radeon_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C,
2830 (sctx->gfx_level >= GFX11 ?
2831 S_028C70_FORMAT_GFX11(V_028C70_COLOR_32) :
2832 S_028C70_FORMAT_GFX6(V_028C70_COLOR_32)) |
2833 S_028C70_NUMBER_TYPE(V_028C70_NUMBER_FLOAT));
2834 continue;
2835 }
2836
2837 cb = (struct si_surface *)state->cbufs[i];
2838 if (!cb) {
2839 radeon_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C,
2840 sctx->gfx_level >= GFX11 ?
2841 S_028C70_FORMAT_GFX11(V_028C70_COLOR_INVALID) :
2842 S_028C70_FORMAT_GFX6(V_028C70_COLOR_INVALID));
2843 continue;
2844 }
2845
2846 tex = (struct si_texture *)cb->base.texture;
2847 radeon_add_to_buffer_list(
2848 sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE | RADEON_USAGE_CB_NEEDS_IMPLICIT_SYNC |
2849 (tex->buffer.b.b.nr_samples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA : RADEON_PRIO_COLOR_BUFFER));
2850
2851 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
2852 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, tex->cmask_buffer,
2853 RADEON_USAGE_READWRITE | RADEON_USAGE_CB_NEEDS_IMPLICIT_SYNC |
2854 RADEON_PRIO_SEPARATE_META);
2855 }
2856
2857 /* Compute mutable surface parameters. */
2858 const struct ac_mutable_cb_state mutable_cb_state = {
2859 .surf = &tex->surface,
2860 .cb = &cb->cb,
2861 .va = tex->buffer.gpu_address,
2862 .base_level = cb->base.u.tex.level,
2863 .num_samples = cb->base.texture->nr_samples,
2864 .fmask_enabled = !!tex->surface.fmask_offset,
2865 /* CMASK and fast clears are configured elsewhere. */
2866 .cmask_enabled = false,
2867 .fast_clear_enabled = false,
2868 .dcc_enabled = vi_dcc_enabled(tex, cb->base.u.tex.level) &&
2869 (i != 1 || !is_msaa_resolve),
2870 };
2871 struct ac_cb_surface cb_surf;
2872
2873 ac_set_mutable_cb_surface_fields(&sctx->screen->info, &mutable_cb_state, &cb_surf);
2874
2875 cb_surf.cb_color_info |= tex->cb_color_info;
2876
2877 if (sctx->gfx_level < GFX11) {
2878 if (tex->swap_rgb_to_bgr) {
2879 /* Swap R and B channels. */
2880 static unsigned rgb_to_bgr[4] = {
2881 [V_028C70_SWAP_STD] = V_028C70_SWAP_ALT,
2882 [V_028C70_SWAP_ALT] = V_028C70_SWAP_STD,
2883 [V_028C70_SWAP_STD_REV] = V_028C70_SWAP_ALT_REV,
2884 [V_028C70_SWAP_ALT_REV] = V_028C70_SWAP_STD_REV,
2885 };
2886 unsigned swap = rgb_to_bgr[G_028C70_COMP_SWAP(cb_surf.cb_color_info)];
2887
2888 cb_surf.cb_color_info &= C_028C70_COMP_SWAP;
2889 cb_surf.cb_color_info |= S_028C70_COMP_SWAP(swap);
2890 }
2891
2892 if (cb->base.u.tex.level > 0)
2893 cb_surf.cb_color_info &= C_028C70_FAST_CLEAR;
2894 else
2895 cb_surf.cb_color_cmask = tex->cmask_base_address_reg;
2896 }
2897
2898 if (sctx->gfx_level >= GFX11) {
2899 radeon_set_context_reg(R_028C60_CB_COLOR0_BASE + i * 0x3C, cb_surf.cb_color_base);
2900
2901 radeon_set_context_reg_seq(R_028C6C_CB_COLOR0_VIEW + i * 0x3C, 4);
2902 radeon_emit(cb_surf.cb_color_view); /* CB_COLOR0_VIEW */
2903 radeon_emit(cb_surf.cb_color_info); /* CB_COLOR0_INFO */
2904 radeon_emit(cb_surf.cb_color_attrib); /* CB_COLOR0_ATTRIB */
2905 radeon_emit(cb_surf.cb_dcc_control); /* CB_COLOR0_FDCC_CONTROL */
2906
2907 radeon_set_context_reg(R_028C94_CB_COLOR0_DCC_BASE + i * 0x3C, cb_surf.cb_dcc_base);
2908 radeon_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_surf.cb_color_base >> 32);
2909 radeon_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_surf.cb_dcc_base >> 32);
2910 radeon_set_context_reg(R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb_surf.cb_color_attrib2);
2911 radeon_set_context_reg(R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_surf.cb_color_attrib3);
2912 } else if (sctx->gfx_level >= GFX10) {
2913 radeon_set_context_reg_seq(R_028C60_CB_COLOR0_BASE + i * 0x3C, 14);
2914 radeon_emit(cb_surf.cb_color_base); /* CB_COLOR0_BASE */
2915 radeon_emit(0); /* hole */
2916 radeon_emit(0); /* hole */
2917 radeon_emit(cb_surf.cb_color_view); /* CB_COLOR0_VIEW */
2918 radeon_emit(cb_surf.cb_color_info); /* CB_COLOR0_INFO */
2919 radeon_emit(cb_surf.cb_color_attrib); /* CB_COLOR0_ATTRIB */
2920 radeon_emit(cb_surf.cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2921 radeon_emit(cb_surf.cb_color_cmask); /* CB_COLOR0_CMASK */
2922 radeon_emit(0); /* hole */
2923 radeon_emit(cb_surf.cb_color_fmask); /* CB_COLOR0_FMASK */
2924 radeon_emit(0); /* hole */
2925 radeon_emit(tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2926 radeon_emit(tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2927 radeon_emit(cb_surf.cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2928
2929 radeon_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_surf.cb_color_base >> 32);
2930 radeon_set_context_reg(R_028E60_CB_COLOR0_CMASK_BASE_EXT + i * 4,
2931 cb_surf.cb_color_cmask >> 32);
2932 radeon_set_context_reg(R_028E80_CB_COLOR0_FMASK_BASE_EXT + i * 4,
2933 cb_surf.cb_color_fmask >> 32);
2934 radeon_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_surf.cb_dcc_base >> 32);
2935 radeon_set_context_reg(R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb_surf.cb_color_attrib2);
2936 radeon_set_context_reg(R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_surf.cb_color_attrib3);
2937 } else if (sctx->gfx_level == GFX9) {
2938 radeon_set_context_reg_seq(R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
2939 radeon_emit(cb_surf.cb_color_base); /* CB_COLOR0_BASE */
2940 radeon_emit(S_028C64_BASE_256B(cb_surf.cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
2941 radeon_emit(cb_surf.cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
2942 radeon_emit(cb_surf.cb_color_view); /* CB_COLOR0_VIEW */
2943 radeon_emit(cb_surf.cb_color_info); /* CB_COLOR0_INFO */
2944 radeon_emit(cb_surf.cb_color_attrib); /* CB_COLOR0_ATTRIB */
2945 radeon_emit(cb_surf.cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2946 radeon_emit(cb_surf.cb_color_cmask); /* CB_COLOR0_CMASK */
2947 radeon_emit(S_028C80_BASE_256B(cb_surf.cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
2948 radeon_emit(cb_surf.cb_color_fmask); /* CB_COLOR0_FMASK */
2949 radeon_emit(S_028C88_BASE_256B(cb_surf.cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
2950 radeon_emit(tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2951 radeon_emit(tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2952 radeon_emit(cb_surf.cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2953 radeon_emit(S_028C98_BASE_256B(cb_surf.cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
2954
2955 radeon_set_context_reg(R_0287A0_CB_MRT0_EPITCH + i * 4, cb_surf.cb_mrt_epitch);
2956 } else {
2957 /* GFX6-8 */
2958 radeon_set_context_reg_seq(R_028C60_CB_COLOR0_BASE + i * 0x3C,
2959 sctx->gfx_level >= GFX8 ? 14 : 13);
2960 radeon_emit(cb_surf.cb_color_base); /* CB_COLOR0_BASE */
2961 radeon_emit(cb_surf.cb_color_pitch); /* CB_COLOR0_PITCH */
2962 radeon_emit(cb_surf.cb_color_slice); /* CB_COLOR0_SLICE */
2963 radeon_emit(cb_surf.cb_color_view); /* CB_COLOR0_VIEW */
2964 radeon_emit(cb_surf.cb_color_info); /* CB_COLOR0_INFO */
2965 radeon_emit(cb_surf.cb_color_attrib); /* CB_COLOR0_ATTRIB */
2966 radeon_emit(cb_surf.cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2967 radeon_emit(cb_surf.cb_color_cmask); /* CB_COLOR0_CMASK */
2968 radeon_emit(tex->surface.u.legacy.color.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
2969 radeon_emit(cb_surf.cb_color_fmask); /* CB_COLOR0_FMASK */
2970 radeon_emit(cb_surf.cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
2971 radeon_emit(tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2972 radeon_emit(tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2973
2974 if (sctx->gfx_level >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */
2975 radeon_emit(cb_surf.cb_dcc_base);
2976 }
2977 }
2978 for (; i < 8; i++)
2979 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2980 radeon_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2981
2982 /* ZS buffer. */
2983 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2984 struct si_surface *zb = (struct si_surface *)state->zsbuf;
2985 struct si_texture *tex = (struct si_texture *)zb->base.texture;
2986
2987 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE |
2988 (zb->base.texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA
2989 : RADEON_PRIO_DEPTH_BUFFER));
2990
2991 const unsigned level = zb->base.u.tex.level;
2992
2993 /* Set mutable fields. */
2994 const struct ac_mutable_ds_state mutable_ds_state = {
2995 .ds = &zb->ds,
2996 .format = tex->db_render_format,
2997 .tc_compat_htile_enabled = vi_tc_compat_htile_enabled(tex, level, PIPE_MASK_ZS),
2998 .zrange_precision = tex->depth_clear_value[level] != 0,
2999 };
3000 struct ac_ds_surface ds;
3001
3002 ac_set_mutable_ds_surface_fields(&sctx->screen->info, &mutable_ds_state, &ds);
3003
3004 if (sctx->gfx_level >= GFX10) {
3005 radeon_set_context_reg(R_028014_DB_HTILE_DATA_BASE, ds.u.gfx6.db_htile_data_base);
3006 radeon_set_context_reg(R_02801C_DB_DEPTH_SIZE_XY, ds.db_depth_size);
3007
3008 if (sctx->gfx_level >= GFX11) {
3009 radeon_set_context_reg_seq(R_028040_DB_Z_INFO, 6);
3010 } else {
3011 radeon_set_context_reg_seq(R_02803C_DB_DEPTH_INFO, 7);
3012 radeon_emit(S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3013 }
3014 radeon_emit(ds.db_z_info); /* DB_Z_INFO */
3015 radeon_emit(ds.db_stencil_info); /* DB_STENCIL_INFO */
3016 radeon_emit(ds.db_depth_base); /* DB_Z_READ_BASE */
3017 radeon_emit(ds.db_stencil_base); /* DB_STENCIL_READ_BASE */
3018 radeon_emit(ds.db_depth_base); /* DB_Z_WRITE_BASE */
3019 radeon_emit(ds.db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3020
3021 radeon_set_context_reg_seq(R_028068_DB_Z_READ_BASE_HI, 5);
3022 radeon_emit(ds.db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
3023 radeon_emit(ds.db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
3024 radeon_emit(ds.db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
3025 radeon_emit(ds.db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
3026 radeon_emit(ds.u.gfx6.db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
3027 } else if (sctx->gfx_level == GFX9) {
3028 radeon_set_context_reg_seq(R_028014_DB_HTILE_DATA_BASE, 3);
3029 radeon_emit(ds.u.gfx6.db_htile_data_base); /* DB_HTILE_DATA_BASE */
3030 radeon_emit(S_028018_BASE_HI(ds.u.gfx6.db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3031 radeon_emit(ds.db_depth_size); /* DB_DEPTH_SIZE */
3032
3033 radeon_set_context_reg_seq(R_028038_DB_Z_INFO, 10);
3034 radeon_emit(ds.db_z_info); /* DB_Z_INFO */
3035 radeon_emit(ds.db_stencil_info); /* DB_STENCIL_INFO */
3036 radeon_emit(ds.db_depth_base); /* DB_Z_READ_BASE */
3037 radeon_emit(S_028044_BASE_HI(ds.db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3038 radeon_emit(ds.db_stencil_base); /* DB_STENCIL_READ_BASE */
3039 radeon_emit(S_02804C_BASE_HI(ds.db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3040 radeon_emit(ds.db_depth_base); /* DB_Z_WRITE_BASE */
3041 radeon_emit(S_028054_BASE_HI(ds.db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3042 radeon_emit(ds.db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3043 radeon_emit(S_02805C_BASE_HI(ds.db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3044
3045 radeon_set_context_reg_seq(R_028068_DB_Z_INFO2, 2);
3046 radeon_emit(ds.u.gfx6.db_z_info2); /* DB_Z_INFO2 */
3047 radeon_emit(ds.u.gfx6.db_stencil_info2); /* DB_STENCIL_INFO2 */
3048 } else {
3049 /* GFX6-GFX8 */
3050 radeon_set_context_reg(R_028014_DB_HTILE_DATA_BASE, ds.u.gfx6.db_htile_data_base);
3051
3052 radeon_set_context_reg_seq(R_02803C_DB_DEPTH_INFO, 9);
3053 radeon_emit(ds.u.gfx6.db_depth_info); /* DB_DEPTH_INFO */
3054 radeon_emit(ds.db_z_info); /* DB_Z_INFO */
3055 radeon_emit(ds.db_stencil_info); /* DB_STENCIL_INFO */
3056 radeon_emit(ds.db_depth_base); /* DB_Z_READ_BASE */
3057 radeon_emit(ds.db_stencil_base); /* DB_STENCIL_READ_BASE */
3058 radeon_emit(ds.db_depth_base); /* DB_Z_WRITE_BASE */
3059 radeon_emit(ds.db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3060 radeon_emit(ds.db_depth_size); /* DB_DEPTH_SIZE */
3061 radeon_emit(ds.u.gfx6.db_depth_slice); /* DB_DEPTH_SLICE */
3062 }
3063
3064 radeon_set_context_reg_seq(R_028028_DB_STENCIL_CLEAR, 2);
3065 radeon_emit(tex->stencil_clear_value[level]); /* R_028028_DB_STENCIL_CLEAR */
3066 radeon_emit(fui(tex->depth_clear_value[level])); /* R_02802C_DB_DEPTH_CLEAR */
3067
3068 radeon_set_context_reg(R_028008_DB_DEPTH_VIEW, ds.db_depth_view);
3069 radeon_set_context_reg(R_028ABC_DB_HTILE_SURFACE, ds.u.gfx6.db_htile_surface);
3070 } else if (sctx->framebuffer.dirty_zsbuf) {
3071 if (sctx->gfx_level == GFX9)
3072 radeon_set_context_reg_seq(R_028038_DB_Z_INFO, 2);
3073 else
3074 radeon_set_context_reg_seq(R_028040_DB_Z_INFO, 2);
3075
3076 /* Gfx11+: DB_Z_INFO.NUM_SAMPLES should match the framebuffer samples if no Z/S is bound.
3077 * It determines the sample count for VRS, primitive-ordered pixel shading, and occlusion
3078 * queries.
3079 */
3080 radeon_emit(S_028040_FORMAT(V_028040_Z_INVALID) | /* DB_Z_INFO */
3081 S_028040_NUM_SAMPLES(sctx->gfx_level >= GFX11 ? sctx->framebuffer.log_samples : 0));
3082 radeon_emit(S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3083 }
3084
3085 /* Framebuffer dimensions. */
3086 /* PA_SC_WINDOW_SCISSOR_TL is set to 0,0 in gfx*_init_gfx_preamble_state */
3087 radeon_set_context_reg(R_028208_PA_SC_WINDOW_SCISSOR_BR,
3088 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3089
3090 if (sctx->screen->dpbb_allowed &&
3091 sctx->screen->pbb_context_states_per_bin > 1)
3092 radeon_event_write(V_028A90_BREAK_BATCH);
3093
3094 radeon_end();
3095
3096 si_update_display_dcc_dirty(sctx);
3097
3098 sctx->framebuffer.dirty_cbufs = 0;
3099 sctx->framebuffer.dirty_zsbuf = false;
3100 }
3101
gfx11_dgpu_emit_framebuffer_state(struct si_context * sctx,unsigned index)3102 static void gfx11_dgpu_emit_framebuffer_state(struct si_context *sctx, unsigned index)
3103 {
3104 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
3105 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3106 unsigned i, nr_cbufs = state->nr_cbufs;
3107 struct si_texture *tex = NULL;
3108 struct si_surface *cb = NULL;
3109 bool is_msaa_resolve = state->nr_cbufs == 2 &&
3110 state->cbufs[0] && state->cbufs[0]->texture->nr_samples > 1 &&
3111 state->cbufs[1] && state->cbufs[1]->texture->nr_samples <= 1;
3112
3113 /* CB can't do MSAA resolve on gfx11. */
3114 assert(!is_msaa_resolve);
3115
3116 radeon_begin(cs);
3117 gfx11_begin_packed_context_regs();
3118
3119 /* Colorbuffers. */
3120 for (i = 0; i < nr_cbufs; i++) {
3121 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3122 continue;
3123
3124 /* RB+ depth-only rendering. See the comment where we set rbplus_depth_only_opt for more
3125 * information.
3126 */
3127 if (i == 0 &&
3128 sctx->screen->info.rbplus_allowed &&
3129 !sctx->queued.named.blend->cb_target_mask) {
3130 gfx11_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C,
3131 S_028C70_FORMAT_GFX11(V_028C70_COLOR_32) |
3132 S_028C70_NUMBER_TYPE(V_028C70_NUMBER_FLOAT));
3133 continue;
3134 }
3135
3136 cb = (struct si_surface *)state->cbufs[i];
3137 if (!cb) {
3138 gfx11_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C,
3139 S_028C70_FORMAT_GFX11(V_028C70_COLOR_INVALID));
3140 continue;
3141 }
3142
3143 tex = (struct si_texture *)cb->base.texture;
3144 radeon_add_to_buffer_list(
3145 sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE | RADEON_USAGE_CB_NEEDS_IMPLICIT_SYNC |
3146 (tex->buffer.b.b.nr_samples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA : RADEON_PRIO_COLOR_BUFFER));
3147
3148 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3149 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, tex->cmask_buffer,
3150 RADEON_USAGE_READWRITE | RADEON_USAGE_CB_NEEDS_IMPLICIT_SYNC |
3151 RADEON_PRIO_SEPARATE_META);
3152 }
3153
3154 /* Compute mutable surface parameters. */
3155 const struct ac_mutable_cb_state mutable_cb_state = {
3156 .surf = &tex->surface,
3157 .cb = &cb->cb,
3158 .va = tex->buffer.gpu_address,
3159 .num_samples = cb->base.texture->nr_samples,
3160 .dcc_enabled = vi_dcc_enabled(tex, cb->base.u.tex.level),
3161 };
3162 struct ac_cb_surface cb_surf;
3163
3164 ac_set_mutable_cb_surface_fields(&sctx->screen->info, &mutable_cb_state, &cb_surf);
3165
3166 cb_surf.cb_color_info |= tex->cb_color_info;
3167
3168 gfx11_set_context_reg(R_028C60_CB_COLOR0_BASE + i * 0x3C, cb_surf.cb_color_base);
3169 gfx11_set_context_reg(R_028C6C_CB_COLOR0_VIEW + i * 0x3C, cb_surf.cb_color_view);
3170 gfx11_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C, cb_surf.cb_color_info);
3171 gfx11_set_context_reg(R_028C74_CB_COLOR0_ATTRIB + i * 0x3C, cb_surf.cb_color_attrib);
3172 gfx11_set_context_reg(R_028C78_CB_COLOR0_DCC_CONTROL + i * 0x3C, cb_surf.cb_dcc_control);
3173 gfx11_set_context_reg(R_028C94_CB_COLOR0_DCC_BASE + i * 0x3C, cb_surf.cb_dcc_base);
3174 gfx11_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_surf.cb_color_base >> 32);
3175 gfx11_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_surf.cb_dcc_base >> 32);
3176 gfx11_set_context_reg(R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb_surf.cb_color_attrib2);
3177 gfx11_set_context_reg(R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_surf.cb_color_attrib3);
3178 }
3179 for (; i < 8; i++)
3180 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3181 gfx11_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3182
3183 /* ZS buffer. */
3184 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3185 struct si_surface *zb = (struct si_surface *)state->zsbuf;
3186 struct si_texture *tex = (struct si_texture *)zb->base.texture;
3187
3188 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE |
3189 (zb->base.texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA
3190 : RADEON_PRIO_DEPTH_BUFFER));
3191
3192 const unsigned level = zb->base.u.tex.level;
3193
3194 /* Set mutable fields. */
3195 const struct ac_mutable_ds_state mutable_ds_state = {
3196 .ds = &zb->ds,
3197 .format = tex->db_render_format,
3198 .tc_compat_htile_enabled = vi_tc_compat_htile_enabled(tex, level, PIPE_MASK_ZS),
3199 .zrange_precision = tex->depth_clear_value[level] != 0,
3200 };
3201 struct ac_ds_surface ds;
3202
3203 ac_set_mutable_ds_surface_fields(&sctx->screen->info, &mutable_ds_state, &ds);
3204
3205 gfx11_set_context_reg(R_028014_DB_HTILE_DATA_BASE, ds.u.gfx6.db_htile_data_base);
3206 gfx11_set_context_reg(R_02801C_DB_DEPTH_SIZE_XY, ds.db_depth_size);
3207 gfx11_set_context_reg(R_028040_DB_Z_INFO, ds.db_z_info);
3208 gfx11_set_context_reg(R_028044_DB_STENCIL_INFO, ds.db_stencil_info);
3209 gfx11_set_context_reg(R_028048_DB_Z_READ_BASE, ds.db_depth_base);
3210 gfx11_set_context_reg(R_02804C_DB_STENCIL_READ_BASE, ds.db_stencil_base);
3211 gfx11_set_context_reg(R_028050_DB_Z_WRITE_BASE, ds.db_depth_base);
3212 gfx11_set_context_reg(R_028054_DB_STENCIL_WRITE_BASE, ds.db_stencil_base);
3213 gfx11_set_context_reg(R_028068_DB_Z_READ_BASE_HI, ds.db_depth_base >> 32);
3214 gfx11_set_context_reg(R_02806C_DB_STENCIL_READ_BASE_HI, ds.db_stencil_base >> 32);
3215 gfx11_set_context_reg(R_028070_DB_Z_WRITE_BASE_HI, ds.db_depth_base >> 32);
3216 gfx11_set_context_reg(R_028074_DB_STENCIL_WRITE_BASE_HI, ds.db_stencil_base >> 32);
3217 gfx11_set_context_reg(R_028078_DB_HTILE_DATA_BASE_HI, ds.u.gfx6.db_htile_data_base >> 32);
3218 gfx11_set_context_reg(R_028028_DB_STENCIL_CLEAR, tex->stencil_clear_value[level]);
3219 gfx11_set_context_reg(R_02802C_DB_DEPTH_CLEAR, fui(tex->depth_clear_value[level]));
3220 gfx11_set_context_reg(R_028008_DB_DEPTH_VIEW, ds.db_depth_view);
3221 gfx11_set_context_reg(R_028ABC_DB_HTILE_SURFACE, ds.u.gfx6.db_htile_surface);
3222 } else if (sctx->framebuffer.dirty_zsbuf) {
3223 /* Gfx11+: DB_Z_INFO.NUM_SAMPLES should match the framebuffer samples if no Z/S is bound.
3224 * It determines the sample count for VRS, primitive-ordered pixel shading, and occlusion
3225 * queries.
3226 */
3227 gfx11_set_context_reg(R_028040_DB_Z_INFO,
3228 S_028040_FORMAT(V_028040_Z_INVALID) |
3229 S_028040_NUM_SAMPLES(sctx->framebuffer.log_samples));
3230 gfx11_set_context_reg(R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
3231 }
3232
3233 /* Framebuffer dimensions. */
3234 /* PA_SC_WINDOW_SCISSOR_TL is set to 0,0 in gfx*_init_gfx_preamble_state */
3235 gfx11_set_context_reg(R_028208_PA_SC_WINDOW_SCISSOR_BR,
3236 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3237 gfx11_end_packed_context_regs();
3238
3239 if (sctx->screen->dpbb_allowed &&
3240 sctx->screen->pbb_context_states_per_bin > 1)
3241 radeon_event_write(V_028A90_BREAK_BATCH);
3242
3243 radeon_end();
3244
3245 si_update_display_dcc_dirty(sctx);
3246
3247 sctx->framebuffer.dirty_cbufs = 0;
3248 sctx->framebuffer.dirty_zsbuf = false;
3249 }
3250
gfx12_emit_framebuffer_state(struct si_context * sctx,unsigned index)3251 static void gfx12_emit_framebuffer_state(struct si_context *sctx, unsigned index)
3252 {
3253 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
3254 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3255 unsigned i, nr_cbufs = state->nr_cbufs;
3256 struct si_texture *tex = NULL;
3257 struct si_surface *cb = NULL;
3258 bool is_msaa_resolve = state->nr_cbufs == 2 &&
3259 state->cbufs[0] && state->cbufs[0]->texture->nr_samples > 1 &&
3260 state->cbufs[1] && state->cbufs[1]->texture->nr_samples <= 1;
3261
3262 /* CB can't do MSAA resolve. */
3263 assert(!is_msaa_resolve);
3264
3265 radeon_begin(cs);
3266 gfx12_begin_context_regs();
3267
3268 /* Colorbuffers. */
3269 for (i = 0; i < nr_cbufs; i++) {
3270 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3271 continue;
3272
3273 /* RB+ depth-only rendering. See the comment where we set rbplus_depth_only_opt for more
3274 * information.
3275 */
3276 if (i == 0 &&
3277 sctx->screen->info.rbplus_allowed &&
3278 !sctx->queued.named.blend->cb_target_mask) {
3279 gfx12_set_context_reg(R_028EC0_CB_COLOR0_INFO + i * 4,
3280 S_028EC0_FORMAT(V_028C70_COLOR_32) |
3281 S_028EC0_NUMBER_TYPE(V_028C70_NUMBER_FLOAT));
3282 continue;
3283 }
3284
3285 cb = (struct si_surface *)state->cbufs[i];
3286 if (!cb) {
3287 gfx12_set_context_reg(R_028EC0_CB_COLOR0_INFO + i * 4,
3288 S_028EC0_FORMAT(V_028C70_COLOR_INVALID));
3289 continue;
3290 }
3291
3292 tex = (struct si_texture *)cb->base.texture;
3293 radeon_add_to_buffer_list(
3294 sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE | RADEON_USAGE_CB_NEEDS_IMPLICIT_SYNC |
3295 (tex->buffer.b.b.nr_samples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA : RADEON_PRIO_COLOR_BUFFER));
3296
3297 /* Compute mutable surface parameters. */
3298 const struct ac_mutable_cb_state mutable_cb_state = {
3299 .surf = &tex->surface,
3300 .cb = &cb->cb,
3301 .va = tex->buffer.gpu_address,
3302 };
3303 struct ac_cb_surface cb_surf;
3304
3305 ac_set_mutable_cb_surface_fields(&sctx->screen->info, &mutable_cb_state, &cb_surf);
3306
3307 gfx12_set_context_reg(R_028C60_CB_COLOR0_BASE + i * 0x24, cb_surf.cb_color_base);
3308 gfx12_set_context_reg(R_028C64_CB_COLOR0_VIEW + i * 0x24, cb_surf.cb_color_view);
3309 gfx12_set_context_reg(R_028C68_CB_COLOR0_VIEW2 + i * 0x24, cb_surf.cb_color_view2);
3310 gfx12_set_context_reg(R_028C6C_CB_COLOR0_ATTRIB + i * 0x24, cb_surf.cb_color_attrib);
3311 gfx12_set_context_reg(R_028C70_CB_COLOR0_FDCC_CONTROL + i * 0x24, cb_surf.cb_dcc_control);
3312 gfx12_set_context_reg(R_028C78_CB_COLOR0_ATTRIB2 + i * 0x24, cb_surf.cb_color_attrib2);
3313 gfx12_set_context_reg(R_028C7C_CB_COLOR0_ATTRIB3 + i * 0x24, cb_surf.cb_color_attrib3);
3314 gfx12_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_surf.cb_color_base >> 32);
3315 gfx12_set_context_reg(R_028EC0_CB_COLOR0_INFO + i * 4, cb_surf.cb_color_info);
3316 }
3317 /* Set unbound colorbuffers. */
3318 for (; i < 8; i++)
3319 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3320 gfx12_set_context_reg(R_028EC0_CB_COLOR0_INFO + i * 4, 0);
3321
3322 /* ZS buffer. */
3323 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3324 struct si_surface *zb = (struct si_surface *)state->zsbuf;
3325 struct si_texture *tex = (struct si_texture *)zb->base.texture;
3326
3327 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer,
3328 RADEON_USAGE_READWRITE | RADEON_USAGE_DB_NEEDS_IMPLICIT_SYNC |
3329 (zb->base.texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA
3330 : RADEON_PRIO_DEPTH_BUFFER));
3331 gfx12_set_context_reg(R_028004_DB_DEPTH_VIEW, zb->ds.db_depth_view);
3332 gfx12_set_context_reg(R_028008_DB_DEPTH_VIEW1, zb->ds.u.gfx12.db_depth_view1);
3333 gfx12_set_context_reg(R_028014_DB_DEPTH_SIZE_XY, zb->ds.db_depth_size);
3334 gfx12_set_context_reg(R_028018_DB_Z_INFO, zb->ds.db_z_info);
3335 gfx12_set_context_reg(R_02801C_DB_STENCIL_INFO, zb->ds.db_stencil_info);
3336 gfx12_set_context_reg(R_028020_DB_Z_READ_BASE, zb->ds.db_depth_base);
3337 gfx12_set_context_reg(R_028024_DB_Z_READ_BASE_HI, zb->ds.db_depth_base >> 32);
3338 gfx12_set_context_reg(R_028028_DB_Z_WRITE_BASE, zb->ds.db_depth_base);
3339 gfx12_set_context_reg(R_02802C_DB_Z_WRITE_BASE_HI, zb->ds.db_depth_base >> 32);
3340 gfx12_set_context_reg(R_028030_DB_STENCIL_READ_BASE, zb->ds.db_stencil_base);
3341 gfx12_set_context_reg(R_028034_DB_STENCIL_READ_BASE_HI, zb->ds.db_stencil_base >> 32);
3342 gfx12_set_context_reg(R_028038_DB_STENCIL_WRITE_BASE, zb->ds.db_stencil_base);
3343 gfx12_set_context_reg(R_02803C_DB_STENCIL_WRITE_BASE_HI, zb->ds.db_stencil_base >> 32);
3344
3345 if (tex->force_disable_hiz_his) {
3346 gfx12_set_context_reg(R_028B94_PA_SC_HIZ_INFO, S_028B94_SURFACE_ENABLE(0));
3347 gfx12_set_context_reg(R_028B98_PA_SC_HIS_INFO, S_028B98_SURFACE_ENABLE(0));
3348 } else {
3349 gfx12_set_context_reg(R_028B94_PA_SC_HIZ_INFO, zb->ds.u.gfx12.hiz_info);
3350 gfx12_set_context_reg(R_028B98_PA_SC_HIS_INFO, zb->ds.u.gfx12.his_info);
3351
3352 if (zb->ds.u.gfx12.hiz_info) {
3353 gfx12_set_context_reg(R_028B9C_PA_SC_HIZ_BASE, zb->ds.u.gfx12.hiz_base);
3354 gfx12_set_context_reg(R_028BA0_PA_SC_HIZ_BASE_EXT, zb->ds.u.gfx12.hiz_base >> 32);
3355 gfx12_set_context_reg(R_028BA4_PA_SC_HIZ_SIZE_XY, zb->ds.u.gfx12.hiz_size_xy);
3356 }
3357 if (zb->ds.u.gfx12.his_info) {
3358 gfx12_set_context_reg(R_028BA8_PA_SC_HIS_BASE, zb->ds.u.gfx12.his_base);
3359 gfx12_set_context_reg(R_028BAC_PA_SC_HIS_BASE_EXT, zb->ds.u.gfx12.his_base >> 32);
3360 gfx12_set_context_reg(R_028BB0_PA_SC_HIS_SIZE_XY, zb->ds.u.gfx12.his_size_xy);
3361 }
3362 }
3363 } else if (sctx->framebuffer.dirty_zsbuf) {
3364 gfx12_set_context_reg(R_028018_DB_Z_INFO,
3365 S_028040_FORMAT(V_028040_Z_INVALID) |
3366 S_028040_NUM_SAMPLES(sctx->framebuffer.log_samples));
3367 gfx12_set_context_reg(R_02801C_DB_STENCIL_INFO,
3368 S_028044_FORMAT(V_028044_STENCIL_INVALID)|
3369 S_028044_TILE_STENCIL_DISABLE(1));
3370 gfx12_set_context_reg(R_028B94_PA_SC_HIZ_INFO, S_028B94_SURFACE_ENABLE(0));
3371 gfx12_set_context_reg(R_028B98_PA_SC_HIS_INFO, S_028B98_SURFACE_ENABLE(0));
3372 }
3373
3374 /* Framebuffer dimensions. */
3375 /* PA_SC_WINDOW_SCISSOR_TL is set in gfx12_init_gfx_preamble_state */
3376 gfx12_set_context_reg(R_028208_PA_SC_WINDOW_SCISSOR_BR,
3377 S_028208_BR_X(state->width - 1) | /* inclusive */
3378 S_028208_BR_Y(state->height - 1)); /* inclusive */
3379 gfx12_end_context_regs();
3380
3381 if (sctx->screen->dpbb_allowed &&
3382 sctx->screen->pbb_context_states_per_bin > 1)
3383 radeon_event_write(V_028A90_BREAK_BATCH);
3384
3385 radeon_end();
3386
3387 sctx->framebuffer.dirty_cbufs = 0;
3388 sctx->framebuffer.dirty_zsbuf = false;
3389 }
3390
si_out_of_order_rasterization(struct si_context * sctx)3391 static bool si_out_of_order_rasterization(struct si_context *sctx)
3392 {
3393 struct si_state_blend *blend = sctx->queued.named.blend;
3394 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3395
3396 if (!sctx->screen->info.has_out_of_order_rast)
3397 return false;
3398
3399 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3400
3401 colormask &= blend->cb_target_enabled_4bit;
3402
3403 /* Conservative: No logic op. */
3404 if (colormask && blend->logicop_enable)
3405 return false;
3406
3407 struct si_dsa_order_invariance dsa_order_invariant = {.zs = true,
3408 .pass_set = true};
3409
3410 if (sctx->framebuffer.state.zsbuf) {
3411 struct si_texture *zstex = (struct si_texture *)sctx->framebuffer.state.zsbuf->texture;
3412 bool has_stencil = zstex->surface.has_stencil;
3413 dsa_order_invariant = dsa->order_invariance[has_stencil];
3414 if (!dsa_order_invariant.zs)
3415 return false;
3416
3417 /* The set of PS invocations is always order invariant,
3418 * except when early Z/S tests are requested. */
3419 if (sctx->shader.ps.cso && sctx->shader.ps.cso->info.base.writes_memory &&
3420 sctx->shader.ps.cso->info.base.fs.early_fragment_tests &&
3421 !dsa_order_invariant.pass_set)
3422 return false;
3423
3424 if (sctx->occlusion_query_mode == SI_OCCLUSION_QUERY_MODE_PRECISE_INTEGER &&
3425 !dsa_order_invariant.pass_set)
3426 return false;
3427 }
3428
3429 if (!colormask)
3430 return true;
3431
3432 unsigned blendmask = colormask & blend->blend_enable_4bit;
3433
3434 if (blendmask) {
3435 /* Only commutative blending. */
3436 if (blendmask & ~blend->commutative_4bit)
3437 return false;
3438
3439 if (!dsa_order_invariant.pass_set)
3440 return false;
3441 }
3442
3443 if (colormask & ~blendmask)
3444 return false;
3445
3446 return true;
3447 }
3448
si_emit_msaa_config(struct si_context * sctx,unsigned index)3449 static void si_emit_msaa_config(struct si_context *sctx, unsigned index)
3450 {
3451 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
3452 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3453 /* 33% faster rendering to linear color buffers */
3454 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3455 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3456 unsigned sc_mode_cntl_1 =
3457 S_028A4C_WALK_SIZE(dst_is_linear) | S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3458 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3459 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3460 S_028A4C_OUT_OF_ORDER_WATER_MARK(sctx->gfx_level >= GFX12 ? 0 : 0x7) |
3461 /* This should also be 0 when the VRS image is enabled. */
3462 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(!sctx->framebuffer.has_hiz_his) |
3463 /* always 1: */
3464 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3465 S_028A4C_TILE_WALK_ORDER_ENABLE(1) | S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3466 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3467 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3468 S_028804_INCOHERENT_EQAA_READS(sctx->gfx_level < GFX12) |
3469 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3470 unsigned coverage_samples, z_samples;
3471 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3472
3473 /* S: Coverage samples (up to 16x):
3474 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3475 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3476 *
3477 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3478 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3479 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3480 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3481 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3482 * # Z samples).
3483 *
3484 * F: Color samples (up to 8x, must be <= coverage samples):
3485 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3486 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3487 *
3488 * Can be anything between coverage and color samples:
3489 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3490 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3491 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3492 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3493 * # All are currently set the same as coverage samples.
3494 *
3495 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3496 * flag for undefined color samples. A shader-based resolve must handle unknowns
3497 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3498 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3499 * useful. The CB resolve always drops unknowns.
3500 *
3501 * Sensible AA configurations:
3502 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3503 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3504 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3505 * EQAA 8s 8z 8f = 8x MSAA
3506 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3507 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3508 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3509 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3510 * EQAA 4s 4z 4f = 4x MSAA
3511 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3512 * EQAA 2s 2z 2f = 2x MSAA
3513 */
3514 coverage_samples = si_get_num_coverage_samples(sctx);
3515
3516 /* DCC_DECOMPRESS and ELIMINATE_FAST_CLEAR require MSAA_NUM_SAMPLES=0. */
3517 if (sctx->gfx_level >= GFX11 && sctx->gfx11_force_msaa_num_samples_zero)
3518 coverage_samples = 1;
3519
3520 /* The DX10 diamond test is not required by GL and decreases line rasterization
3521 * performance, so don't use it.
3522 */
3523 unsigned sc_line_cntl = 0;
3524 unsigned sc_aa_config = 0;
3525
3526 if (coverage_samples > 1 && (rs->multisample_enable ||
3527 sctx->smoothing_enabled)) {
3528 unsigned log_samples = util_logbase2(coverage_samples);
3529
3530 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1) |
3531 S_028BDC_PERPENDICULAR_ENDCAP_ENA(rs->perpendicular_end_caps) |
3532 S_028BDC_EXTRA_DX_DY_PRECISION(rs->perpendicular_end_caps &&
3533 (sctx->family == CHIP_VEGA20 ||
3534 sctx->gfx_level >= GFX10));
3535 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3536 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3537
3538 if (sctx->gfx_level < GFX12) {
3539 sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(si_msaa_max_distance[log_samples]) |
3540 S_028BE0_COVERED_CENTROID_IS_CENTER(sctx->gfx_level >= GFX10_3);
3541 }
3542 }
3543
3544 if (sctx->framebuffer.nr_samples > 1 ||
3545 sctx->smoothing_enabled) {
3546 if (sctx->framebuffer.state.zsbuf) {
3547 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3548 z_samples = MAX2(1, z_samples);
3549 } else {
3550 z_samples = coverage_samples;
3551 }
3552 unsigned log_samples = util_logbase2(coverage_samples);
3553 unsigned log_z_samples = util_logbase2(z_samples);
3554 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3555 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3556 if (sctx->framebuffer.nr_samples > 1) {
3557 if (sctx->gfx_level >= GFX12) {
3558 sc_aa_config |= S_028BE0_PS_ITER_SAMPLES(log_ps_iter_samples);
3559 db_eqaa |= S_028078_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3560 S_028078_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3561 } else {
3562 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3563 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3564 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3565 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3566 }
3567 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3568 } else if (sctx->smoothing_enabled) {
3569 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3570 }
3571 }
3572
3573 if (sctx->gfx_level >= GFX12) {
3574 radeon_begin(cs);
3575 gfx12_begin_context_regs();
3576 gfx12_opt_set_context_reg(R_028BDC_PA_SC_LINE_CNTL, SI_TRACKED_PA_SC_LINE_CNTL,
3577 sc_line_cntl);
3578 gfx12_opt_set_context_reg(R_028BE0_PA_SC_AA_CONFIG, SI_TRACKED_PA_SC_AA_CONFIG,
3579 sc_aa_config);
3580 gfx12_opt_set_context_reg(R_028078_DB_EQAA, SI_TRACKED_DB_EQAA, db_eqaa);
3581 gfx12_opt_set_context_reg(R_028A4C_PA_SC_MODE_CNTL_1, SI_TRACKED_PA_SC_MODE_CNTL_1,
3582 sc_mode_cntl_1);
3583 gfx12_end_context_regs();
3584 radeon_end(); /* don't track context rolls on GFX12 */
3585 } else if (sctx->screen->info.has_set_context_pairs_packed) {
3586 radeon_begin(cs);
3587 gfx11_begin_packed_context_regs();
3588 gfx11_opt_set_context_reg(R_028BDC_PA_SC_LINE_CNTL, SI_TRACKED_PA_SC_LINE_CNTL,
3589 sc_line_cntl);
3590 gfx11_opt_set_context_reg(R_028BE0_PA_SC_AA_CONFIG, SI_TRACKED_PA_SC_AA_CONFIG,
3591 sc_aa_config);
3592 gfx11_opt_set_context_reg(R_028804_DB_EQAA, SI_TRACKED_DB_EQAA, db_eqaa);
3593 gfx11_opt_set_context_reg(R_028A4C_PA_SC_MODE_CNTL_1, SI_TRACKED_PA_SC_MODE_CNTL_1,
3594 sc_mode_cntl_1);
3595 gfx11_end_packed_context_regs();
3596 radeon_end(); /* don't track context rolls on GFX11 */
3597 } else {
3598 radeon_begin(cs);
3599 radeon_opt_set_context_reg2(R_028BDC_PA_SC_LINE_CNTL, SI_TRACKED_PA_SC_LINE_CNTL,
3600 sc_line_cntl, sc_aa_config);
3601 radeon_opt_set_context_reg(R_028804_DB_EQAA, SI_TRACKED_DB_EQAA, db_eqaa);
3602 radeon_opt_set_context_reg(R_028A4C_PA_SC_MODE_CNTL_1, SI_TRACKED_PA_SC_MODE_CNTL_1,
3603 sc_mode_cntl_1);
3604 radeon_end_update_context_roll();
3605 }
3606 }
3607
si_update_ps_iter_samples(struct si_context * sctx)3608 void si_update_ps_iter_samples(struct si_context *sctx)
3609 {
3610 if (sctx->framebuffer.nr_samples > 1)
3611 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3612 if (sctx->screen->dpbb_allowed)
3613 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3614 }
3615
si_set_min_samples(struct pipe_context * ctx,unsigned min_samples)3616 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3617 {
3618 struct si_context *sctx = (struct si_context *)ctx;
3619
3620 /* The hardware can only do sample shading with 2^n samples. */
3621 min_samples = util_next_power_of_two(min_samples);
3622
3623 if (sctx->ps_iter_samples == min_samples)
3624 return;
3625
3626 sctx->ps_iter_samples = min_samples;
3627
3628 si_ps_key_update_sample_shading(sctx);
3629 si_ps_key_update_framebuffer_rasterizer_sample_shading(sctx);
3630 sctx->do_update_shaders = true;
3631
3632 si_update_ps_iter_samples(sctx);
3633 }
3634
3635 /*
3636 * Samplers
3637 */
3638
3639 /**
3640 * Build the sampler view descriptor for a buffer texture.
3641 * @param state 256-bit descriptor; only the high 128 bits are filled in
3642 */
si_make_buffer_descriptor(struct si_screen * screen,struct si_resource * buf,enum pipe_format format,unsigned offset,unsigned num_elements,uint32_t * state)3643 void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
3644 enum pipe_format format, unsigned offset, unsigned num_elements,
3645 uint32_t *state)
3646 {
3647 const struct util_format_description *desc;
3648 unsigned stride;
3649 unsigned num_records;
3650
3651 desc = util_format_description(format);
3652 stride = desc->block.bits / 8;
3653
3654 num_records = num_elements;
3655 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3656
3657 /* The NUM_RECORDS field has a different meaning depending on the chip,
3658 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3659 *
3660 * GFX6-7,10:
3661 * - If STRIDE == 0, it's in byte units.
3662 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3663 *
3664 * GFX8:
3665 * - For SMEM and STRIDE == 0, it's in byte units.
3666 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3667 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3668 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3669 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3670 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3671 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3672 * That way the same descriptor can be used by both SMEM and VMEM.
3673 *
3674 * GFX9:
3675 * - For SMEM and STRIDE == 0, it's in byte units.
3676 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3677 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3678 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3679 */
3680 if (screen->info.gfx_level == GFX8)
3681 num_records *= stride;
3682
3683 const struct ac_buffer_state buffer_state = {
3684 .size = num_records,
3685 .format = format,
3686 .swizzle =
3687 {
3688 desc->swizzle[0],
3689 desc->swizzle[1],
3690 desc->swizzle[2],
3691 desc->swizzle[3],
3692 },
3693 .stride = stride,
3694 .gfx10_oob_select = V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET,
3695 };
3696
3697 ac_build_buffer_descriptor(screen->info.gfx_level, &buffer_state, &state[4]);
3698 }
3699
3700 /**
3701 * Translate the parameters to an image descriptor for CDNA image emulation.
3702 * In this function, we choose our own image descriptor format because we emulate image opcodes
3703 * using buffer opcodes.
3704 */
cdna_emu_make_image_descriptor(struct si_screen * screen,struct si_texture * tex,bool sampler,enum pipe_texture_target target,enum pipe_format pipe_format,const unsigned char state_swizzle[4],unsigned first_level,unsigned last_level,unsigned first_layer,unsigned last_layer,unsigned width,unsigned height,unsigned depth,uint32_t * state,uint32_t * fmask_state)3705 static void cdna_emu_make_image_descriptor(struct si_screen *screen, struct si_texture *tex,
3706 bool sampler, enum pipe_texture_target target,
3707 enum pipe_format pipe_format,
3708 const unsigned char state_swizzle[4], unsigned first_level,
3709 unsigned last_level, unsigned first_layer,
3710 unsigned last_layer, unsigned width, unsigned height,
3711 unsigned depth, uint32_t *state, uint32_t *fmask_state)
3712 {
3713 const struct util_format_description *desc = util_format_description(pipe_format);
3714
3715 /* We don't need support these. We only need enough to support VAAPI and OpenMAX. */
3716 if (target == PIPE_TEXTURE_CUBE ||
3717 target == PIPE_TEXTURE_CUBE_ARRAY ||
3718 tex->buffer.b.b.last_level > 0 ||
3719 tex->buffer.b.b.nr_samples >= 2 ||
3720 desc->colorspace != UTIL_FORMAT_COLORSPACE_RGB ||
3721 desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED ||
3722 util_format_is_compressed(pipe_format)) {
3723 assert(!"unexpected texture type");
3724 memset(state, 0, 8 * 4);
3725 return;
3726 }
3727
3728 /* Adjust the image parameters according to the texture type. */
3729 switch (target) {
3730 case PIPE_TEXTURE_1D:
3731 height = 1;
3732 FALLTHROUGH;
3733 case PIPE_TEXTURE_2D:
3734 case PIPE_TEXTURE_RECT:
3735 depth = 1;
3736 break;
3737
3738 case PIPE_TEXTURE_1D_ARRAY:
3739 height = 1;
3740 FALLTHROUGH;
3741 case PIPE_TEXTURE_2D_ARRAY:
3742 first_layer = MIN2(first_layer, tex->buffer.b.b.array_size - 1);
3743 last_layer = MIN2(last_layer, tex->buffer.b.b.array_size - 1);
3744 last_layer = MAX2(last_layer, first_layer);
3745 depth = last_layer - first_layer + 1;
3746 break;
3747
3748 case PIPE_TEXTURE_3D:
3749 first_layer = 0;
3750 break;
3751
3752 default:
3753 unreachable("invalid texture target");
3754 }
3755
3756 unsigned stride = desc->block.bits / 8;
3757 uint64_t num_records = tex->surface.surf_size / stride;
3758 assert(num_records <= UINT32_MAX);
3759
3760 /* Prepare the format fields. */
3761 unsigned char swizzle[4];
3762 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3763
3764 /* Buffer descriptor */
3765 const struct ac_buffer_state buffer_state = {
3766 .size = num_records,
3767 .format = pipe_format,
3768 .swizzle =
3769 {
3770 desc->swizzle[0],
3771 desc->swizzle[1],
3772 desc->swizzle[2],
3773 desc->swizzle[3],
3774 },
3775 .stride = stride,
3776 .gfx10_oob_select = V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET,
3777 };
3778
3779 ac_build_buffer_descriptor(screen->info.gfx_level, &buffer_state, &state[0]);
3780
3781 /* Additional fields used by image opcode emulation. */
3782 state[4] = width | (height << 16);
3783 state[5] = depth | (first_layer << 16);
3784 state[6] = tex->surface.u.gfx9.surf_pitch;
3785 state[7] = (uint32_t)tex->surface.u.gfx9.surf_pitch * tex->surface.u.gfx9.surf_height;
3786 }
3787
3788 /**
3789 * Build the sampler view descriptor for a texture.
3790 */
gfx10_make_texture_descriptor(struct si_screen * screen,struct si_texture * tex,bool sampler,enum pipe_texture_target target,enum pipe_format pipe_format,const unsigned char state_swizzle[4],unsigned first_level,unsigned last_level,unsigned first_layer,unsigned last_layer,unsigned width,unsigned height,unsigned depth,bool get_bo_metadata,uint32_t * state,uint32_t * fmask_state)3791 static void gfx10_make_texture_descriptor(
3792 struct si_screen *screen, struct si_texture *tex, bool sampler, enum pipe_texture_target target,
3793 enum pipe_format pipe_format, const unsigned char state_swizzle[4], unsigned first_level,
3794 unsigned last_level, unsigned first_layer, unsigned last_layer, unsigned width, unsigned height,
3795 unsigned depth, bool get_bo_metadata, uint32_t *state, uint32_t *fmask_state)
3796 {
3797 struct pipe_resource *res = &tex->buffer.b.b;
3798 const struct util_format_description *desc;
3799 unsigned char swizzle[4];
3800 unsigned type;
3801
3802 desc = util_format_description(pipe_format);
3803
3804 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3805 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3806 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3807 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3808
3809 switch (pipe_format) {
3810 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3811 case PIPE_FORMAT_X32_S8X24_UINT:
3812 case PIPE_FORMAT_X8Z24_UNORM:
3813 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3814 break;
3815 case PIPE_FORMAT_X24S8_UINT:
3816 /*
3817 * X24S8 is implemented as an 8_8_8_8 data format, to
3818 * fix texture gathers. This affects at least
3819 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3820 */
3821 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3822 break;
3823 default:
3824 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3825 }
3826 } else {
3827 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3828 }
3829
3830 if (!sampler && (res->target == PIPE_TEXTURE_CUBE || res->target == PIPE_TEXTURE_CUBE_ARRAY)) {
3831 /* For the purpose of shader images, treat cube maps as 2D
3832 * arrays.
3833 */
3834 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3835 } else {
3836 type = si_tex_dim(screen, tex, target, res->nr_samples);
3837 }
3838
3839 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3840 height = 1;
3841 depth = res->array_size;
3842 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY || type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3843 if (sampler || res->target != PIPE_TEXTURE_3D)
3844 depth = res->array_size;
3845 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3846 depth = res->array_size / 6;
3847
3848 const struct ac_texture_state tex_state = {
3849 .surf = &tex->surface,
3850 .format = pipe_format,
3851 .img_format = res->format,
3852 .width = width,
3853 .height = height,
3854 .depth = (type == V_008F1C_SQ_RSRC_IMG_3D && sampler) ? depth - 1 : last_layer,
3855 .type = type,
3856 .swizzle =
3857 {
3858 swizzle[0],
3859 swizzle[1],
3860 swizzle[2],
3861 swizzle[3],
3862 },
3863 .num_samples = res->nr_samples,
3864 .num_storage_samples = res->nr_storage_samples,
3865 .first_level = first_level,
3866 .last_level = last_level,
3867 .num_levels = res->last_level + 1,
3868 .first_layer = first_layer,
3869 .last_layer = last_layer,
3870 .gfx10 = {
3871 .uav3d = !!(type == V_008F1C_SQ_RSRC_IMG_3D && !sampler),
3872 .upgraded_depth = tex->upgraded_depth,
3873 },
3874 .dcc_enabled = vi_dcc_enabled(tex, first_level),
3875 };
3876
3877 ac_build_texture_descriptor(&screen->info, &tex_state, &state[0]);
3878
3879 /* Initialize the sampler view for FMASK. */
3880 if (tex->surface.fmask_offset) {
3881 const struct ac_fmask_state ac_state = {
3882 .surf = &tex->surface,
3883 .va = tex->buffer.gpu_address,
3884 .width = width,
3885 .height = height,
3886 .depth = depth,
3887 .type = si_tex_dim(screen, tex, target, 0),
3888 .first_layer = first_layer,
3889 .last_layer = last_layer,
3890 .num_samples = res->nr_samples,
3891 .num_storage_samples = res->nr_storage_samples,
3892 };
3893
3894 ac_build_fmask_descriptor(screen->info.gfx_level, &ac_state, &fmask_state[0]);
3895 }
3896 }
3897
3898 /**
3899 * Build the sampler view descriptor for a texture (SI-GFX9).
3900 */
si_make_texture_descriptor(struct si_screen * screen,struct si_texture * tex,bool sampler,enum pipe_texture_target target,enum pipe_format pipe_format,const unsigned char state_swizzle[4],unsigned first_level,unsigned last_level,unsigned first_layer,unsigned last_layer,unsigned width,unsigned height,unsigned depth,bool get_bo_metadata,uint32_t * state,uint32_t * fmask_state)3901 void si_make_texture_descriptor(struct si_screen *screen, struct si_texture *tex,
3902 bool sampler, enum pipe_texture_target target,
3903 enum pipe_format pipe_format,
3904 const unsigned char state_swizzle[4], unsigned first_level,
3905 unsigned last_level, unsigned first_layer,
3906 unsigned last_layer, unsigned width, unsigned height,
3907 unsigned depth, bool get_bo_metadata,
3908 uint32_t *state, uint32_t *fmask_state)
3909 {
3910 if (!screen->info.has_image_opcodes && !get_bo_metadata) {
3911 cdna_emu_make_image_descriptor(screen, tex, sampler, target, pipe_format, state_swizzle,
3912 first_level, last_level, first_layer, last_layer, width,
3913 height, depth, state, fmask_state);
3914 return;
3915 }
3916
3917 if (screen->info.gfx_level >= GFX10) {
3918 gfx10_make_texture_descriptor(screen, tex, sampler, target, pipe_format, state_swizzle,
3919 first_level, last_level, first_layer, last_layer, width,
3920 height, depth, get_bo_metadata, state, fmask_state);
3921 return;
3922 }
3923
3924 struct pipe_resource *res = &tex->buffer.b.b;
3925 const struct util_format_description *desc;
3926 unsigned char swizzle[4];
3927 unsigned type, num_samples;
3928
3929 desc = util_format_description(pipe_format);
3930
3931 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ? MAX2(1, res->nr_samples)
3932 : MAX2(1, res->nr_storage_samples);
3933
3934 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3935 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3936 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3937 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3938
3939 switch (pipe_format) {
3940 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3941 case PIPE_FORMAT_X32_S8X24_UINT:
3942 case PIPE_FORMAT_X8Z24_UNORM:
3943 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3944 break;
3945 case PIPE_FORMAT_X24S8_UINT:
3946 /*
3947 * X24S8 is implemented as an 8_8_8_8 data format, to
3948 * fix texture gathers. This affects at least
3949 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3950 */
3951 if (screen->info.gfx_level <= GFX8)
3952 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3953 else
3954 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3955 break;
3956 default:
3957 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3958 }
3959 } else {
3960 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3961 }
3962
3963 if (!sampler && (res->target == PIPE_TEXTURE_CUBE || res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3964 (screen->info.gfx_level <= GFX8 && res->target == PIPE_TEXTURE_3D))) {
3965 /* For the purpose of shader images, treat cube maps and 3D
3966 * textures as 2D arrays. For 3D textures, the address
3967 * calculations for mipmaps are different, so we rely on the
3968 * caller to effectively disable mipmaps.
3969 */
3970 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3971
3972 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3973 } else {
3974 type = si_tex_dim(screen, tex, target, num_samples);
3975 }
3976
3977 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3978 height = 1;
3979 depth = res->array_size;
3980 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY || type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3981 if (sampler || res->target != PIPE_TEXTURE_3D)
3982 depth = res->array_size;
3983 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3984 depth = res->array_size / 6;
3985
3986 const struct ac_texture_state tex_state = {
3987 .surf = &tex->surface,
3988 .format = pipe_format,
3989 .img_format = res->format,
3990 .width = width,
3991 .height = height,
3992 .depth = depth,
3993 .type = type,
3994 .swizzle =
3995 {
3996 swizzle[0],
3997 swizzle[1],
3998 swizzle[2],
3999 swizzle[3],
4000 },
4001 .num_samples = res->nr_samples,
4002 .num_storage_samples = res->nr_storage_samples,
4003 .first_level = first_level,
4004 .last_level = last_level,
4005 .num_levels = res->last_level + 1,
4006 .first_layer = first_layer,
4007 .last_layer = last_layer,
4008 .dcc_enabled = vi_dcc_enabled(tex, first_level),
4009 .tc_compat_htile_enabled = true,
4010 };
4011
4012 ac_build_texture_descriptor(&screen->info, &tex_state, &state[0]);
4013
4014 /* Initialize the sampler view for FMASK. */
4015 if (tex->surface.fmask_offset) {
4016 const struct ac_fmask_state ac_state = {
4017 .surf = &tex->surface,
4018 .va = tex->buffer.gpu_address,
4019 .width = width,
4020 .height = height,
4021 .depth = depth,
4022 .type = si_tex_dim(screen, tex, target, 0),
4023 .first_layer = first_layer,
4024 .last_layer = last_layer,
4025 .num_samples = res->nr_samples,
4026 .num_storage_samples = res->nr_storage_samples,
4027 };
4028
4029 ac_build_fmask_descriptor(screen->info.gfx_level, &ac_state, &fmask_state[0]);
4030 }
4031 }
4032
4033 /**
4034 * Create a sampler view.
4035 *
4036 * @param ctx context
4037 * @param texture texture
4038 * @param state sampler view template
4039 */
si_create_sampler_view(struct pipe_context * ctx,struct pipe_resource * texture,const struct pipe_sampler_view * state)4040 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
4041 struct pipe_resource *texture,
4042 const struct pipe_sampler_view *state)
4043 {
4044 struct si_context *sctx = (struct si_context *)ctx;
4045 struct si_sampler_view *view = CALLOC_STRUCT_CL(si_sampler_view);
4046 struct si_texture *tex = (struct si_texture *)texture;
4047 unsigned char state_swizzle[4];
4048 unsigned last_layer = state->u.tex.last_layer;
4049 enum pipe_format pipe_format;
4050 const struct legacy_surf_level *surflevel;
4051
4052 if (!view)
4053 return NULL;
4054
4055 /* initialize base object */
4056 view->base = *state;
4057 view->base.texture = NULL;
4058 view->base.reference.count = 1;
4059 view->base.context = ctx;
4060
4061 assert(texture);
4062 pipe_resource_reference(&view->base.texture, texture);
4063
4064 if (state->format == PIPE_FORMAT_X24S8_UINT || state->format == PIPE_FORMAT_S8X24_UINT ||
4065 state->format == PIPE_FORMAT_X32_S8X24_UINT || state->format == PIPE_FORMAT_S8_UINT)
4066 view->is_stencil_sampler = true;
4067
4068 /* Buffer resource. */
4069 if (texture->target == PIPE_BUFFER) {
4070 uint32_t elements = si_clamp_texture_texel_count(sctx->screen->b.caps.max_texel_buffer_elements,
4071 state->format, state->u.buf.size);
4072
4073 si_make_buffer_descriptor(sctx->screen, si_resource(texture), state->format,
4074 state->u.buf.offset, elements, view->state);
4075 return &view->base;
4076 }
4077
4078 state_swizzle[0] = state->swizzle_r;
4079 state_swizzle[1] = state->swizzle_g;
4080 state_swizzle[2] = state->swizzle_b;
4081 state_swizzle[3] = state->swizzle_a;
4082
4083 /* This is not needed if gallium frontends set last_layer correctly. */
4084 if (state->target == PIPE_TEXTURE_1D || state->target == PIPE_TEXTURE_2D ||
4085 state->target == PIPE_TEXTURE_RECT || state->target == PIPE_TEXTURE_CUBE)
4086 last_layer = state->u.tex.first_layer;
4087
4088 /* Texturing with separate depth and stencil. */
4089 pipe_format = state->format;
4090
4091 /* Depth/stencil texturing sometimes needs separate texture. */
4092 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4093 if (!tex->flushed_depth_texture && !si_init_flushed_depth_texture(ctx, texture)) {
4094 pipe_resource_reference(&view->base.texture, NULL);
4095 FREE(view);
4096 return NULL;
4097 }
4098
4099 assert(tex->flushed_depth_texture);
4100
4101 /* Override format for the case where the flushed texture
4102 * contains only Z or only S.
4103 */
4104 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4105 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4106
4107 tex = tex->flushed_depth_texture;
4108 }
4109
4110 surflevel = tex->surface.u.legacy.level;
4111
4112 if (tex->db_compatible) {
4113 if (!view->is_stencil_sampler)
4114 pipe_format = tex->db_render_format;
4115
4116 switch (pipe_format) {
4117 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4118 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4119 break;
4120 case PIPE_FORMAT_X8Z24_UNORM:
4121 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4122 /* Z24 is always stored like this for DB
4123 * compatibility.
4124 */
4125 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4126 break;
4127 case PIPE_FORMAT_X24S8_UINT:
4128 case PIPE_FORMAT_S8X24_UINT:
4129 case PIPE_FORMAT_X32_S8X24_UINT:
4130 pipe_format = PIPE_FORMAT_S8_UINT;
4131 surflevel = tex->surface.u.legacy.zs.stencil_level;
4132 break;
4133 default:;
4134 }
4135 }
4136
4137 view->dcc_incompatible =
4138 vi_dcc_formats_are_incompatible(texture, state->u.tex.first_level, state->format);
4139
4140 si_make_texture_descriptor(sctx->screen, tex, true, state->target, pipe_format, state_swizzle,
4141 state->u.tex.first_level, state->u.tex.last_level,
4142 state->u.tex.first_layer, last_layer, texture->width0,
4143 texture->height0, texture->depth0, false, view->state,
4144 view->fmask_state);
4145
4146 view->base_level_info = &surflevel[0];
4147 view->block_width = util_format_get_blockwidth(pipe_format);
4148 return &view->base;
4149 }
4150
si_sampler_view_destroy(struct pipe_context * ctx,struct pipe_sampler_view * state)4151 static void si_sampler_view_destroy(struct pipe_context *ctx, struct pipe_sampler_view *state)
4152 {
4153 struct si_sampler_view *view = (struct si_sampler_view *)state;
4154
4155 pipe_resource_reference(&state->texture, NULL);
4156 FREE_CL(view);
4157 }
4158
wrap_mode_uses_border_color(unsigned wrap,bool linear_filter)4159 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4160 {
4161 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER || wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4162 (linear_filter && (wrap == PIPE_TEX_WRAP_CLAMP || wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4163 }
4164
si_translate_border_color(struct si_context * sctx,const struct pipe_sampler_state * state,const union pipe_color_union * color,bool is_integer,uint32_t * border_color_ptr)4165 static uint32_t si_translate_border_color(struct si_context *sctx,
4166 const struct pipe_sampler_state *state,
4167 const union pipe_color_union *color, bool is_integer,
4168 uint32_t *border_color_ptr)
4169 {
4170 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4171 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4172
4173 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4174 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4175 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4176 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4177
4178 #define simple_border_types(elt) \
4179 do { \
4180 if (color->elt[0] == 0 && color->elt[1] == 0 && color->elt[2] == 0 && color->elt[3] == 0) \
4181 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK; \
4182 if (color->elt[0] == 0 && color->elt[1] == 0 && color->elt[2] == 0 && color->elt[3] == 1) \
4183 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK; \
4184 if (color->elt[0] == 1 && color->elt[1] == 1 && color->elt[2] == 1 && color->elt[3] == 1) \
4185 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE; \
4186 } while (false)
4187
4188 if (is_integer)
4189 simple_border_types(ui);
4190 else
4191 simple_border_types(f);
4192
4193 #undef simple_border_types
4194
4195 int i;
4196
4197 /* Check if the border has been uploaded already. */
4198 for (i = 0; i < sctx->border_color_count; i++)
4199 if (memcmp(&sctx->border_color_table[i], color, sizeof(*color)) == 0)
4200 break;
4201
4202 if (i >= SI_MAX_BORDER_COLORS) {
4203 /* Getting 4096 unique border colors is very unlikely. */
4204 static bool printed;
4205 if (!printed) {
4206 fprintf(stderr, "radeonsi: The border color table is full. "
4207 "Any new border colors will be just black. "
4208 "This is a hardware limitation.\n");
4209 printed = true;
4210 }
4211 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4212 }
4213
4214 if (i == sctx->border_color_count) {
4215 /* Upload a new border color. */
4216 memcpy(&sctx->border_color_table[i], color, sizeof(*color));
4217 util_memcpy_cpu_to_le32(&sctx->border_color_map[i], color, sizeof(*color));
4218 sctx->border_color_count++;
4219 }
4220
4221 *border_color_ptr = i;
4222
4223 return V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
4224 }
4225
si_tex_filter(unsigned filter,unsigned max_aniso)4226 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4227 {
4228 if (filter == PIPE_TEX_FILTER_LINEAR)
4229 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4230 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4231 else
4232 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4233 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4234 }
4235
si_tex_aniso_filter(unsigned filter)4236 static inline unsigned si_tex_aniso_filter(unsigned filter)
4237 {
4238 if (filter < 2)
4239 return 0;
4240 if (filter < 4)
4241 return 1;
4242 if (filter < 8)
4243 return 2;
4244 if (filter < 16)
4245 return 3;
4246 return 4;
4247 }
4248
si_tex_filter_mode(unsigned mode)4249 static unsigned si_tex_filter_mode(unsigned mode)
4250 {
4251 switch (mode) {
4252 case PIPE_TEX_REDUCTION_WEIGHTED_AVERAGE:
4253 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4254 case PIPE_TEX_REDUCTION_MIN:
4255 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4256 case PIPE_TEX_REDUCTION_MAX:
4257 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4258 default:
4259 break;
4260 }
4261 return 0;
4262 }
4263
si_create_sampler_state(struct pipe_context * ctx,const struct pipe_sampler_state * state)4264 static void *si_create_sampler_state(struct pipe_context *ctx,
4265 const struct pipe_sampler_state *state)
4266 {
4267 struct si_context *sctx = (struct si_context *)ctx;
4268 struct si_screen *sscreen = sctx->screen;
4269 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4270 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso : state->max_anisotropy;
4271 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4272 unsigned filter_mode = si_tex_filter_mode(state->reduction_mode);
4273 bool trunc_coord = (state->min_img_filter == PIPE_TEX_FILTER_NEAREST &&
4274 state->mag_img_filter == PIPE_TEX_FILTER_NEAREST &&
4275 state->compare_mode == PIPE_TEX_COMPARE_NONE) ||
4276 sscreen->info.conformant_trunc_coord;
4277 union pipe_color_union clamped_border_color;
4278
4279 if (!rstate) {
4280 return NULL;
4281 }
4282
4283 /* Validate inputs. */
4284 if (!is_wrap_mode_legal(sscreen, state->wrap_s) ||
4285 !is_wrap_mode_legal(sscreen, state->wrap_t) ||
4286 !is_wrap_mode_legal(sscreen, state->wrap_r) ||
4287 (!sscreen->info.has_3d_cube_border_color_mipmap &&
4288 (state->min_mip_filter != PIPE_TEX_MIPFILTER_NONE ||
4289 state->max_anisotropy > 0))) {
4290 assert(0);
4291 return NULL;
4292 }
4293
4294 #ifndef NDEBUG
4295 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4296 #endif
4297
4298 unsigned border_color_ptr = 0;
4299 unsigned border_color_type =
4300 si_translate_border_color(sctx, state, &state->border_color,
4301 state->border_color_is_integer,
4302 &border_color_ptr);
4303
4304 struct ac_sampler_state ac_state = {
4305 .address_mode_u = si_tex_wrap(state->wrap_s),
4306 .address_mode_v = si_tex_wrap(state->wrap_t),
4307 .address_mode_w = si_tex_wrap(state->wrap_r),
4308 .max_aniso_ratio = max_aniso_ratio,
4309 .depth_compare_func = si_tex_compare(state->compare_mode, state->compare_func),
4310 .unnormalized_coords = state->unnormalized_coords,
4311 .cube_wrap = state->seamless_cube_map,
4312 .trunc_coord = trunc_coord,
4313 .filter_mode = filter_mode,
4314 .mag_filter = si_tex_filter(state->mag_img_filter, max_aniso),
4315 .min_filter = si_tex_filter(state->min_img_filter, max_aniso),
4316 .mip_filter = si_tex_mipfilter(state->min_mip_filter),
4317 .min_lod = state->min_lod,
4318 .max_lod = state->max_lod,
4319 .lod_bias = state->lod_bias,
4320 .border_color_type = border_color_type,
4321 .border_color_ptr = border_color_ptr,
4322 };
4323
4324 ac_build_sampler_descriptor(sscreen->info.gfx_level, &ac_state, rstate->val);
4325
4326 /* Create sampler resource for upgraded depth textures. */
4327 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4328
4329 for (unsigned i = 0; i < 4; ++i) {
4330 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4331 * when the border color is 1.0. */
4332 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4333 }
4334
4335 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0) {
4336 if (sscreen->info.gfx_level <= GFX9)
4337 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4338 } else {
4339 border_color_ptr = 0;
4340 border_color_type = si_translate_border_color(sctx, state, &clamped_border_color, false, &border_color_ptr);
4341
4342 rstate->upgraded_depth_val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
4343
4344 if (sscreen->info.gfx_level >= GFX11) {
4345 rstate->upgraded_depth_val[3] |= S_008F3C_BORDER_COLOR_PTR_GFX11(border_color_ptr);
4346 } else {
4347 rstate->upgraded_depth_val[3] |= S_008F3C_BORDER_COLOR_PTR_GFX6(border_color_ptr);
4348 }
4349 }
4350
4351 return rstate;
4352 }
4353
si_set_sample_mask(struct pipe_context * ctx,unsigned sample_mask)4354 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4355 {
4356 struct si_context *sctx = (struct si_context *)ctx;
4357
4358 if (sctx->sample_mask == (uint16_t)sample_mask)
4359 return;
4360
4361 sctx->sample_mask = sample_mask;
4362 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4363 }
4364
si_emit_sample_mask(struct si_context * sctx,unsigned index)4365 static void si_emit_sample_mask(struct si_context *sctx, unsigned index)
4366 {
4367 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
4368 unsigned mask = sctx->sample_mask;
4369
4370 /* Needed for line and polygon smoothing as well as for the Polaris
4371 * small primitive filter. We expect the gallium frontend to take care of
4372 * this for us.
4373 */
4374 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4375 (mask & 1 && sctx->blitter_running));
4376
4377 radeon_begin(cs);
4378 radeon_set_context_reg_seq(R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4379 radeon_emit(mask | (mask << 16));
4380 radeon_emit(mask | (mask << 16));
4381 radeon_end();
4382 }
4383
si_delete_sampler_state(struct pipe_context * ctx,void * state)4384 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4385 {
4386 #ifndef NDEBUG
4387 struct si_sampler_state *s = state;
4388
4389 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4390 s->magic = 0;
4391 #endif
4392 free(state);
4393 }
4394
4395 /*
4396 * Vertex elements & buffers
4397 */
4398
si_compute_fast_udiv_info32(uint32_t D,unsigned num_bits)4399 struct si_fast_udiv_info32 si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4400 {
4401 struct util_fast_udiv_info info = util_compute_fast_udiv_info(D, num_bits, 32);
4402
4403 struct si_fast_udiv_info32 result = {
4404 info.multiplier,
4405 info.pre_shift,
4406 info.post_shift,
4407 info.increment,
4408 };
4409 return result;
4410 }
4411
si_create_vertex_elements(struct pipe_context * ctx,unsigned count,const struct pipe_vertex_element * elements)4412 static void *si_create_vertex_elements(struct pipe_context *ctx, unsigned count,
4413 const struct pipe_vertex_element *elements)
4414 {
4415 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
4416
4417 if (sscreen->debug_flags & DBG(VERTEX_ELEMENTS)) {
4418 for (int i = 0; i < count; ++i) {
4419 const struct pipe_vertex_element *e = elements + i;
4420 fprintf(stderr, "elements[%d]: offset %2d, buffer_index %d, dual_slot %d, format %3d, divisor %u\n",
4421 i, e->src_offset, e->vertex_buffer_index, e->dual_slot, e->src_format, e->instance_divisor);
4422 }
4423 }
4424
4425 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4426 struct si_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4427 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32) == 16);
4428 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4429 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4430 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4431 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4432 int i;
4433
4434 assert(count <= SI_MAX_ATTRIBS);
4435 if (!v)
4436 return NULL;
4437
4438 v->count = count;
4439
4440 unsigned num_vbos_in_user_sgprs = si_num_vbos_in_user_sgprs(sscreen);
4441 unsigned alloc_count =
4442 count > num_vbos_in_user_sgprs ? count - num_vbos_in_user_sgprs : 0;
4443 v->vb_desc_list_alloc_size = align(alloc_count * 16, SI_CPDMA_ALIGNMENT);
4444
4445 for (i = 0; i < count; ++i) {
4446 const struct util_format_description *desc;
4447 const struct util_format_channel_description *channel;
4448 int first_non_void;
4449 unsigned vbo_index = elements[i].vertex_buffer_index;
4450
4451 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4452 FREE(v);
4453 return NULL;
4454 }
4455
4456 unsigned instance_divisor = elements[i].instance_divisor;
4457 if (instance_divisor) {
4458 if (instance_divisor == 1) {
4459 v->instance_divisor_is_one |= 1u << i;
4460 } else {
4461 v->instance_divisor_is_fetched |= 1u << i;
4462 divisor_factors[i] = si_compute_fast_udiv_info32(instance_divisor, 32);
4463 }
4464 }
4465
4466 desc = util_format_description(elements[i].src_format);
4467 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4468 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4469
4470 v->elem[i].format_size = desc->block.bits / 8;
4471 v->elem[i].src_offset = elements[i].src_offset;
4472 v->elem[i].stride = elements[i].src_stride;
4473 v->vertex_buffer_index[i] = vbo_index;
4474
4475 bool always_fix = false;
4476 union si_vs_fix_fetch fix_fetch;
4477 unsigned log_hw_load_size; /* the load element size as seen by the hardware */
4478
4479 fix_fetch.bits = 0;
4480 log_hw_load_size = MIN2(2, util_logbase2(desc->block.bits) - 3);
4481
4482 if (channel) {
4483 switch (channel->type) {
4484 case UTIL_FORMAT_TYPE_FLOAT:
4485 fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT;
4486 break;
4487 case UTIL_FORMAT_TYPE_FIXED:
4488 fix_fetch.u.format = AC_FETCH_FORMAT_FIXED;
4489 break;
4490 case UTIL_FORMAT_TYPE_SIGNED: {
4491 if (channel->pure_integer)
4492 fix_fetch.u.format = AC_FETCH_FORMAT_SINT;
4493 else if (channel->normalized)
4494 fix_fetch.u.format = AC_FETCH_FORMAT_SNORM;
4495 else
4496 fix_fetch.u.format = AC_FETCH_FORMAT_SSCALED;
4497 break;
4498 }
4499 case UTIL_FORMAT_TYPE_UNSIGNED: {
4500 if (channel->pure_integer)
4501 fix_fetch.u.format = AC_FETCH_FORMAT_UINT;
4502 else if (channel->normalized)
4503 fix_fetch.u.format = AC_FETCH_FORMAT_UNORM;
4504 else
4505 fix_fetch.u.format = AC_FETCH_FORMAT_USCALED;
4506 break;
4507 }
4508 default:
4509 unreachable("bad format type");
4510 }
4511 } else {
4512 switch (elements[i].src_format) {
4513 case PIPE_FORMAT_R11G11B10_FLOAT:
4514 fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT;
4515 break;
4516 default:
4517 unreachable("bad other format");
4518 }
4519 }
4520
4521 if (desc->channel[0].size == 10) {
4522 fix_fetch.u.log_size = 3; /* special encoding for 2_10_10_10 */
4523 log_hw_load_size = 2;
4524
4525 /* The hardware always treats the 2-bit alpha channel as
4526 * unsigned, so a shader workaround is needed. The affected
4527 * chips are GFX8 and older except Stoney (GFX8.1).
4528 */
4529 always_fix = sscreen->info.gfx_level <= GFX8 && sscreen->info.family != CHIP_STONEY &&
4530 channel->type == UTIL_FORMAT_TYPE_SIGNED;
4531 } else if (elements[i].src_format == PIPE_FORMAT_R11G11B10_FLOAT) {
4532 fix_fetch.u.log_size = 3; /* special encoding */
4533 fix_fetch.u.format = AC_FETCH_FORMAT_FIXED;
4534 log_hw_load_size = 2;
4535 } else {
4536 fix_fetch.u.log_size = util_logbase2(channel->size) - 3;
4537 fix_fetch.u.num_channels_m1 = desc->nr_channels - 1;
4538
4539 /* Always fix up:
4540 * - doubles (multiple loads + truncate to float)
4541 * - 32-bit requiring a conversion
4542 */
4543 always_fix = (fix_fetch.u.log_size == 3) ||
4544 (fix_fetch.u.log_size == 2 && fix_fetch.u.format != AC_FETCH_FORMAT_FLOAT &&
4545 fix_fetch.u.format != AC_FETCH_FORMAT_UINT &&
4546 fix_fetch.u.format != AC_FETCH_FORMAT_SINT);
4547
4548 /* Also fixup 8_8_8 and 16_16_16. */
4549 if (desc->nr_channels == 3 && fix_fetch.u.log_size <= 1) {
4550 always_fix = true;
4551 log_hw_load_size = fix_fetch.u.log_size;
4552 }
4553 }
4554
4555 if (desc->swizzle[0] != PIPE_SWIZZLE_X) {
4556 assert(desc->swizzle[0] == PIPE_SWIZZLE_Z &&
4557 (desc->swizzle[2] == PIPE_SWIZZLE_X || desc->swizzle[2] == PIPE_SWIZZLE_0));
4558 fix_fetch.u.reverse = 1;
4559 }
4560
4561 /* Force the workaround for unaligned access here already if the
4562 * offset relative to the vertex buffer base is unaligned.
4563 *
4564 * There is a theoretical case in which this is too conservative:
4565 * if the vertex buffer's offset is also unaligned in just the
4566 * right way, we end up with an aligned address after all.
4567 * However, this case should be extremely rare in practice (it
4568 * won't happen in well-behaved applications), and taking it
4569 * into account would complicate the fast path (where everything
4570 * is nicely aligned).
4571 */
4572 bool check_alignment =
4573 log_hw_load_size >= 1 &&
4574 (sscreen->info.gfx_level == GFX6 || sscreen->info.gfx_level >= GFX10);
4575 bool opencode = sscreen->options.vs_fetch_always_opencode;
4576
4577 if (check_alignment && ((elements[i].src_offset & ((1 << log_hw_load_size) - 1)) != 0 ||
4578 elements[i].src_stride & 3))
4579 opencode = true;
4580
4581 if (always_fix || check_alignment || opencode)
4582 v->fix_fetch[i] = fix_fetch.bits;
4583
4584 if (opencode)
4585 v->fix_fetch_opencode |= 1 << i;
4586 if (opencode || always_fix)
4587 v->fix_fetch_always |= 1 << i;
4588
4589 if (check_alignment && !opencode) {
4590 assert(log_hw_load_size == 1 || log_hw_load_size == 2);
4591
4592 v->fix_fetch_unaligned |= 1 << i;
4593 v->hw_load_is_dword |= (log_hw_load_size - 1) << i;
4594 v->vb_alignment_check_mask |= 1 << vbo_index;
4595 }
4596
4597 const struct ac_buffer_state buffer_state = {
4598 .format = elements[i].src_format,
4599 .swizzle =
4600 {
4601 desc->swizzle[0],
4602 desc->swizzle[1],
4603 desc->swizzle[2],
4604 desc->swizzle[3],
4605 },
4606 /* OOB_SELECT chooses the out-of-bounds check:
4607 * - 1: index >= NUM_RECORDS (Structured)
4608 * - 3: offset >= NUM_RECORDS (Raw)
4609 */
4610 .gfx10_oob_select = v->elem[i].stride ? V_008F0C_OOB_SELECT_STRUCTURED
4611 : V_008F0C_OOB_SELECT_RAW,
4612 };
4613
4614 ac_set_buf_desc_word3(sscreen->info.gfx_level, &buffer_state, &v->elem[i].rsrc_word3);
4615 }
4616
4617 if (v->instance_divisor_is_fetched) {
4618 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
4619
4620 v->instance_divisor_factor_buffer = (struct si_resource *)pipe_buffer_create(
4621 &sscreen->b, 0, PIPE_USAGE_DEFAULT, num_divisors * sizeof(divisor_factors[0]));
4622 if (!v->instance_divisor_factor_buffer) {
4623 FREE(v);
4624 return NULL;
4625 }
4626 void *map =
4627 sscreen->ws->buffer_map(sscreen->ws, v->instance_divisor_factor_buffer->buf, NULL, PIPE_MAP_WRITE);
4628 memcpy(map, divisor_factors, num_divisors * sizeof(divisor_factors[0]));
4629 }
4630 return v;
4631 }
4632
si_bind_vertex_elements(struct pipe_context * ctx,void * state)4633 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4634 {
4635 struct si_context *sctx = (struct si_context *)ctx;
4636 struct si_vertex_elements *old = sctx->vertex_elements;
4637 struct si_vertex_elements *v = (struct si_vertex_elements *)state;
4638
4639 if (!v)
4640 v = sctx->no_velems_state;
4641
4642 sctx->vertex_elements = v;
4643 sctx->num_vertex_elements = v->count;
4644 sctx->vertex_buffers_dirty = sctx->num_vertex_elements > 0;
4645
4646 if (old->instance_divisor_is_one != v->instance_divisor_is_one ||
4647 old->instance_divisor_is_fetched != v->instance_divisor_is_fetched ||
4648 (old->vb_alignment_check_mask ^ v->vb_alignment_check_mask) &
4649 sctx->vertex_buffer_unaligned ||
4650 ((v->vb_alignment_check_mask & sctx->vertex_buffer_unaligned) &&
4651 memcmp(old->vertex_buffer_index, v->vertex_buffer_index,
4652 sizeof(v->vertex_buffer_index[0]) * MAX2(old->count, v->count))) ||
4653 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
4654 * functions of fix_fetch and the src_offset alignment.
4655 * If they change and fix_fetch doesn't, it must be due to different
4656 * src_offset alignment, which is reflected in fix_fetch_opencode. */
4657 old->fix_fetch_opencode != v->fix_fetch_opencode ||
4658 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) *
4659 MAX2(old->count, v->count))) {
4660 si_vs_key_update_inputs(sctx);
4661 sctx->do_update_shaders = true;
4662 }
4663
4664 if (v->instance_divisor_is_fetched) {
4665 struct pipe_constant_buffer cb;
4666
4667 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
4668 cb.user_buffer = NULL;
4669 cb.buffer_offset = 0;
4670 cb.buffer_size = 0xffffffff;
4671 si_set_internal_const_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4672 }
4673 }
4674
si_delete_vertex_element(struct pipe_context * ctx,void * state)4675 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4676 {
4677 struct si_context *sctx = (struct si_context *)ctx;
4678 struct si_vertex_elements *v = (struct si_vertex_elements *)state;
4679
4680 if (sctx->vertex_elements == state)
4681 si_bind_vertex_elements(ctx, sctx->no_velems_state);
4682
4683 si_resource_reference(&v->instance_divisor_factor_buffer, NULL);
4684 FREE(state);
4685 }
4686
si_set_vertex_buffers(struct pipe_context * ctx,unsigned count,const struct pipe_vertex_buffer * buffers)4687 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
4688 const struct pipe_vertex_buffer *buffers)
4689 {
4690 struct si_context *sctx = (struct si_context *)ctx;
4691 uint32_t unaligned = 0;
4692 unsigned i;
4693
4694 assert(count <= ARRAY_SIZE(sctx->vertex_buffer));
4695 assert(!count || buffers);
4696
4697 for (i = 0; i < count; i++) {
4698 const struct pipe_vertex_buffer *src = buffers + i;
4699 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + i;
4700 struct pipe_resource *buf = src->buffer.resource;
4701
4702 dst->buffer_offset = src->buffer_offset;
4703
4704 /* Only unreference bound vertex buffers. */
4705 pipe_resource_reference(&dst->buffer.resource, NULL);
4706 dst->buffer.resource = src->buffer.resource;
4707
4708 if (src->buffer_offset & 3)
4709 unaligned |= BITFIELD_BIT(i);
4710
4711 if (buf) {
4712 si_resource(buf)->bind_history |= SI_BIND_VERTEX_BUFFER;
4713 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(buf),
4714 RADEON_USAGE_READ | RADEON_PRIO_VERTEX_BUFFER);
4715 }
4716 }
4717
4718 unsigned last_count = sctx->num_vertex_buffers;
4719 for (; i < last_count; i++)
4720 pipe_resource_reference(&sctx->vertex_buffer[i].buffer.resource, NULL);
4721
4722 sctx->num_vertex_buffers = count;
4723 sctx->vertex_buffers_dirty = sctx->num_vertex_elements > 0;
4724 sctx->vertex_buffer_unaligned = unaligned;
4725
4726 /* Check whether alignment may have changed in a way that requires
4727 * shader changes. This check is conservative: a vertex buffer can only
4728 * trigger a shader change if the misalignment amount changes (e.g.
4729 * from byte-aligned to short-aligned), but we only keep track of
4730 * whether buffers are at least dword-aligned, since that should always
4731 * be the case in well-behaved applications anyway.
4732 */
4733 if (sctx->vertex_elements->vb_alignment_check_mask & unaligned) {
4734 si_vs_key_update_inputs(sctx);
4735 sctx->do_update_shaders = true;
4736 }
4737 }
4738
4739 static struct pipe_vertex_state *
si_create_vertex_state(struct pipe_screen * screen,struct pipe_vertex_buffer * buffer,const struct pipe_vertex_element * elements,unsigned num_elements,struct pipe_resource * indexbuf,uint32_t full_velem_mask)4740 si_create_vertex_state(struct pipe_screen *screen,
4741 struct pipe_vertex_buffer *buffer,
4742 const struct pipe_vertex_element *elements,
4743 unsigned num_elements,
4744 struct pipe_resource *indexbuf,
4745 uint32_t full_velem_mask)
4746 {
4747 struct si_screen *sscreen = (struct si_screen *)screen;
4748 struct si_vertex_state *state = CALLOC_STRUCT(si_vertex_state);
4749
4750 util_init_pipe_vertex_state(screen, buffer, elements, num_elements, indexbuf, full_velem_mask,
4751 &state->b);
4752
4753 /* Initialize the vertex element state in state->element.
4754 * Do it by creating a vertex element state object and copying it there.
4755 */
4756 struct si_context ctx = {};
4757 ctx.b.screen = screen;
4758 struct si_vertex_elements *velems = si_create_vertex_elements(&ctx.b, num_elements, elements);
4759 state->velems = *velems;
4760 si_delete_vertex_element(&ctx.b, velems);
4761
4762 assert(!state->velems.instance_divisor_is_one);
4763 assert(!state->velems.instance_divisor_is_fetched);
4764 assert(!state->velems.fix_fetch_always);
4765 assert(buffer->buffer_offset % 4 == 0);
4766 assert(!buffer->is_user_buffer);
4767 for (unsigned i = 0; i < num_elements; i++) {
4768 assert(elements[i].src_offset % 4 == 0);
4769 assert(!elements[i].dual_slot);
4770 assert(elements[i].src_stride % 4 == 0);
4771 }
4772
4773 for (unsigned i = 0; i < num_elements; i++) {
4774 si_set_vertex_buffer_descriptor(sscreen, &state->velems, &state->b.input.vbuffer, i,
4775 &state->descriptors[i * 4]);
4776 }
4777
4778 return &state->b;
4779 }
4780
si_vertex_state_destroy(struct pipe_screen * screen,struct pipe_vertex_state * state)4781 static void si_vertex_state_destroy(struct pipe_screen *screen,
4782 struct pipe_vertex_state *state)
4783 {
4784 pipe_vertex_buffer_unreference(&state->input.vbuffer);
4785 pipe_resource_reference(&state->input.indexbuf, NULL);
4786 FREE(state);
4787 }
4788
4789 static struct pipe_vertex_state *
si_pipe_create_vertex_state(struct pipe_screen * screen,struct pipe_vertex_buffer * buffer,const struct pipe_vertex_element * elements,unsigned num_elements,struct pipe_resource * indexbuf,uint32_t full_velem_mask)4790 si_pipe_create_vertex_state(struct pipe_screen *screen,
4791 struct pipe_vertex_buffer *buffer,
4792 const struct pipe_vertex_element *elements,
4793 unsigned num_elements,
4794 struct pipe_resource *indexbuf,
4795 uint32_t full_velem_mask)
4796 {
4797 struct si_screen *sscreen = (struct si_screen *)screen;
4798
4799 return util_vertex_state_cache_get(screen, buffer, elements, num_elements, indexbuf,
4800 full_velem_mask, &sscreen->vertex_state_cache);
4801 }
4802
si_pipe_vertex_state_destroy(struct pipe_screen * screen,struct pipe_vertex_state * state)4803 static void si_pipe_vertex_state_destroy(struct pipe_screen *screen,
4804 struct pipe_vertex_state *state)
4805 {
4806 struct si_screen *sscreen = (struct si_screen *)screen;
4807
4808 util_vertex_state_destroy(screen, &sscreen->vertex_state_cache, state);
4809 }
4810
4811 /*
4812 * Misc
4813 */
4814
si_set_tess_state(struct pipe_context * ctx,const float default_outer_level[4],const float default_inner_level[2])4815 static void si_set_tess_state(struct pipe_context *ctx, const float default_outer_level[4],
4816 const float default_inner_level[2])
4817 {
4818 struct si_context *sctx = (struct si_context *)ctx;
4819 struct pipe_constant_buffer cb;
4820 float array[8];
4821
4822 memcpy(array, default_outer_level, sizeof(float) * 4);
4823 memcpy(array + 4, default_inner_level, sizeof(float) * 2);
4824
4825 cb.buffer = NULL;
4826 cb.user_buffer = array;
4827 cb.buffer_offset = 0;
4828 cb.buffer_size = sizeof(array);
4829
4830 si_set_internal_const_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4831 }
4832
si_create_blend_custom(struct si_context * sctx,unsigned mode)4833 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4834 {
4835 struct pipe_blend_state blend;
4836
4837 memset(&blend, 0, sizeof(blend));
4838 blend.independent_blend_enable = true;
4839 blend.rt[0].colormask = 0xf;
4840 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4841 }
4842
si_pm4_emit_sqtt_pipeline(struct si_context * sctx,unsigned index)4843 static void si_pm4_emit_sqtt_pipeline(struct si_context *sctx, unsigned index)
4844 {
4845 struct si_pm4_state *state = sctx->queued.array[index];
4846
4847 si_pm4_emit_state(sctx, index);
4848
4849 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, ((struct si_sqtt_fake_pipeline*)state)->bo,
4850 RADEON_USAGE_READ | RADEON_PRIO_SHADER_BINARY);
4851 }
4852
si_init_state_compute_functions(struct si_context * sctx)4853 void si_init_state_compute_functions(struct si_context *sctx)
4854 {
4855 sctx->b.create_sampler_state = si_create_sampler_state;
4856 sctx->b.delete_sampler_state = si_delete_sampler_state;
4857 sctx->b.create_sampler_view = si_create_sampler_view;
4858 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4859 }
4860
si_init_state_functions(struct si_context * sctx)4861 void si_init_state_functions(struct si_context *sctx)
4862 {
4863 sctx->atoms.s.pm4_states[SI_STATE_IDX(blend)].emit = si_pm4_emit_state;
4864 sctx->atoms.s.pm4_states[SI_STATE_IDX(rasterizer)].emit = si_pm4_emit_rasterizer;
4865 sctx->atoms.s.pm4_states[SI_STATE_IDX(dsa)].emit = si_pm4_emit_dsa;
4866 sctx->atoms.s.pm4_states[SI_STATE_IDX(sqtt_pipeline)].emit = si_pm4_emit_sqtt_pipeline;
4867 sctx->atoms.s.pm4_states[SI_STATE_IDX(ls)].emit = si_pm4_emit_shader;
4868 sctx->atoms.s.pm4_states[SI_STATE_IDX(hs)].emit = si_pm4_emit_shader;
4869 sctx->atoms.s.pm4_states[SI_STATE_IDX(es)].emit = si_pm4_emit_shader;
4870 sctx->atoms.s.pm4_states[SI_STATE_IDX(gs)].emit = si_pm4_emit_shader;
4871 sctx->atoms.s.pm4_states[SI_STATE_IDX(vs)].emit = si_pm4_emit_shader;
4872 sctx->atoms.s.pm4_states[SI_STATE_IDX(ps)].emit = si_pm4_emit_shader;
4873
4874 if (sctx->gfx_level >= GFX12)
4875 sctx->atoms.s.framebuffer.emit = gfx12_emit_framebuffer_state;
4876 else if (sctx->screen->info.has_set_context_pairs_packed)
4877 sctx->atoms.s.framebuffer.emit = gfx11_dgpu_emit_framebuffer_state;
4878 else
4879 sctx->atoms.s.framebuffer.emit = gfx6_emit_framebuffer_state;
4880
4881 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
4882 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
4883 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
4884 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
4885 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
4886 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
4887 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
4888 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
4889 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
4890
4891 sctx->b.create_blend_state = si_create_blend_state;
4892 sctx->b.bind_blend_state = si_bind_blend_state;
4893 sctx->b.delete_blend_state = si_delete_blend_state;
4894 sctx->b.set_blend_color = si_set_blend_color;
4895
4896 sctx->b.create_rasterizer_state = si_create_rs_state;
4897 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4898 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4899
4900 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4901 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4902 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4903
4904 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4905
4906 if (sctx->gfx_level < GFX11) {
4907 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4908 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4909 sctx->custom_blend_eliminate_fastclear =
4910 si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4911 }
4912
4913 sctx->custom_blend_dcc_decompress =
4914 si_create_blend_custom(sctx,
4915 sctx->gfx_level >= GFX12 ? V_028858_CB_DCC_DECOMPRESS :
4916 sctx->gfx_level >= GFX11 ? V_028808_CB_DCC_DECOMPRESS_GFX11 :
4917 V_028808_CB_DCC_DECOMPRESS_GFX8);
4918
4919 sctx->b.set_clip_state = si_set_clip_state;
4920 sctx->b.set_stencil_ref = si_set_stencil_ref;
4921
4922 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4923
4924 sctx->b.set_sample_mask = si_set_sample_mask;
4925
4926 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4927 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4928 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4929 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4930
4931 sctx->b.set_min_samples = si_set_min_samples;
4932 sctx->b.set_tess_state = si_set_tess_state;
4933
4934 sctx->b.set_active_query_state = si_set_active_query_state;
4935 }
4936
si_init_screen_state_functions(struct si_screen * sscreen)4937 void si_init_screen_state_functions(struct si_screen *sscreen)
4938 {
4939 sscreen->b.is_format_supported = si_is_format_supported;
4940 sscreen->b.create_vertex_state = si_pipe_create_vertex_state;
4941 sscreen->b.vertex_state_destroy = si_pipe_vertex_state_destroy;
4942
4943 util_vertex_state_cache_init(&sscreen->vertex_state_cache,
4944 si_create_vertex_state, si_vertex_state_destroy);
4945 }
4946
si_init_compute_preamble_state(struct si_context * sctx,struct si_pm4_state * pm4)4947 static void si_init_compute_preamble_state(struct si_context *sctx,
4948 struct si_pm4_state *pm4)
4949 {
4950 uint64_t border_color_va =
4951 sctx->border_color_buffer ? sctx->border_color_buffer->gpu_address : 0;
4952
4953 const struct ac_preamble_state preamble_state = {
4954 .border_color_va = border_color_va,
4955 .gfx11 = {
4956 .compute_dispatch_interleave = 256,
4957 },
4958 };
4959
4960 ac_init_compute_preamble_state(&preamble_state, &pm4->base);
4961
4962 if (sctx->gfx_level == GFX10 || sctx->gfx_level == GFX10_3)
4963 ac_pm4_set_reg(&pm4->base, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
4964 }
4965
4966
si_init_graphics_preamble_state(struct si_context * sctx,struct si_pm4_state * pm4)4967 static void si_init_graphics_preamble_state(struct si_context *sctx,
4968 struct si_pm4_state *pm4)
4969 {
4970 struct si_screen *sscreen = sctx->screen;
4971 uint64_t border_color_va =
4972 sctx->border_color_buffer ? sctx->border_color_buffer->gpu_address : 0;
4973
4974 const struct ac_preamble_state preamble_state = {
4975 .border_color_va = border_color_va,
4976 .gfx10.cache_rb_gl2 = sctx->gfx_level >= GFX10 && sscreen->options.cache_rb_gl2,
4977 };
4978
4979 ac_init_graphics_preamble_state(&preamble_state, &pm4->base);
4980
4981 if (sctx->gfx_level >= GFX7) {
4982 /* If any sample location uses the -8 coordinate, the EXCLUSION fields should be set to 0. */
4983 ac_pm4_set_reg(&pm4->base, R_02882C_PA_SU_PRIM_FILTER_CNTL,
4984 S_02882C_XMAX_RIGHT_EXCLUSION(1) |
4985 S_02882C_YMAX_BOTTOM_EXCLUSION(1));
4986 }
4987 }
4988
gfx6_init_gfx_preamble_state(struct si_context * sctx)4989 static void gfx6_init_gfx_preamble_state(struct si_context *sctx)
4990 {
4991 struct si_screen *sscreen = sctx->screen;
4992 bool has_clear_state = sscreen->info.has_clear_state;
4993
4994 /* We need more space because the preamble is large. */
4995 struct si_pm4_state *pm4 = si_pm4_create_sized(sscreen, 214, sctx->has_graphics);
4996 if (!pm4)
4997 return;
4998
4999 if (sctx->has_graphics && !sctx->shadowing.registers) {
5000 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
5001 ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1));
5002 ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1));
5003
5004 if (sscreen->dpbb_allowed) {
5005 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_EVENT_WRITE, 0, 0));
5006 ac_pm4_cmd_add(&pm4->base, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
5007 }
5008
5009 if (has_clear_state) {
5010 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CLEAR_STATE, 0, 0));
5011 ac_pm4_cmd_add(&pm4->base, 0);
5012 }
5013 }
5014
5015 si_init_compute_preamble_state(sctx, pm4);
5016
5017 if (!sctx->has_graphics)
5018 goto done;
5019
5020 /* Graphics registers. */
5021 si_init_graphics_preamble_state(sctx, pm4);
5022
5023 if (!has_clear_state)
5024 ac_pm4_set_reg(&pm4->base, R_02800C_DB_RENDER_OVERRIDE, 0);
5025
5026 if (sctx->family >= CHIP_POLARIS10 && !sctx->screen->info.has_small_prim_filter_sample_loc_bug) {
5027 /* Polaris10-12 should disable small line culling, but those also have the sample loc bug,
5028 * so they never enter this branch.
5029 */
5030 assert(sctx->family > CHIP_POLARIS12);
5031 ac_pm4_set_reg(&pm4->base, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
5032 S_028830_SMALL_PRIM_FILTER_ENABLE(1));
5033 }
5034
5035 if (sctx->gfx_level <= GFX7 || !has_clear_state) {
5036 ac_pm4_set_reg(&pm4->base, R_028034_PA_SC_SCREEN_SCISSOR_BR,
5037 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5038 }
5039
5040 if (sctx->gfx_level == GFX9) {
5041 ac_pm4_set_reg(&pm4->base, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5042 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5043 }
5044
5045 done:
5046 ac_pm4_finalize(&pm4->base);
5047 sctx->cs_preamble_state = pm4;
5048 sctx->cs_preamble_state_tmz = si_pm4_clone(sscreen, pm4); /* Make a copy of the preamble for TMZ. */
5049 }
5050
cdna_init_compute_preamble_state(struct si_context * sctx)5051 static void cdna_init_compute_preamble_state(struct si_context *sctx)
5052 {
5053 struct si_screen *sscreen = sctx->screen;
5054 uint64_t border_color_va =
5055 sctx->border_color_buffer ? sctx->border_color_buffer->gpu_address : 0;
5056 uint32_t compute_cu_en = S_00B858_SH0_CU_EN(sscreen->info.spi_cu_en) |
5057 S_00B858_SH1_CU_EN(sscreen->info.spi_cu_en);
5058
5059 struct si_pm4_state *pm4 = si_pm4_create_sized(sscreen, 48, true);
5060 if (!pm4)
5061 return;
5062
5063 /* Compute registers. */
5064 /* Disable profiling on compute chips. */
5065 ac_pm4_set_reg(&pm4->base, R_00B82C_COMPUTE_PERFCOUNT_ENABLE, 0);
5066 ac_pm4_set_reg(&pm4->base, R_00B834_COMPUTE_PGM_HI, S_00B834_DATA(sctx->screen->info.address32_hi >> 8));
5067 ac_pm4_set_reg(&pm4->base, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, compute_cu_en);
5068 ac_pm4_set_reg(&pm4->base, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1, compute_cu_en);
5069 ac_pm4_set_reg(&pm4->base, R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, compute_cu_en);
5070 ac_pm4_set_reg(&pm4->base, R_00B868_COMPUTE_STATIC_THREAD_MGMT_SE3, compute_cu_en);
5071 ac_pm4_set_reg(&pm4->base, R_00B878_COMPUTE_THREAD_TRACE_ENABLE, 0);
5072
5073 if (sscreen->info.family >= CHIP_GFX940) {
5074 ac_pm4_set_reg(&pm4->base, R_00B89C_COMPUTE_TG_CHUNK_SIZE, 0);
5075 ac_pm4_set_reg(&pm4->base, R_00B8B4_COMPUTE_PGM_RSRC3, 0);
5076 } else {
5077 ac_pm4_set_reg(&pm4->base, R_00B894_COMPUTE_STATIC_THREAD_MGMT_SE4, compute_cu_en);
5078 ac_pm4_set_reg(&pm4->base, R_00B898_COMPUTE_STATIC_THREAD_MGMT_SE5, compute_cu_en);
5079 ac_pm4_set_reg(&pm4->base, R_00B89C_COMPUTE_STATIC_THREAD_MGMT_SE6, compute_cu_en);
5080 ac_pm4_set_reg(&pm4->base, R_00B8A0_COMPUTE_STATIC_THREAD_MGMT_SE7, compute_cu_en);
5081 }
5082
5083 ac_pm4_set_reg(&pm4->base, R_0301EC_CP_COHER_START_DELAY, 0);
5084
5085 /* Set the pointer to border colors. Only MI100 supports border colors. */
5086 if (sscreen->info.family == CHIP_MI100) {
5087 ac_pm4_set_reg(&pm4->base, R_030E00_TA_CS_BC_BASE_ADDR, border_color_va >> 8);
5088 ac_pm4_set_reg(&pm4->base, R_030E04_TA_CS_BC_BASE_ADDR_HI,
5089 S_030E04_ADDRESS(border_color_va >> 40));
5090 }
5091
5092 ac_pm4_finalize(&pm4->base);
5093 sctx->cs_preamble_state = pm4;
5094 sctx->cs_preamble_state_tmz = si_pm4_clone(sscreen, pm4); /* Make a copy of the preamble for TMZ. */
5095 }
5096
gfx10_init_gfx_preamble_state(struct si_context * sctx)5097 static void gfx10_init_gfx_preamble_state(struct si_context *sctx)
5098 {
5099 struct si_screen *sscreen = sctx->screen;
5100
5101 /* We need more space because the preamble is large. */
5102 struct si_pm4_state *pm4 = si_pm4_create_sized(sscreen, 214, sctx->has_graphics);
5103 if (!pm4)
5104 return;
5105
5106 if (sctx->has_graphics && !sctx->shadowing.registers) {
5107 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
5108 ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1));
5109 ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1));
5110
5111 if (sscreen->dpbb_allowed) {
5112 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_EVENT_WRITE, 0, 0));
5113 ac_pm4_cmd_add(&pm4->base, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
5114 }
5115
5116 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CLEAR_STATE, 0, 0));
5117 ac_pm4_cmd_add(&pm4->base, 0);
5118 }
5119
5120 si_init_compute_preamble_state(sctx, pm4);
5121
5122 if (!sctx->has_graphics)
5123 goto done;
5124
5125 /* Graphics registers. */
5126 si_init_graphics_preamble_state(sctx, pm4);
5127
5128 ac_pm4_set_reg(&pm4->base, R_028708_SPI_SHADER_IDX_FORMAT,
5129 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
5130
5131 if (sctx->gfx_level >= GFX10_3) {
5132 /* The rate combiners have no effect if they are disabled like this:
5133 * VERTEX_RATE: BYPASS_VTX_RATE_COMBINER = 1
5134 * PRIMITIVE_RATE: BYPASS_PRIM_RATE_COMBINER = 1
5135 * HTILE_RATE: VRS_HTILE_ENCODING = 0
5136 * SAMPLE_ITER: PS_ITER_SAMPLE = 0
5137 *
5138 * Use OVERRIDE, which will ignore results from previous combiners.
5139 * (e.g. enabled sample shading overrides the vertex rate)
5140 */
5141 ac_pm4_set_reg(&pm4->base, R_028848_PA_CL_VRS_CNTL,
5142 S_028848_VERTEX_RATE_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE) |
5143 S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE));
5144 }
5145
5146 done:
5147 ac_pm4_finalize(&pm4->base);
5148 sctx->cs_preamble_state = pm4;
5149 sctx->cs_preamble_state_tmz = si_pm4_clone(sscreen, pm4); /* Make a copy of the preamble for TMZ. */
5150 }
5151
gfx12_init_gfx_preamble_state(struct si_context * sctx)5152 static void gfx12_init_gfx_preamble_state(struct si_context *sctx)
5153 {
5154 struct si_screen *sscreen = sctx->screen;
5155
5156 struct si_pm4_state *pm4 = si_pm4_create_sized(sscreen, 300, sctx->has_graphics);
5157 if (!pm4)
5158 return;
5159
5160 if (sctx->has_graphics && !sctx->shadowing.registers) {
5161 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
5162 ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1));
5163 ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1));
5164 }
5165
5166 if (sctx->has_graphics && sscreen->dpbb_allowed) {
5167 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_EVENT_WRITE, 0, 0));
5168 ac_pm4_cmd_add(&pm4->base, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
5169 }
5170
5171 si_init_compute_preamble_state(sctx, pm4);
5172
5173 if (!sctx->has_graphics)
5174 goto done;
5175
5176 /* Graphics registers. */
5177 si_init_graphics_preamble_state(sctx, pm4);
5178
5179 ac_pm4_set_reg(&pm4->base, R_028648_SPI_SHADER_IDX_FORMAT,
5180 S_028648_IDX0_EXPORT_FORMAT(V_028648_SPI_SHADER_1COMP));
5181
5182 /* The rate combiners have no effect if they are disabled like this:
5183 * VERTEX_RATE: BYPASS_VTX_RATE_COMBINER = 1
5184 * PRIMITIVE_RATE: BYPASS_PRIM_RATE_COMBINER = 1
5185 * HTILE_RATE: VRS_HTILE_ENCODING = 0
5186 * SAMPLE_ITER: PS_ITER_SAMPLE = 0
5187 *
5188 * Use OVERRIDE, which will ignore results from previous combiners.
5189 * (e.g. enabled sample shading overrides the vertex rate)
5190 */
5191 ac_pm4_set_reg(&pm4->base, R_028848_PA_CL_VRS_CNTL,
5192 S_028848_VERTEX_RATE_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE) |
5193 S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE));
5194
5195 ac_pm4_set_reg(&pm4->base, R_028C54_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5196 S_028C54_NULL_SQUAD_AA_MASK_ENABLE(1));
5197
5198 done:
5199 sctx->cs_preamble_state = pm4;
5200 sctx->cs_preamble_state_tmz = si_pm4_clone(sscreen, pm4); /* Make a copy of the preamble for TMZ. */
5201 }
5202
si_init_gfx_preamble_state(struct si_context * sctx)5203 void si_init_gfx_preamble_state(struct si_context *sctx)
5204 {
5205 if (!sctx->screen->info.has_graphics)
5206 cdna_init_compute_preamble_state(sctx);
5207 else if (sctx->gfx_level >= GFX12)
5208 gfx12_init_gfx_preamble_state(sctx);
5209 else if (sctx->gfx_level >= GFX10)
5210 gfx10_init_gfx_preamble_state(sctx);
5211 else
5212 gfx6_init_gfx_preamble_state(sctx);
5213 }
5214