1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <arch/romstage.h>
4 #include <cbmem.h>
5 #include <cf9_reset.h>
6 #include <console/console.h>
7 #include <elog.h>
8 #include <fsp/util.h>
9 #include <intelblocks/cfg.h>
10 #include <intelblocks/cse.h>
11 #include <intelblocks/early_graphics.h>
12 #include <intelblocks/oc_wdt.h>
13 #include <intelblocks/pcr.h>
14 #include <intelblocks/pmclib.h>
15 #include <intelblocks/smbus.h>
16 #include <intelblocks/thermal.h>
17 #include <intelblocks/vtd.h>
18 #include <intelbasecode/debug_feature.h>
19 #include <memory_info.h>
20 #include <soc/intel/common/smbios.h>
21 #include <soc/iomap.h>
22 #include <soc/pm.h>
23 #include <soc/romstage.h>
24 #include <soc/soc_chip.h>
25 #include <cpu/intel/cpu_ids.h>
26 #include <string.h>
27 #include <security/intel/txt/txt.h>
28 #include <soc/pcr_ids.h>
29
30 #define PSF_UFS0_BASE_ADDRESS 0x280
31 #define PSF_UFS1_BASE_ADDRESS 0x300
32 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C
33 #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8)
34
disable_ufs(void)35 static void disable_ufs(void)
36 {
37 /* disable USF0 */
38 pcr_or32(PID_PSF2, PSF_UFS0_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN,
39 PCR_PSFX_T0_SHDW_PCIEN_FUNDIS);
40
41 /* disable USF1 */
42 pcr_or32(PID_PSF2, PSF_UFS1_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN,
43 PCR_PSFX_T0_SHDW_PCIEN_FUNDIS);
44 }
45
46 #include "ux.h"
47
48 #define FSP_SMBIOS_MEMORY_INFO_GUID \
49 { \
50 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \
51 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \
52 }
53
skip_cse_sub_part_update(void)54 bool skip_cse_sub_part_update(void)
55 {
56 return cpu_get_cpuid() != CPUID_ALDERLAKE_K0;
57 }
58
59 /* Save the DIMM information for SMBIOS table 17 */
save_dimm_info(void)60 static void save_dimm_info(void)
61 {
62 int node, channel, dimm, dimm_max, index;
63 size_t hob_size;
64 const CONTROLLER_INFO *ctrlr_info;
65 const CHANNEL_INFO *channel_info;
66 const DIMM_INFO *src_dimm;
67 struct dimm_info *dest_dimm;
68 struct memory_info *mem_info;
69 const MEMORY_INFO_DATA_HOB *meminfo_hob;
70 const uint8_t smbios_memory_info_guid[sizeof(EFI_GUID)] = FSP_SMBIOS_MEMORY_INFO_GUID;
71 const uint8_t *serial_num;
72 const char *dram_part_num = NULL;
73 size_t dram_part_num_len = 0;
74
75 /* Locate the memory info HOB, presence validated by raminit */
76 meminfo_hob = fsp_find_extension_hob_by_guid(
77 smbios_memory_info_guid,
78 &hob_size);
79 if (meminfo_hob == NULL || hob_size == 0) {
80 printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n");
81 return;
82 }
83
84 /*
85 * Allocate CBMEM area for DIMM information used to populate SMBIOS
86 * table 17
87 */
88 mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
89 if (mem_info == NULL) {
90 printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n");
91 return;
92 }
93 memset(mem_info, 0, sizeof(*mem_info));
94
95 /* Allow mainboard to override DRAM part number. */
96 dram_part_num = mainboard_get_dram_part_num();
97 if (dram_part_num)
98 dram_part_num_len = strlen(dram_part_num);
99
100 /* Save available DIMM information */
101 index = 0;
102 dimm_max = ARRAY_SIZE(mem_info->dimm);
103 for (node = 0; node < MAX_NODE; node++) {
104 ctrlr_info = &meminfo_hob->Controller[node];
105 for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) {
106 channel_info = &ctrlr_info->ChannelInfo[channel];
107 if (channel_info->Status != CHANNEL_PRESENT)
108 continue;
109
110 for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) {
111 src_dimm = &channel_info->DimmInfo[dimm];
112 dest_dimm = &mem_info->dimm[index];
113 if (src_dimm->Status != DIMM_PRESENT)
114 continue;
115
116 /* If there is no DRAM part number overridden by
117 * mainboard then use original one. */
118 if (!dram_part_num) {
119 dram_part_num_len = sizeof(src_dimm->ModulePartNum);
120 dram_part_num = (const char *)
121 &src_dimm->ModulePartNum[0];
122 }
123
124 uint8_t memProfNum = meminfo_hob->MemoryProfile;
125 serial_num = src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL;
126
127 /* Populate the DIMM information */
128 dimm_info_fill(dest_dimm,
129 src_dimm->DimmCapacity,
130 meminfo_hob->MemoryType,
131 meminfo_hob->ConfiguredMemoryClockSpeed,
132 src_dimm->RankInDimm,
133 channel_info->ChannelId,
134 src_dimm->DimmId,
135 dram_part_num,
136 dram_part_num_len,
137 serial_num,
138 meminfo_hob->DataWidth,
139 meminfo_hob->VddVoltage[memProfNum],
140 meminfo_hob->EccSupport,
141 src_dimm->MfgId,
142 src_dimm->SpdModuleType,
143 node,
144 meminfo_hob->MaximumMemoryClockSpeed);
145 index++;
146 }
147 }
148 }
149 mem_info->dimm_cnt = index;
150 printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
151 }
152
cse_fw_update_misc_oper(void)153 void cse_fw_update_misc_oper(void)
154 {
155 if (ux_inform_user_of_update_operation("CSE update"))
156 elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC);
157 }
158
cse_board_reset(void)159 void cse_board_reset(void)
160 {
161 early_graphics_stop();
162 }
163
mainboard_romstage_entry(void)164 void mainboard_romstage_entry(void)
165 {
166 struct chipset_power_state *ps = pmc_get_power_state();
167 bool s3wake = pmc_fill_power_state(ps) == ACPI_S3;
168
169 setup_oc_wdt();
170
171 /* Initialize HECI interface */
172 cse_init(HECI1_BASE_ADDRESS);
173
174 if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE))
175 dbg_feature_cntrl_init();
176
177 /*
178 * Disable Intel TXT if `CPU is unsupported` or `SoC haven't selected the config`.
179 *
180 * It would help to access VGA framebuffer prior calling into CSE
181 * firmware update or FSP-M.
182 */
183 if (!CONFIG(INTEL_TXT))
184 disable_intel_txt();
185
186 if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake)
187 cse_fw_sync();
188
189 /* Program to Disable UFS Controllers */
190 if (!is_devfn_enabled(PCH_DEVFN_UFS) &&
191 (CONFIG(USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS))) {
192 printk(BIOS_INFO, "Disabling UFS controllers\n");
193 disable_ufs();
194 if (ps->prev_sleep_state == ACPI_S5) {
195 printk(BIOS_INFO, "Warm Reset after disabling UFS controllers\n");
196 system_reset();
197 }
198 }
199
200 /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
201 systemagent_early_init();
202 /* Program SMBus base address and enable it */
203 smbus_common_init();
204
205
206 /* Update coreboot timestamp table with CSE timestamps */
207 if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY))
208 cse_get_telemetry_data();
209
210 /*
211 * Set low maximum temp threshold value used for dynamic thermal sensor
212 * shutdown consideration.
213 *
214 * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the
215 * thermal sensor when CPU is in a C-state and LTT >= DTS Temp.
216 */
217 pch_thermal_configuration();
218
219 fsp_memory_init(s3wake);
220 pmc_set_disb();
221 if (!s3wake)
222 save_dimm_info();
223
224 /*
225 * Turn-off early graphics configuration with two purposes:
226 * - Clear any potentially still on-screen message
227 * - Allow PEIM graphics driver to smoothly execute in ramstage if
228 * RUN_FSP_GOP is selected
229 */
230 early_graphics_stop();
231
232 if (CONFIG(ENABLE_EARLY_DMA_PROTECTION))
233 vtd_enable_dma_protection();
234 }
235