1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_MEDIATEK_MT8183_SMI_H 4 #define SOC_MEDIATEK_MT8183_SMI_H 5 6 #include <soc/addressmap.h> 7 #include <types.h> 8 9 struct mt8183_smi_regs { 10 u32 reserved1[64]; 11 u32 smi_l1len; 12 u32 smi_l1arb0; 13 u32 smi_l1arb1; 14 u32 smi_l1arb2; 15 u32 smi_l1arb3; 16 u32 smi_l1arb4; 17 u32 smi_l1arb5; 18 u32 smi_l1arb6; 19 u32 smi_l1arb7; 20 u32 reserved2[31]; 21 u32 smi_mon_axi_ena; 22 u32 smi_mon_axi_clr; 23 u32 reserved3[1]; 24 u32 smi_mon_axi_type; 25 u32 smi_mon_axi_con; 26 u32 reserved4[3]; 27 u32 smi_mon_axi_act_cnt; 28 u32 smi_mon_axi_req_cnt; 29 u32 smi_mon_axi_ostd_cnt; 30 u32 smi_mon_axi_bea_cnt; 31 u32 smi_mon_axi_byt_cnt; 32 u32 smi_mon_axi_cp_cnt; 33 u32 smi_mon_axi_dp_cnt; 34 u32 smi_mon_axi_cp_max; 35 u32 smi_mon_axi_cos_max; 36 u32 reserved5[15]; 37 u32 smi_bus_sel; 38 u32 reserved6[1]; 39 u32 smi_wrr_reg0; 40 u32 smi_wrr_reg1; 41 u32 smi_read_fifo_th; 42 u32 smi_m4u_th; 43 u32 smi_fifo_th1; 44 u32 smi_fifo_th2; 45 u32 smi_preultra_mask0; 46 u32 smi_preultra_mask1; 47 u32 reserved7[46]; 48 u32 smi_dcm; 49 u32 smi_ela; 50 u32 smi_m1_rultra_wrr0; 51 u32 smi_m1_rultra_wrr1; 52 u32 smi_m1_wultra_wrr0; 53 u32 smi_m1_wultra_wrr1; 54 u32 smi_m2_rultra_wrr0; 55 u32 smi_m2_rultra_wrr1; 56 u32 smi_m2_wultra_wrr0; 57 u32 smi_m2_wultra_wrr1; 58 u32 reserved8[38]; 59 u32 smi_common_clamp_en; 60 u32 smi_common_clamp_en_set; 61 u32 smi_common_clamp_en_clr; 62 u32 reserved9[13]; 63 u32 smi_debug_s0; 64 u32 smi_debug_s1; 65 u32 smi_debug_s2; 66 u32 smi_debug_s3; 67 u32 smi_debug_s4; 68 u32 smi_debug_s5; 69 u32 smi_debug_s6; 70 u32 smi_debug_s7; 71 u32 reserved10[4]; 72 u32 smi_debug_m0; 73 u32 smi_debug_m1; 74 u32 reserved11[2]; 75 u32 smi_debug_misc; 76 u32 smi_dummy; 77 u32 reserved12[46]; 78 u32 smi_hist_rec0; 79 u32 smi_hist_rec_data0; 80 u32 smi_hist_rec_data1; 81 u32 smi_hist_rec_data2; 82 u32 smi_hist_rec_data3; 83 u32 smi_hist_rec_data4; 84 u32 smi_hist_rec_data5; 85 u32 smi_hist_rec_data6; 86 u32 smi_hist_rec_data7; 87 u32 smi_hist_rec_data8; 88 u32 smi_hist_rec_data9; 89 }; 90 91 check_member(mt8183_smi_regs, smi_l1len, 0x0100); 92 check_member(mt8183_smi_regs, smi_mon_axi_ena, 0x01a0); 93 check_member(mt8183_smi_regs, smi_mon_axi_act_cnt, 0x01c0); 94 check_member(mt8183_smi_regs, smi_bus_sel, 0x0220); 95 check_member(mt8183_smi_regs, smi_dcm, 0x0300); 96 check_member(mt8183_smi_regs, smi_common_clamp_en, 0x03c0); 97 check_member(mt8183_smi_regs, smi_debug_s0, 0x0400); 98 check_member(mt8183_smi_regs, smi_debug_m0, 0x0430); 99 check_member(mt8183_smi_regs, smi_debug_misc, 0x0440); 100 check_member(mt8183_smi_regs, smi_hist_rec0, 0x0500); 101 check_member(mt8183_smi_regs, smi_hist_rec_data9, 0x0528); 102 103 static struct mt8183_smi_regs *const mt8183_smi = (void *)SMI_BASE; 104 105 #endif /* SOC_MEDIATEK_MT8183_SMI_H */ 106