1 /*
2 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
3 * Copyright (c) 2024, Altera Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9 #include <errno.h>
10 #include <common/debug.h>
11 #include <drivers/delay_timer.h>
12 #include <lib/mmio.h>
13 #include <platform_def.h>
14
15 #include "socfpga_f2sdram_manager.h"
16 #include "socfpga_mailbox.h"
17 #include "socfpga_plat_def.h"
18 #include "socfpga_reset_manager.h"
19 #include "socfpga_system_manager.h"
20
deassert_peripheral_reset(void)21 void deassert_peripheral_reset(void)
22 {
23 mmio_clrbits_32(SOCFPGA_RSTMGR(PER1MODRST),
24 RSTMGR_FIELD(PER1, WATCHDOG0) |
25 RSTMGR_FIELD(PER1, WATCHDOG1) |
26 RSTMGR_FIELD(PER1, WATCHDOG2) |
27 RSTMGR_FIELD(PER1, WATCHDOG3) |
28 RSTMGR_FIELD(PER1, WATCHDOG4) |
29 RSTMGR_FIELD(PER1, L4SYSTIMER0) |
30 RSTMGR_FIELD(PER1, L4SYSTIMER1) |
31 RSTMGR_FIELD(PER1, SPTIMER0) |
32 RSTMGR_FIELD(PER1, SPTIMER1) |
33 RSTMGR_FIELD(PER1, I2C0) |
34 RSTMGR_FIELD(PER1, I2C1) |
35 RSTMGR_FIELD(PER1, I2C2) |
36 RSTMGR_FIELD(PER1, I2C3) |
37 RSTMGR_FIELD(PER1, I2C4) |
38 RSTMGR_FIELD(PER1, I3C0) |
39 RSTMGR_FIELD(PER1, I3C1) |
40 RSTMGR_FIELD(PER1, UART0) |
41 RSTMGR_FIELD(PER1, UART1) |
42 RSTMGR_FIELD(PER1, GPIO0) |
43 RSTMGR_FIELD(PER1, GPIO1));
44
45 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST),
46 RSTMGR_FIELD(PER0, SOFTPHY) |
47 RSTMGR_FIELD(PER0, EMAC0OCP) |
48 RSTMGR_FIELD(PER0, EMAC1OCP) |
49 RSTMGR_FIELD(PER0, EMAC2OCP) |
50 RSTMGR_FIELD(PER0, USB0OCP) |
51 RSTMGR_FIELD(PER0, USB1OCP) |
52 RSTMGR_FIELD(PER0, NANDOCP) |
53 RSTMGR_FIELD(PER0, SDMMCOCP) |
54 RSTMGR_FIELD(PER0, DMAOCP));
55
56 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST),
57 RSTMGR_FIELD(PER0, EMAC0) |
58 RSTMGR_FIELD(PER0, EMAC1) |
59 RSTMGR_FIELD(PER0, EMAC2) |
60 RSTMGR_FIELD(PER0, USB0) |
61 RSTMGR_FIELD(PER0, USB1) |
62 RSTMGR_FIELD(PER0, NAND) |
63 RSTMGR_FIELD(PER0, SDMMC) |
64 RSTMGR_FIELD(PER0, DMA) |
65 RSTMGR_FIELD(PER0, SPIM0) |
66 RSTMGR_FIELD(PER0, SPIM1) |
67 RSTMGR_FIELD(PER0, SPIS0) |
68 RSTMGR_FIELD(PER0, SPIS1) |
69 RSTMGR_FIELD(PER0, EMACPTP) |
70 RSTMGR_FIELD(PER0, DMAIF0) |
71 RSTMGR_FIELD(PER0, DMAIF1) |
72 RSTMGR_FIELD(PER0, DMAIF2) |
73 RSTMGR_FIELD(PER0, DMAIF3) |
74 RSTMGR_FIELD(PER0, DMAIF4) |
75 RSTMGR_FIELD(PER0, DMAIF5) |
76 RSTMGR_FIELD(PER0, DMAIF6) |
77 RSTMGR_FIELD(PER0, DMAIF7));
78
79 #if (PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX) || (PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5)
80 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
81 RSTMGR_FIELD(BRG, MPFE));
82 #endif
83 }
84
config_hps_hs_before_warm_reset(void)85 void config_hps_hs_before_warm_reset(void)
86 {
87 uint32_t or_mask = 0;
88
89 or_mask |= RSTMGR_HDSKEN_EMIF_FLUSH;
90 or_mask |= RSTMGR_HDSKEN_FPGAHSEN;
91 or_mask |= RSTMGR_HDSKEN_ETRSTALLEN;
92 or_mask |= RSTMGR_HDSKEN_LWS2F_FLUSH;
93 or_mask |= RSTMGR_HDSKEN_L3NOC_DBG;
94 or_mask |= RSTMGR_HDSKEN_DEBUG_L3NOC;
95
96 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), or_mask);
97 }
98
poll_idle_status(uint32_t addr,uint32_t mask,uint32_t match,uint32_t delay_ms)99 static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_ms)
100 {
101 int time_out = delay_ms;
102
103 while (time_out-- > 0) {
104
105 if ((mmio_read_32(addr) & mask) == match) {
106 return 0;
107 }
108 udelay(1000);
109 }
110
111 return -ETIMEDOUT;
112 }
113
114 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
poll_idle_status_by_clkcycles(uint32_t addr,uint32_t mask,uint32_t match,uint32_t delay_clk_cycles)115 static int poll_idle_status_by_clkcycles(uint32_t addr, uint32_t mask,
116 uint32_t match, uint32_t delay_clk_cycles)
117 {
118 int time_out = delay_clk_cycles;
119
120 while (time_out-- > 0) {
121
122 if ((mmio_read_32(addr) & mask) == match) {
123 return 0;
124 }
125 udelay(1);
126 }
127 return -ETIMEDOUT;
128 }
129 #endif
130
socfpga_s2f_bridge_mask(uint32_t mask,uint32_t * brg_mask,uint32_t * noc_mask)131 static void socfpga_s2f_bridge_mask(uint32_t mask,
132 uint32_t *brg_mask,
133 uint32_t *noc_mask)
134 {
135 *brg_mask = 0;
136 *noc_mask = 0;
137
138 if ((mask & SOC2FPGA_MASK) != 0U) {
139 *brg_mask |= RSTMGR_FIELD(BRG, SOC2FPGA);
140 *noc_mask |= IDLE_DATA_SOC2FPGA;
141 }
142
143 if ((mask & LWHPS2FPGA_MASK) != 0U) {
144 *brg_mask |= RSTMGR_FIELD(BRG, LWHPS2FPGA);
145 *noc_mask |= IDLE_DATA_LWSOC2FPGA;
146 }
147 }
148
socfpga_f2s_bridge_mask(uint32_t mask,uint32_t * brg_mask,uint32_t * f2s_idlereq,uint32_t * f2s_force_drain,uint32_t * f2s_en,uint32_t * f2s_idleack,uint32_t * f2s_respempty,uint32_t * f2s_cmdidle)149 static void socfpga_f2s_bridge_mask(uint32_t mask,
150 uint32_t *brg_mask,
151 uint32_t *f2s_idlereq,
152 uint32_t *f2s_force_drain,
153 uint32_t *f2s_en,
154 uint32_t *f2s_idleack,
155 uint32_t *f2s_respempty,
156 uint32_t *f2s_cmdidle)
157 {
158 *brg_mask = 0;
159 *f2s_idlereq = 0;
160 *f2s_force_drain = 0;
161 *f2s_en = 0;
162 *f2s_idleack = 0;
163 *f2s_respempty = 0;
164 *f2s_cmdidle = 0;
165
166 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
167 if ((mask & FPGA2SOC_MASK) != 0U) {
168 *brg_mask |= RSTMGR_FIELD(BRG, FPGA2SOC);
169 }
170 if ((mask & F2SDRAM0_MASK) != 0U) {
171 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM0);
172 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ;
173 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN;
174 *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE;
175 *f2s_idleack |= FLAGINSTATUS_F2SDRAM0_IDLEACK;
176 *f2s_respempty |= FLAGINSTATUS_F2SDRAM0_RESPEMPTY;
177 *f2s_cmdidle |= FLAGINSTATUS_F2SDRAM0_CMDIDLE;
178 }
179 if ((mask & F2SDRAM1_MASK) != 0U) {
180 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM1);
181 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM1_IDLEREQ;
182 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM1_FORCE_DRAIN;
183 *f2s_en |= FLAGOUTSETCLR_F2SDRAM1_ENABLE;
184 *f2s_idleack |= FLAGINSTATUS_F2SDRAM1_IDLEACK;
185 *f2s_respempty |= FLAGINSTATUS_F2SDRAM1_RESPEMPTY;
186 *f2s_cmdidle |= FLAGINSTATUS_F2SDRAM1_CMDIDLE;
187 }
188 if ((mask & F2SDRAM2_MASK) != 0U) {
189 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM2);
190 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM2_IDLEREQ;
191 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM2_FORCE_DRAIN;
192 *f2s_en |= FLAGOUTSETCLR_F2SDRAM2_ENABLE;
193 *f2s_idleack |= FLAGINSTATUS_F2SDRAM2_IDLEACK;
194 *f2s_respempty |= FLAGINSTATUS_F2SDRAM2_RESPEMPTY;
195 *f2s_cmdidle |= FLAGINSTATUS_F2SDRAM2_CMDIDLE;
196 }
197 #elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
198 if (mask & FPGA2SOC_MASK) {
199 *brg_mask |= RSTMGR_FIELD(BRG, FPGA2SOC);
200 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ;
201 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN;
202 *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE;
203 *f2s_idleack |= FLAGINSTATUS_F2SDRAM0_IDLEACK;
204 *f2s_respempty |= FLAGINSTATUS_F2SDRAM0_RESPEMPTY;
205 }
206 if (mask & F2SDRAM0_MASK) {
207 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM0);
208 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ;
209 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN;
210 *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE;
211 *f2s_idleack |= FLAGINSTATUS_F2SDRAM0_IDLEACK;
212 *f2s_respempty |= FLAGINSTATUS_F2SDRAM0_RESPEMPTY;
213 }
214 if (mask & F2SDRAM1_MASK) {
215 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM1);
216 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM1_IDLEREQ;
217 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM1_FORCE_DRAIN;
218 *f2s_en |= FLAGOUTSETCLR_F2SDRAM1_ENABLE;
219 *f2s_idleack |= FLAGINSTATUS_F2SDRAM1_IDLEACK;
220 *f2s_respempty |= FLAGINSTATUS_F2SDRAM1_RESPEMPTY;
221 }
222 if (mask & F2SDRAM2_MASK) {
223 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM2);
224 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM2_IDLEREQ;
225 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM2_FORCE_DRAIN;
226 *f2s_en |= FLAGOUTSETCLR_F2SDRAM2_ENABLE;
227 *f2s_idleack |= FLAGINSTATUS_F2SDRAM2_IDLEACK;
228 *f2s_respempty |= FLAGINSTATUS_F2SDRAM2_RESPEMPTY;
229 }
230 #else
231 if ((mask & FPGA2SOC_MASK) != 0U) {
232 *brg_mask |= RSTMGR_FIELD(BRG, FPGA2SOC);
233 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ;
234 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN;
235 *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE;
236 *f2s_idleack |= FLAGINSTATUS_F2SDRAM0_IDLEACK;
237 *f2s_respempty |= FLAGINSTATUS_F2SDRAM0_RESPEMPTY;
238 *f2s_cmdidle |= FLAGINSTATUS_F2SDRAM0_CMDIDLE;
239 }
240 #endif
241 }
242
socfpga_bridges_reset(uint32_t mask)243 int socfpga_bridges_reset(uint32_t mask)
244 {
245 int ret = 0;
246 int timeout = 300;
247 uint32_t brg_mask = 0;
248 uint32_t noc_mask = 0;
249 uint32_t f2s_idlereq = 0;
250 uint32_t f2s_force_drain = 0;
251 uint32_t f2s_en = 0;
252 uint32_t f2s_idleack = 0;
253 uint32_t f2s_respempty = 0;
254 uint32_t f2s_cmdidle = 0;
255
256 /* Reset s2f bridge */
257 socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask);
258 if (brg_mask) {
259 if (mask & SOC2FPGA_MASK) {
260 /* Request handshake with SOC2FPGA bridge to clear traffic */
261 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
262 RSTMGR_HDSKREQ_S2F_FLUSH);
263
264 /* Wait for bridge to idle status */
265 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
266 RSTMGR_HDSKACK_S2F_FLUSH,
267 RSTMGR_HDSKACK_S2F_FLUSH, 300);
268 }
269
270 if (mask & LWHPS2FPGA_MASK) {
271 /* Request handshake with LWSOC2FPGA bridge to clear traffic */
272 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
273 RSTMGR_HDSKREQ_LWS2F_FLUSH);
274
275 /* Wait for bridge to idle status */
276 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
277 RSTMGR_HDSKACK_LWS2F_FLUSH,
278 RSTMGR_HDSKACK_LWS2F_FLUSH, 300);
279 }
280
281 if (ret < 0) {
282 ERROR("S2F Bridge reset: Timeout waiting for idle ack\n");
283 assert(false);
284 }
285
286 /* Assert reset to bridge */
287 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
288 brg_mask);
289
290 /* Clear idle requests to bridge */
291 if (mask & SOC2FPGA_MASK) {
292 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
293 RSTMGR_HDSKREQ_S2F_FLUSH);
294 }
295
296 if (mask & LWHPS2FPGA_MASK) {
297 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
298 RSTMGR_HDSKREQ_LWS2F_FLUSH);
299 }
300
301 /* When FPGA reconfig is complete */
302 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask);
303 }
304
305 /* Reset f2s bridge */
306 socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
307 &f2s_force_drain, &f2s_en,
308 &f2s_idleack, &f2s_respempty,
309 &f2s_cmdidle);
310
311 if (brg_mask) {
312 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN),
313 RSTMGR_HDSKEN_FPGAHSEN);
314
315 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
316 RSTMGR_HDSKREQ_FPGAHSREQ);
317
318 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
319 RSTMGR_HDSKACK_FPGAHSREQ,
320 RSTMGR_HDSKACK_FPGAHSREQ, 300);
321
322 if (ret < 0) {
323 ERROR("F2S Bridge disable: Timeout waiting for idle req\n");
324 assert(false);
325 }
326
327 /* Disable f2s bridge */
328 mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
329 f2s_en);
330 udelay(5);
331
332 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
333 f2s_force_drain);
334 udelay(5);
335
336 do {
337 /* Read response queue status to ensure it is empty */
338 uint32_t idle_status;
339
340 idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(
341 SIDEBANDMGR_FLAGINSTATUS0));
342 if (idle_status & f2s_respempty) {
343 idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(
344 SIDEBANDMGR_FLAGINSTATUS0));
345 if (idle_status & f2s_respempty) {
346 break;
347 }
348 }
349 udelay(1000);
350 } while (timeout-- > 0);
351
352 /* Assert reset to f2s bridge */
353 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
354 brg_mask);
355
356 /* Clear idle request to FPGA */
357 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
358 RSTMGR_HDSKREQ_FPGAHSREQ);
359
360 /* Clear idle request to MPFE */
361 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
362 f2s_idlereq);
363
364 /* When FPGA reconfig is complete */
365 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask);
366
367 /* Enable f2s bridge */
368 mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
369 f2s_idlereq);
370
371 ret = poll_idle_status(SOCFPGA_F2SDRAMMGR(
372 SIDEBANDMGR_FLAGINSTATUS0), f2s_idleack, 0, 300);
373 if (ret < 0) {
374 ERROR("F2S bridge enable: Timeout waiting for idle ack");
375 assert(false);
376 }
377
378 mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
379 f2s_force_drain);
380 udelay(5);
381
382 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
383 f2s_en);
384 udelay(5);
385 }
386
387 return ret;
388 }
389
390 /* TODO: Function too long, shall refactor */
socfpga_bridges_enable(uint32_t mask)391 int socfpga_bridges_enable(uint32_t mask)
392 {
393 int ret = 0;
394 int ret_hps = 0;
395 uint32_t brg_mask = 0;
396 uint32_t noc_mask = 0;
397 uint32_t f2s_idlereq = 0;
398 uint32_t f2s_force_drain = 0;
399 uint32_t f2s_en = 0;
400 uint32_t f2s_idleack = 0;
401 uint32_t f2s_respempty = 0;
402 uint32_t f2s_cmdidle = 0;
403 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
404 uint32_t brg_lst = 0;
405 #endif
406
407 /* Enable s2f bridge */
408 socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask);
409 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
410 /**************** SOC2FPGA ****************/
411 brg_lst = mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST));
412 if ((brg_mask & RSTMGR_BRGMODRSTMASK_SOC2FPGA)
413 && ((brg_lst & RSTMGR_BRGMODRSTMASK_SOC2FPGA) != 0)) {
414 /*
415 * To request handshake
416 * Write Reset Manager hdskreq[soc2fpga_flush_req] = 1
417 */
418 VERBOSE("Set S2F hdskreq ...\n");
419 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
420 ((~(brg_lst) << 9) & (RSTMGR_HDSKREQ_LWSOC2FPGAREQ
421 | RSTMGR_HDSKREQ_SOC2FPGAREQ))
422 | (RSTMGR_HDSKREQ_SOC2FPGAREQ));
423
424 udelay(1000);
425
426 /*
427 * To poll idle status
428 * Read Reset Manager hdskack[soc2fpga] = 1
429 */
430 if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
431 & RSTMGR_BRGMODRST_SOC2FPGA) == 0x00) {
432 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
433 RSTMGR_HDSKREQ_SOC2FPGAREQ, RSTMGR_HDSKREQ_SOC2FPGAREQ,
434 300);
435 }
436
437 udelay(1000);
438
439 if (ret < 0) {
440 ERROR("S2F bridge enable: Timeout hdskack\n");
441 }
442
443 /*
444 * To assert reset
445 * Write Reset Manager hdskreq[soc2fpga_flush_req] = 0
446 */
447 VERBOSE("Assert S2F ...\n");
448 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
449 (~brg_lst & 0x3) | RSTMGR_BRGMODRST_SOC2FPGA);
450
451 udelay(1000);
452
453 /*
454 * To clear idle request
455 * Write Reset Manager hdskreq[soc2fpga_flush_req] = 0
456 */
457 VERBOSE("Clear S2F hdskreq ...\n");
458 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
459 ((~(brg_lst) << 9) & (RSTMGR_HDSKREQ_LWSOC2FPGAREQ
460 | RSTMGR_HDSKREQ_SOC2FPGAREQ))
461 | (RSTMGR_HDSKREQ_SOC2FPGAREQ));
462
463 udelay(1000);
464
465 /*
466 * To clear ack status
467 * Write Reset Manager hdskack[soc2fpga_flush_ack] = 1
468 * This bit is W1S/W1C
469 */
470 VERBOSE("Clear S2F hdskack ...\n");
471 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
472 ((~(brg_lst) << 9) & (RSTMGR_HDSKREQ_LWSOC2FPGAREQ
473 | RSTMGR_HDSKREQ_SOC2FPGAREQ))
474 | (RSTMGR_HDSKACK_SOC2FPGAACK));
475
476 udelay(1000);
477
478 /*
479 * To deassert reset
480 * Write Reset Manager brgmodrst[soc2fpga] = 0
481 */
482 VERBOSE("Deassert S2F ...\n");
483 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
484 (~brg_lst & (RSTMGR_BRGMODRST_SOC2FPGA
485 | RSTMGR_BRGMODRST_LWHPS2FPGA))
486 | RSTMGR_BRGMODRST_SOC2FPGA);
487
488 /* Set System Manager soc bridge control register[soc2fpga_ready_latency_enable] = 1 */
489 VERBOSE("Set SOC soc2fpga_ready_latency_enable ...\n");
490 mmio_setbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL),
491 SYSMGR_SOC_BRIDGE_CTRL_EN);
492 }
493
494 /**************** LWSOCFPGA ****************/
495
496 /* Enable LWSOC2FPGA bridge */
497 brg_lst = mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST));
498 if ((brg_mask & RSTMGR_BRGMODRSTMASK_LWHPS2FPGA)
499 && ((brg_lst & RSTMGR_BRGMODRSTMASK_LWHPS2FPGA) != 0)) {
500 /*
501 * To request handshake
502 * Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 1
503 */
504 VERBOSE("Set LWS2F hdskreq ...\n");
505 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
506 ((~(brg_lst) << 9) & (RSTMGR_HDSKREQ_LWSOC2FPGAREQ
507 | RSTMGR_HDSKREQ_SOC2FPGAREQ))
508 | (RSTMGR_HDSKREQ_LWSOC2FPGAREQ));
509
510 udelay(1000);
511
512 /*
513 * To poll idle status
514 * Read Reset Manager hdskack[lwsoc2fpga] = 1
515 */
516 if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
517 & RSTMGR_BRGMODRST_LWHPS2FPGA) == 0x00) {
518 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
519 RSTMGR_HDSKREQ_LWSOC2FPGAREQ, RSTMGR_HDSKREQ_LWSOC2FPGAREQ,
520 300);
521 }
522
523 udelay(1000);
524
525 if (ret < 0) {
526 ERROR("LWS2F bridge enable: Timeout hdskack\n");
527 }
528
529 /*
530 * To assert reset
531 * Write Reset Manager brgmodrst[lwsoc2fpga] = 1
532 */
533 VERBOSE("Assert LWS2F ...\n");
534 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
535 (~brg_lst & (RSTMGR_BRGMODRST_SOC2FPGA
536 | RSTMGR_BRGMODRST_LWHPS2FPGA))
537 | RSTMGR_BRGMODRST_LWHPS2FPGA);
538
539 udelay(1000);
540
541 /*
542 * To clear idle request
543 * Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 0
544 */
545 VERBOSE("Clear LWS2F hdskreq ...\n");
546 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
547 ((~(brg_lst) << 9) & (RSTMGR_HDSKREQ_LWSOC2FPGAREQ
548 | RSTMGR_HDSKREQ_SOC2FPGAREQ))
549 | (RSTMGR_HDSKREQ_LWSOC2FPGAREQ));
550
551 udelay(1000);
552
553 /*
554 * To clear ack status
555 * Write Reset Manager hdskack[lwsoc2fpga_flush_ack] = 1
556 * This bit is W1S/W1C
557 */
558 VERBOSE("Clear LWS2F hdskack ...\n");
559 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
560 ((~(brg_lst) << 9) & (RSTMGR_HDSKREQ_LWSOC2FPGAREQ
561 | RSTMGR_HDSKREQ_SOC2FPGAREQ))
562 | (RSTMGR_HDSKACK_SOC2FPGAACK));
563
564 udelay(1000);
565
566 /*
567 * To deassert reset
568 * Write Reset Manager brgmodrst[lwsoc2fpga] = 0
569 */
570 VERBOSE("Deassert LWS2F ...\n");
571 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
572 ((~brg_lst & (RSTMGR_BRGMODRST_SOC2FPGA
573 | RSTMGR_BRGMODRST_LWHPS2FPGA)))
574 | RSTMGR_BRGMODRST_LWHPS2FPGA);
575
576 /* Set System Manager lwsoc bridge control register[lwsoc2fpga_ready_latency_enable] = 1 */
577 VERBOSE("Set LWSOC lwsoc2fpga_ready_latency_enable ...\n");
578 mmio_setbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL),
579 SYSMGR_LWSOC_BRIDGE_CTRL_EN);
580 }
581 #else
582 if (brg_mask != 0U) {
583 /* Clear idle request */
584 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR),
585 noc_mask);
586
587 /* De-assert all bridges */
588 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask);
589
590 /* Wait until idle ack becomes 0 */
591 ret_hps = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
592 noc_mask, 0, 1000);
593 }
594 #endif
595
596 /* Enable f2s bridge */
597 socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
598 &f2s_force_drain, &f2s_en,
599 &f2s_idleack, &f2s_respempty, &f2s_cmdidle);
600 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
601 /* Enable FPGA2SOC bridge */
602
603 if ((brg_mask & RSTMGR_BRGMODRSTMASK_FPGA2SOC)
604 && ((brg_lst & RSTMGR_BRGMODRSTMASK_FPGA2SOC) != 0)) {
605 /*
606 * To request handshake
607 * Write Reset Manager hdsken[fpgahsen] = 1
608 */
609 VERBOSE("Set FPGA hdsken(fpgahsen) ...\n");
610 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
611
612 /*
613 * To request handshake
614 * Write Reset Manager hdskreq[fpgahsreq] = 1
615 */
616 VERBOSE("Set FPGA hdskreq(fpgahsreq) ...\n");
617 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
618
619 /*
620 * To poll idle status
621 * Read Reset Manager hdskack[fpgahsack] = 1
622 */
623 VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
624 if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
625 & RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
626 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
627 RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK,
628 300);
629 }
630
631 if (ret < 0) {
632 ERROR("FPGA bridge fpga handshake fpgahsreq: Timeout\n");
633 }
634
635 /*
636 * To fence and drain traffic
637 * Write Reset Manager hdskreq[f2s_flush_req] = 1
638 */
639 VERBOSE("Set F2S hdskreq(f2s_flush_req) ...\n");
640 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
641 RSTMGR_HDSKREQ_FPGA2SOCREQ);
642
643 /*
644 * To poll idle status
645 * Read Reset Manager hdskack[f2s_flush_ack] = 1
646 */
647 VERBOSE("Get F2S hdskack(f2s_flush_ack) ...\n");
648 if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
649 & RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
650 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
651 RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK,
652 300);
653 }
654
655 if (ret < 0) {
656 ERROR("F2S bridge fpga handshake f2sdram_flush_req: Timeout\n");
657 }
658
659 /*
660 * To clear idle request
661 * Write Reset Manager hdskreq[fpgahsreq] = 1
662 */
663 VERBOSE("Clear FPGA hdskreq(fpgahsreq) ...\n");
664 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
665
666 /*
667 * To clear idle request
668 * Write Reset Manager hdskreq[f2s_flush_req] = 1
669 */
670 VERBOSE("Clear F2S hdskreq(f2s_flush_req) ...\n");
671 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
672 RSTMGR_HDSKREQ_FPGA2SOCREQ);
673
674 /*
675 * To poll idle status
676 * Read Reset Manager hdskack[f2s_flush_ack] = 0
677 */
678 VERBOSE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
679 if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
680 & RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
681 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
682 RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
683 300);
684 }
685
686 if (ret < 0) {
687 ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
688 }
689
690 /*
691 * To poll idle status
692 * Read Reset Manager hdskack[fpgahsack] = 0
693 */
694 VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
695 if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
696 & RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
697 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
698 RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
699 300);
700 }
701
702 if (ret < 0) {
703 ERROR("F2S bridge fpga handshake fpgahsack: Timeout\n");
704 }
705
706 /*
707 * To assert reset
708 * Write Reset Manager brgmodrst[fpga2soc] = 1
709 */
710 VERBOSE("Assert F2S ...\n");
711 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
712
713 udelay(1000);
714
715 /*
716 * To deassert reset
717 * Write Reset Manager brgmodrst[fpga2soc] = 0
718 */
719 VERBOSE("Deassert F2S ...\n");
720 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
721
722 /* Write System Manager f2s bridge control register[f2soc_enable] = 1 */
723 VERBOSE("Deassert F2S f2soc_enable ...\n");
724 mmio_setbits_32(SOCFPGA_SYSMGR(F2S_BRIDGE_CTRL),
725 SYSMGR_F2S_BRIDGE_CTRL_EN);
726 }
727
728 /* Enable FPGA2SDRAM bridge */
729 if ((brg_mask & RSTMGR_BRGMODRSTMASK_F2SDRAM0)
730 && ((brg_lst & RSTMGR_BRGMODRSTMASK_F2SDRAM0) != 0)) {
731 /*
732 * To request handshake
733 * Write Reset Manager hdsken[fpgahsen] = 1
734 */
735 VERBOSE("Set F2SDRAM hdsken(fpgahsen) ...\n");
736 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
737
738 /*
739 * To request handshake
740 * Write Reset Manager hdskreq[fpgahsreq] = 1
741 */
742 VERBOSE("Set F2SDRAM hdskreq(fpgahsreq) ...\n");
743 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
744
745 /*
746 * To poll idle status
747 * Read Reset Manager hdskack[fpgahsack] = 1
748 */
749 VERBOSE("Get F2SDRAM hdskack(fpgahsack) ...\n");
750 if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
751 & RSTMGR_BRGMODRSTMASK_F2SDRAM0) == 0x00) {
752 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
753 RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK,
754 300);
755 }
756
757 if (ret < 0) {
758 ERROR("F2SDRAM bridge fpga handshake fpgahsreq: Timeout\n");
759 }
760
761 /*
762 * To fence and drain traffic
763 * Write Reset Manager hdskreq[f2sdram_flush_req] = 1
764 */
765 VERBOSE("Set F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
766 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
767 RSTMGR_HDSKREQ_F2SDRAM0REQ);
768
769 /*
770 * To poll idle status
771 * Read Reset Manager hdskack[f2sdram_flush_ack] = 1
772 */
773 VERBOSE("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
774 if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
775 & RSTMGR_BRGMODRSTMASK_F2SDRAM0) == 0x00) {
776 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
777 RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK,
778 300);
779 }
780
781 if (ret < 0) {
782 ERROR("F2SDRAM bridge fpga handshake f2sdram_flush_req: Timeout\n");
783 }
784
785 /*
786 * To clear idle request
787 * Write Reset Manager hdskreq[fpgahsreq] = 1
788 */
789 VERBOSE("Clear F2SDRAM hdskreq(fpgahsreq) ...\n");
790 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
791
792 /*
793 * To clear idle request
794 * Write Reset Manager hdskreq[f2sdram_flush_req] = 1
795 */
796 VERBOSE("Clear F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
797 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_F2SDRAM0REQ);
798
799 /*
800 * To poll idle status
801 * Read Reset Manager hdskack[f2sdram_flush_ack] = 0
802 */
803 VERBOSE("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
804 if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
805 & RSTMGR_BRGMODRSTMASK_F2SDRAM0) == 0x00) {
806 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
807 RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK_DASRT,
808 300);
809 }
810
811 if (ret < 0) {
812 ERROR("F2SDRAM bridge fpga handshake f2sdram_flush_ack: Timeout\n");
813 }
814
815 /*
816 * To poll idle status
817 * Read Reset Manager hdskack[fpgahsack] = 0
818 */
819 VERBOSE("Get F2SDRAM hdskack(fpgahsack) ...\n");
820 if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
821 & RSTMGR_BRGMODRSTMASK_F2SDRAM0) == 0x00) {
822 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
823 RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
824 300);
825 }
826
827 if (ret < 0) {
828 ERROR("F2SDRAM bridge fpga handshake fpgahsack: Timeout\n");
829 }
830
831 /*
832 * To assert reset
833 * Write Reset Manager brgmodrst[fpga2sdram] = 1
834 */
835 VERBOSE("Assert F2SDRAM ...\n");
836 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
837 RSTMGR_BRGMODRST_F2SSDRAM0);
838
839 udelay(1000);
840
841 /*
842 * To deassert reset
843 * Write Reset Manager brgmodrst[fpga2sdram] = 0
844 */
845 VERBOSE("Deassert F2SDRAM ...\n");
846 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
847 RSTMGR_BRGMODRST_F2SSDRAM0);
848 }
849 #else
850 if (brg_mask != 0U) {
851 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask);
852
853 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
854 f2s_idlereq);
855
856 ret = poll_idle_status(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGINSTATUS0),
857 f2s_idleack, 0, 300);
858
859 if (ret < 0) {
860 ERROR("F2S bridge enable: Timeout idle ack");
861 }
862
863 /* Clear the force drain */
864 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
865 f2s_force_drain);
866 udelay(5);
867
868 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
869 f2s_en);
870 udelay(5);
871 }
872 #endif
873 ret = ret | ret_hps;
874 return ret;
875 }
876
socfpga_bridge_nongraceful_disable(uint32_t mask)877 int socfpga_bridge_nongraceful_disable(uint32_t mask)
878 {
879 int ret = 0;
880 int timeout = 1000;
881 uint32_t brg_mask = 0;
882 uint32_t f2s_idlereq = 0;
883 uint32_t f2s_force_drain = 0;
884 uint32_t f2s_en = 0;
885 uint32_t f2s_idleack = 0;
886 uint32_t f2s_respempty = 0;
887 uint32_t f2s_cmdidle = 0;
888
889 socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
890 &f2s_force_drain, &f2s_en,
891 &f2s_idleack, &f2s_respempty, &f2s_cmdidle);
892
893 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
894 f2s_idlereq);
895
896 /* Time out Error - Bus is still active */
897 /* Performing a non-graceful shutdown with Force drain */
898 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
899 f2s_force_drain);
900
901 ret = -ETIMEDOUT;
902 do {
903 /* Read response queue status to ensure it is empty */
904 uint32_t idle_status;
905
906 idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGINSTATUS0));
907 if ((idle_status & f2s_respempty) != 0U) {
908 idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGINSTATUS0));
909 if ((idle_status & f2s_respempty) != 0U) {
910 /* No time-out we are good! */
911 ret = 0;
912 break;
913 }
914 }
915
916 asm("nop");
917
918 } while (timeout-- > 0);
919
920 return ret;
921 }
922
socfpga_bridges_disable(uint32_t mask)923 int socfpga_bridges_disable(uint32_t mask)
924 {
925 int ret = 0;
926 uint32_t brg_mask = 0;
927 uint32_t noc_mask = 0;
928 uint32_t f2s_idlereq = 0;
929 uint32_t f2s_force_drain = 0;
930 uint32_t f2s_en = 0;
931 uint32_t f2s_idleack = 0;
932 uint32_t f2s_respempty = 0;
933 uint32_t f2s_cmdidle = 0;
934
935 /* Disable s2f bridge */
936 socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask);
937 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
938 /* Disable SOC2FPGA bridge */
939 if (brg_mask & RSTMGR_BRGMODRSTMASK_SOC2FPGA) {
940 /*
941 * To clear handshake
942 * Write Reset Manager hdskreq[soc2fpga_flush_req] = 0
943 */
944 VERBOSE("Set S2F hdskreq ...\n");
945 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
946 RSTMGR_HDSKREQ_SOC2FPGAREQ);
947
948 /*
949 * To poll idle status
950 * Read Reset Manager hdskack[soc2fpga] = 0
951 */
952 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
953 RSTMGR_HDSKACK_SOC2FPGAACK, RSTMGR_HDSKACK_SOC2FPGAACK_DASRT,
954 300);
955
956 if (ret < 0) {
957 ERROR("S2F bridge enable: Timeout hdskack\n");
958 }
959
960 /*
961 * To assert reset
962 * Write Reset Manager brgmodrst[soc2fpga] = 1
963 */
964 VERBOSE("Assert S2F ...\n");
965 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
966 RSTMGR_BRGMODRST_SOC2FPGA);
967
968 /* Clear System Manager soc bridge control register[soc2fpga_ready_latency_enable] = 1 */
969 VERBOSE("Clear SOC soc2fpga_ready_latency_enable ...\n");
970 mmio_clrbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL),
971 SYSMGR_SOC_BRIDGE_CTRL_EN);
972
973 udelay(1000);
974 }
975
976 /* Disable LWSOC2FPGA bridge */
977 if (brg_mask & RSTMGR_BRGMODRSTMASK_LWHPS2FPGA) {
978 /*
979 * To clear handshake
980 * Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 0
981 */
982 VERBOSE("Set LWS2F hdskreq ...\n");
983 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
984 RSTMGR_HDSKREQ_LWSOC2FPGAREQ);
985
986 /*
987 * To poll idle status
988 * Read Reset Manager hdskack[lwsoc2fpga] = 0
989 */
990 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
991 RSTMGR_HDSKACK_LWSOC2FPGAACK, RSTMGR_HDSKACK_LWSOC2FPGAACK_DASRT,
992 300);
993
994 if (ret < 0) {
995 ERROR("LWS2F bridge enable: Timeout hdskack\n");
996 }
997
998 /*
999 * To assert reset
1000 * Write Reset Manager brgmodrst[lwsoc2fpga] = 1
1001 */
1002 VERBOSE("Assert LWS2F ...\n");
1003 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
1004 RSTMGR_BRGMODRST_LWHPS2FPGA);
1005
1006 /* Clear System Manager lwsoc bridge control register[lwsoc2fpga_ready_latency_enable] = 1 */
1007 VERBOSE("Clear LWSOC lwsoc2fpga_ready_latency_enable ...\n");
1008 mmio_clrbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL),
1009 SYSMGR_LWSOC_BRIDGE_CTRL_EN);
1010
1011 udelay(1000);
1012 }
1013 #else
1014 if (brg_mask != 0U) {
1015 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_SET),
1016 noc_mask);
1017
1018 mmio_write_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1);
1019
1020 ret = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
1021 noc_mask, noc_mask, 300);
1022 if (ret < 0) {
1023 ERROR("S2F Bridge disable: Timeout idle ack\n");
1024 }
1025
1026 ret = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLESTATUS),
1027 noc_mask, noc_mask, 300);
1028 if (ret < 0) {
1029 ERROR("S2F Bridge disable: Timeout idle status\n");
1030 }
1031
1032 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask);
1033
1034 mmio_write_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 0);
1035 }
1036 #endif
1037
1038 /* Disable f2s bridge */
1039 socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
1040 &f2s_force_drain, &f2s_en,
1041 &f2s_idleack, &f2s_respempty, &f2s_cmdidle);
1042 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
1043 /* Disable FPGA2SOC bridge */
1044 if (brg_mask & RSTMGR_BRGMODRSTMASK_FPGA2SOC) {
1045 /*
1046 * To request handshake
1047 * Write Reset Manager hdsken[fpgahsen] = 1
1048 */
1049 VERBOSE("Set FPGA hdsken(fpgahsen) ...\n");
1050 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
1051
1052 /*
1053 * To clear handshake request
1054 * Write Reset Manager hdskreq[fpgahsreq] = 0
1055 */
1056 VERBOSE("Clear FPGA hdskreq(fpgahsreq) ...\n");
1057 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
1058
1059 /*
1060 * To clear handshake request
1061 * Write Reset Manager hdskreq[f2s_flush_req] = 0
1062 */
1063 VERBOSE("Clear F2S hdskreq(f2s_flush_req) ...\n");
1064 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
1065 RSTMGR_HDSKREQ_FPGA2SOCREQ);
1066
1067 /*
1068 * To poll idle status
1069 * Read Reset Manager hdskack[f2s_flush_ack] = 0
1070 */
1071 VERBOSE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
1072 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
1073 RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
1074 300);
1075
1076 if (ret < 0) {
1077 ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
1078 }
1079
1080 /*
1081 * To poll idle status
1082 * Read Reset Manager hdskack[fpgahsack] = 0
1083 */
1084 VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
1085 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
1086 RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
1087 300);
1088
1089 if (ret < 0) {
1090 ERROR("F2S bridge fpga handshake fpgahsack: Timeout\n");
1091 }
1092
1093 /*
1094 * To assert reset
1095 * Write Reset Manager brgmodrst[fpga2soc] = 1
1096 */
1097 VERBOSE("Assert F2S ...\n");
1098 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
1099
1100 udelay(1000);
1101
1102 /* Write System Manager f2s bridge control register[f2soc_enable] = 0 */
1103 VERBOSE("Assert F2S f2soc_enable ...\n");
1104 mmio_clrbits_32(SOCFPGA_SYSMGR(F2S_BRIDGE_CTRL),
1105 SYSMGR_F2S_BRIDGE_CTRL_EN);
1106 }
1107
1108 /* Disable FPGA2SDRAM bridge */
1109 if (brg_mask & RSTMGR_BRGMODRSTMASK_F2SDRAM0) {
1110 /*
1111 * To request handshake
1112 * Write Reset Manager hdsken[fpgahsen] = 1
1113 */
1114 VERBOSE("Set F2SDRAM hdsken(fpgahsen) ...\n");
1115 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
1116
1117 /*
1118 * To clear handshake request
1119 * Write Reset Manager hdskreq[fpgahsreq] = 0
1120 */
1121 VERBOSE("Clear F2SDRAM hdskreq(fpgahsreq) ...\n");
1122 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
1123
1124 /*
1125 * To clear handshake request
1126 * Write Reset Manager hdskreq[f2sdram_flush_req] = 0
1127 */
1128 VERBOSE("Clear F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
1129 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_F2SDRAM0REQ);
1130
1131 /*
1132 * To poll idle status
1133 * Read Reset Manager hdskack[f2sdram_flush_ack] = 0
1134 */
1135 VERBOSE("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
1136 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
1137 RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK_DASRT,
1138 300);
1139
1140 if (ret < 0) {
1141 ERROR("F2SDRAM bridge fpga handshake f2sdram_flush_ack: Timeout\n");
1142 }
1143
1144 /*
1145 * To poll idle status
1146 * Read Reset Manager hdskack[fpgahsack] = 0
1147 */
1148 VERBOSE("Get F2SDRAM hdskack(fpgahsack) ...\n");
1149 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
1150 RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
1151 300);
1152
1153 if (ret < 0) {
1154 ERROR("F2SDRAM bridge fpga handshake fpgahsack: Timeout\n");
1155 }
1156
1157 /*
1158 * To assert reset
1159 * Write Reset Manager brgmodrst[fpga2sdram] = 1
1160 */
1161 VERBOSE("Assert F2SDRAM ...\n");
1162 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
1163 RSTMGR_BRGMODRST_F2SSDRAM0);
1164
1165 udelay(1000);
1166
1167 /*
1168 * Assert fpga2sdram_manager_main_SidebandManager_FlagOutClr0
1169 * f2s_ready_latency_enable
1170 */
1171 VERBOSE("Assert F2SDRAM f2s_ready_latency_enable ...\n");
1172 mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
1173 FLAGOUTCLR0_F2SDRAM0_ENABLE);
1174 }
1175 #else
1176 if (brg_mask != 0U) {
1177
1178 if (mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST)) & brg_mask) {
1179 /* Bridge cannot be reset twice */
1180 return 0;
1181 }
1182
1183 /* Starts the fence and drain traffic from F2SDRAM to MPFE */
1184 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN),
1185 RSTMGR_HDSKEN_FPGAHSEN);
1186 udelay(5);
1187 /* Ignoring FPGA ACK as it will time-out */
1188 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
1189 RSTMGR_HDSKREQ_FPGAHSREQ);
1190
1191 ret = poll_idle_status_by_clkcycles(SOCFPGA_RSTMGR(HDSKACK),
1192 RSTMGR_HDSKACK_FPGAHSREQ,
1193 RSTMGR_HDSKACK_FPGAHSREQ, 1000);
1194
1195 /* DISABLE F2S Bridge */
1196 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
1197 f2s_en);
1198 udelay(5);
1199
1200 ret = socfpga_bridge_nongraceful_disable(mask);
1201
1202 /* Bridge reset */
1203 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
1204 /* Software must never write a 0x1 to FPGA2SOC_MASK bit */
1205 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
1206 brg_mask & ~RSTMGR_FIELD(BRG, FPGA2SOC));
1207 #else
1208 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
1209 brg_mask);
1210 #endif
1211 /* Re-enable traffic to SDRAM*/
1212 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
1213 RSTMGR_HDSKREQ_FPGAHSREQ);
1214
1215 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
1216 f2s_idlereq);
1217 }
1218 #endif
1219
1220 return ret;
1221 }
1222
1223 /* CPUxRESETBASELOW */
socfpga_cpu_reset_base(unsigned int cpu_id)1224 int socfpga_cpu_reset_base(unsigned int cpu_id)
1225 {
1226 int ret = 0;
1227 uint32_t entrypoint = 0;
1228
1229 ret = socfpga_cpurstrelease(cpu_id);
1230
1231 if (ret < 0) {
1232 return RSTMGR_RET_ERROR;
1233 }
1234
1235 if (ret == RSTMGR_RET_OK) {
1236
1237 switch (cpu_id) {
1238 case 0:
1239 entrypoint = mmio_read_32(SOCFPGA_RSTMGR_CPUBASELOW_0);
1240 entrypoint |= mmio_read_32(SOCFPGA_RSTMGR_CPUBASEHIGH_0) << 24;
1241 break;
1242
1243 case 1:
1244 entrypoint = mmio_read_32(SOCFPGA_RSTMGR_CPUBASELOW_1);
1245 entrypoint |= mmio_read_32(SOCFPGA_RSTMGR_CPUBASEHIGH_1) << 24;
1246 break;
1247
1248 case 2:
1249 entrypoint = mmio_read_32(SOCFPGA_RSTMGR_CPUBASELOW_2);
1250 entrypoint |= mmio_read_32(SOCFPGA_RSTMGR_CPUBASEHIGH_2) << 24;
1251 break;
1252
1253 case 3:
1254 entrypoint = mmio_read_32(SOCFPGA_RSTMGR_CPUBASELOW_3);
1255 entrypoint |= mmio_read_32(SOCFPGA_RSTMGR_CPUBASEHIGH_3) << 24;
1256 break;
1257
1258 default:
1259 break;
1260 }
1261
1262 mmio_write_64(PLAT_SEC_ENTRY, entrypoint);
1263 }
1264
1265 return RSTMGR_RET_OK;
1266 }
1267
1268 /* CPURSTRELEASE */
socfpga_cpurstrelease(unsigned int cpu_id)1269 int socfpga_cpurstrelease(unsigned int cpu_id)
1270 {
1271 unsigned int timeout = 0;
1272
1273 do {
1274 /* Read response queue status to ensure it is empty */
1275 uint32_t cpurstrelease_status;
1276
1277 cpurstrelease_status = mmio_read_32(SOCFPGA_RSTMGR(CPURSTRELEASE));
1278
1279 if ((cpurstrelease_status & RSTMGR_CPUSTRELEASE_CPUx) == cpu_id) {
1280 return RSTMGR_RET_OK;
1281 }
1282 udelay(1000);
1283 } while (timeout-- > 0);
1284
1285 return RSTMGR_RET_ERROR;
1286 }