1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef MTK_COMMON_SPI_H 4 #define MTK_COMMON_SPI_H 5 6 #include <device/mmio.h> 7 #include <soc/gpio_base.h> 8 #include <spi-generic.h> 9 #include <types.h> 10 11 enum { 12 SPI_CMD_ACT_SHIFT = 0, 13 SPI_CMD_RESUME_SHIFT = 1, 14 SPI_CMD_RST_SHIFT = 2, 15 SPI_CMD_PAUSE_EN_SHIFT = 4, 16 SPI_CMD_DEASSERT_SHIFT = 5, 17 SPI_CMD_CPHA_SHIFT = 8, 18 SPI_CMD_CPOL_SHIFT = 9, 19 SPI_CMD_RX_DMA_SHIFT = 10, 20 SPI_CMD_TX_DMA_SHIFT = 11, 21 SPI_CMD_TXMSBF_SHIFT = 12, 22 SPI_CMD_RXMSBF_SHIFT = 13, 23 SPI_CMD_RX_ENDIAN_SHIFT = 14, 24 SPI_CMD_TX_ENDIAN_SHIFT = 15, 25 SPI_CMD_FINISH_IE_SHIFT = 16, 26 SPI_CMD_PAUSE_IE_SHIFT = 17, 27 28 SPI_CMD_ACT_EN = BIT(SPI_CMD_ACT_SHIFT), 29 SPI_CMD_RESUME_EN = BIT(SPI_CMD_RESUME_SHIFT), 30 SPI_CMD_RST_EN = BIT(SPI_CMD_RST_SHIFT), 31 SPI_CMD_PAUSE_EN = BIT(SPI_CMD_PAUSE_EN_SHIFT), 32 SPI_CMD_DEASSERT_EN = BIT(SPI_CMD_DEASSERT_SHIFT), 33 SPI_CMD_CPHA_EN = BIT(SPI_CMD_CPHA_SHIFT), 34 SPI_CMD_CPOL_EN = BIT(SPI_CMD_CPOL_SHIFT), 35 SPI_CMD_RX_DMA_EN = BIT(SPI_CMD_RX_DMA_SHIFT), 36 SPI_CMD_TX_DMA_EN = BIT(SPI_CMD_TX_DMA_SHIFT), 37 SPI_CMD_TXMSBF_EN = BIT(SPI_CMD_TXMSBF_SHIFT), 38 SPI_CMD_RXMSBF_EN = BIT(SPI_CMD_RXMSBF_SHIFT), 39 SPI_CMD_RX_ENDIAN_EN = BIT(SPI_CMD_RX_ENDIAN_SHIFT), 40 SPI_CMD_TX_ENDIAN_EN = BIT(SPI_CMD_TX_ENDIAN_SHIFT), 41 SPI_CMD_FINISH_IE_EN = BIT(SPI_CMD_FINISH_IE_SHIFT), 42 SPI_CMD_PAUSE_IE_EN = BIT(SPI_CMD_PAUSE_IE_SHIFT), 43 }; 44 45 enum spi_pad_mask { 46 SPI_PAD0_MASK = 0x0, 47 SPI_PAD1_MASK = 0x1, 48 SPI_PAD2_MASK = 0x2, 49 SPI_PAD3_MASK = 0x3, 50 SPI_PAD_SEL_MASK = 0x3 51 }; 52 53 /* SPI peripheral register map. */ 54 typedef struct mtk_spi_regs { 55 uint32_t spi_cfg0_reg; 56 uint32_t spi_cfg1_reg; 57 uint32_t spi_tx_src_reg; 58 uint32_t spi_rx_dst_reg; 59 uint32_t spi_tx_data_reg; 60 uint32_t spi_rx_data_reg; 61 uint32_t spi_cmd_reg; 62 uint32_t spi_status0_reg; 63 uint32_t spi_status1_reg; 64 uint32_t spi_pad_macro_sel_reg; 65 uint32_t spi_cfg2_reg; 66 uint32_t spi_tx_src_64_reg; 67 uint32_t spi_rx_dst_64_reg; 68 } mtk_spi_regs; 69 70 check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); 71 72 struct mtk_spi_bus { 73 struct spi_slave slave; 74 struct mtk_spi_regs *regs; 75 int initialized; 76 int state; 77 gpio_t cs_gpio; 78 }; 79 80 extern const struct spi_ctrlr spi_ctrlr; 81 extern struct mtk_spi_bus spi_bus[]; 82 83 void mtk_spi_set_gpio_pinmux(unsigned int bus, 84 enum spi_pad_mask pad_select); 85 void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, 86 unsigned int tick_dly); 87 void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, 88 unsigned int speed_hz, unsigned int tick_dly); 89 90 #endif 91