1 /*
2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <drivers/clk.h>
13 #include <drivers/delay_timer.h>
14 #include <drivers/st/stm32_console.h>
15 #include <drivers/st/stm32mp_clkfunc.h>
16 #include <drivers/st/stm32mp_reset.h>
17 #include <lib/mmio.h>
18 #include <lib/smccc.h>
19 #include <lib/xlat_tables/xlat_tables_v2.h>
20 #include <plat/common/platform.h>
21 #include <services/arm_arch_svc.h>
22
23 #include <platform_def.h>
24
25 #define HEADER_VERSION_MAJOR_MASK GENMASK(23, 16)
26 #define RESET_TIMEOUT_US_1MS 1000U
27
28 /* Internal layout of the 32bit OTP word board_id */
29 #define BOARD_ID_BOARD_NB_MASK GENMASK_32(31, 16)
30 #define BOARD_ID_BOARD_NB_SHIFT 16
31 #define BOARD_ID_VARCPN_MASK GENMASK_32(15, 12)
32 #define BOARD_ID_VARCPN_SHIFT 12
33 #define BOARD_ID_REVISION_MASK GENMASK_32(11, 8)
34 #define BOARD_ID_REVISION_SHIFT 8
35 #define BOARD_ID_VARFG_MASK GENMASK_32(7, 4)
36 #define BOARD_ID_VARFG_SHIFT 4
37 #define BOARD_ID_BOM_MASK GENMASK_32(3, 0)
38
39 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \
40 BOARD_ID_BOARD_NB_SHIFT)
41 #define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \
42 BOARD_ID_VARCPN_SHIFT)
43 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \
44 BOARD_ID_REVISION_SHIFT)
45 #define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \
46 BOARD_ID_VARFG_SHIFT)
47 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK)
48
49 #define BOOT_AUTH_MASK GENMASK_32(23, 20)
50 #define BOOT_AUTH_SHIFT 20
51 #define BOOT_PART_MASK GENMASK_32(19, 16)
52 #define BOOT_PART_SHIFT 16
53 #define BOOT_ITF_MASK GENMASK_32(15, 12)
54 #define BOOT_ITF_SHIFT 12
55 #define BOOT_INST_MASK GENMASK_32(11, 8)
56 #define BOOT_INST_SHIFT 8
57
58 /* Layout for fwu update information. */
59 #define FWU_INFO_IDX_MSK GENMASK(3, 0)
60 #define FWU_INFO_IDX_OFF U(0)
61 #define FWU_INFO_CNT_MSK GENMASK(7, 4)
62 #define FWU_INFO_CNT_OFF U(4)
63
64 static console_t console;
65
plat_get_ns_image_entrypoint(void)66 uintptr_t plat_get_ns_image_entrypoint(void)
67 {
68 return BL33_BASE;
69 }
70
plat_get_syscnt_freq2(void)71 unsigned int plat_get_syscnt_freq2(void)
72 {
73 return read_cntfrq_el0();
74 }
75
76 static uintptr_t boot_ctx_address;
77 static uint16_t boot_itf_selected;
78
stm32mp_save_boot_ctx_address(uintptr_t address)79 void stm32mp_save_boot_ctx_address(uintptr_t address)
80 {
81 boot_api_context_t *boot_context = (boot_api_context_t *)address;
82
83 boot_ctx_address = address;
84 boot_itf_selected = boot_context->boot_interface_selected;
85 }
86
stm32mp_get_boot_ctx_address(void)87 uintptr_t stm32mp_get_boot_ctx_address(void)
88 {
89 return boot_ctx_address;
90 }
91
stm32mp_get_boot_itf_selected(void)92 uint16_t stm32mp_get_boot_itf_selected(void)
93 {
94 return boot_itf_selected;
95 }
96
stm32mp_ddrctrl_base(void)97 uintptr_t stm32mp_ddrctrl_base(void)
98 {
99 return DDRCTRL_BASE;
100 }
101
stm32mp_ddrphyc_base(void)102 uintptr_t stm32mp_ddrphyc_base(void)
103 {
104 return DDRPHYC_BASE;
105 }
106
stm32mp_pwr_base(void)107 uintptr_t stm32mp_pwr_base(void)
108 {
109 return PWR_BASE;
110 }
111
stm32mp_rcc_base(void)112 uintptr_t stm32mp_rcc_base(void)
113 {
114 return RCC_BASE;
115 }
116
stm32mp_lock_available(void)117 bool stm32mp_lock_available(void)
118 {
119 const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT;
120
121 /* The spinlocks are used only when MMU and data cache are enabled */
122 #ifdef __aarch64__
123 return (read_sctlr_el3() & c_m_bits) == c_m_bits;
124 #else
125 return (read_sctlr() & c_m_bits) == c_m_bits;
126 #endif
127 }
128
stm32mp_map_ddr_non_cacheable(void)129 int stm32mp_map_ddr_non_cacheable(void)
130 {
131 return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
132 STM32MP_DDR_MAX_SIZE,
133 MT_NON_CACHEABLE | MT_RW | MT_SECURE);
134 }
135
stm32mp_unmap_ddr(void)136 int stm32mp_unmap_ddr(void)
137 {
138 return mmap_remove_dynamic_region(STM32MP_DDR_BASE,
139 STM32MP_DDR_MAX_SIZE);
140 }
141
stm32_get_otp_index(const char * otp_name,uint32_t * otp_idx,uint32_t * otp_len)142 int stm32_get_otp_index(const char *otp_name, uint32_t *otp_idx,
143 uint32_t *otp_len)
144 {
145 assert(otp_name != NULL);
146 assert(otp_idx != NULL);
147
148 return dt_find_otp_name(otp_name, otp_idx, otp_len);
149 }
150
stm32_get_otp_value(const char * otp_name,uint32_t * otp_val)151 int stm32_get_otp_value(const char *otp_name, uint32_t *otp_val)
152 {
153 uint32_t otp_idx;
154
155 assert(otp_name != NULL);
156 assert(otp_val != NULL);
157
158 if (stm32_get_otp_index(otp_name, &otp_idx, NULL) != 0) {
159 return -1;
160 }
161
162 if (stm32_get_otp_value_from_idx(otp_idx, otp_val) != 0) {
163 ERROR("BSEC: %s Read Error\n", otp_name);
164 return -1;
165 }
166
167 return 0;
168 }
169
stm32_get_otp_value_from_idx(const uint32_t otp_idx,uint32_t * otp_val)170 int stm32_get_otp_value_from_idx(const uint32_t otp_idx, uint32_t *otp_val)
171 {
172 uint32_t ret = BSEC_NOT_SUPPORTED;
173
174 assert(otp_val != NULL);
175
176 #if defined(IMAGE_BL2)
177 ret = stm32_otp_shadow_read(otp_val, otp_idx);
178 #elif defined(IMAGE_BL31) || defined(IMAGE_BL32)
179 ret = stm32_otp_read(otp_val, otp_idx);
180 #else
181 #error "Not supported"
182 #endif
183 if (ret != BSEC_OK) {
184 ERROR("BSEC: idx=%u Read Error\n", otp_idx);
185 return -1;
186 }
187
188 return 0;
189 }
190
191 #if defined(IMAGE_BL2)
reset_uart(uint32_t reset)192 static void reset_uart(uint32_t reset)
193 {
194 int ret;
195
196 ret = stm32mp_reset_assert(reset, RESET_TIMEOUT_US_1MS);
197 if (ret != 0) {
198 panic();
199 }
200
201 udelay(2);
202
203 ret = stm32mp_reset_deassert(reset, RESET_TIMEOUT_US_1MS);
204 if (ret != 0) {
205 panic();
206 }
207
208 mdelay(1);
209 }
210 #endif
211
set_console(uintptr_t base,uint32_t clk_rate)212 static void set_console(uintptr_t base, uint32_t clk_rate)
213 {
214 unsigned int console_flags;
215
216 if (console_stm32_register(base, clk_rate,
217 (uint32_t)STM32MP_UART_BAUDRATE, &console) == 0) {
218 panic();
219 }
220
221 console_flags = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH |
222 CONSOLE_FLAG_TRANSLATE_CRLF;
223 #if !defined(IMAGE_BL2) && defined(DEBUG)
224 console_flags |= CONSOLE_FLAG_RUNTIME;
225 #endif
226
227 console_set_scope(&console, console_flags);
228 }
229
stm32mp_uart_console_setup(void)230 int stm32mp_uart_console_setup(void)
231 {
232 struct dt_node_info dt_uart_info;
233 uint32_t clk_rate = 0U;
234 int result;
235 uint32_t boot_itf __unused;
236 uint32_t boot_instance __unused;
237
238 result = dt_get_stdout_uart_info(&dt_uart_info);
239
240 if ((result <= 0) ||
241 (dt_uart_info.status == DT_DISABLED)) {
242 return -ENODEV;
243 }
244
245 #if defined(IMAGE_BL2)
246 if ((dt_uart_info.clock < 0) ||
247 (dt_uart_info.reset < 0)) {
248 return -ENODEV;
249 }
250 #endif
251
252 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2)
253 stm32_get_boot_interface(&boot_itf, &boot_instance);
254
255 if ((boot_itf == BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) &&
256 (get_uart_address(boot_instance) == dt_uart_info.base)) {
257 return -EACCES;
258 }
259 #endif
260
261 #if defined(IMAGE_BL2)
262 if (dt_set_stdout_pinctrl() != 0) {
263 return -ENODEV;
264 }
265
266 clk_enable((unsigned long)dt_uart_info.clock);
267
268 reset_uart((uint32_t)dt_uart_info.reset);
269
270 clk_rate = clk_get_rate((unsigned long)dt_uart_info.clock);
271 #endif
272
273 set_console(dt_uart_info.base, clk_rate);
274
275 return 0;
276 }
277
278 #if EARLY_CONSOLE
plat_setup_early_console(void)279 void plat_setup_early_console(void)
280 {
281 #if defined(IMAGE_BL2) || STM32MP_RECONFIGURE_CONSOLE
282 plat_crash_console_init();
283 #endif
284 set_console(STM32MP_DEBUG_USART_BASE, STM32MP_DEBUG_USART_CLK_FRQ);
285 NOTICE("Early console setup\n");
286 }
287 #endif /* EARLY_CONSOLE */
288
289 /*****************************************************************************
290 * plat_is_smccc_feature_available() - This function checks whether SMCCC
291 * feature is availabile for platform.
292 * @fid: SMCCC function id
293 *
294 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
295 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
296 *****************************************************************************/
plat_is_smccc_feature_available(u_register_t fid)297 int32_t plat_is_smccc_feature_available(u_register_t fid)
298 {
299 switch (fid) {
300 case SMCCC_ARCH_SOC_ID:
301 return SMC_ARCH_CALL_SUCCESS;
302 default:
303 return SMC_ARCH_CALL_NOT_SUPPORTED;
304 }
305 }
306
307 /* Get SOC version */
plat_get_soc_version(void)308 int32_t plat_get_soc_version(void)
309 {
310 uint32_t chip_id = stm32mp_get_chip_dev_id();
311 uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_ST_BKID, JEDEC_ST_MFID);
312
313 return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK));
314 }
315
316 /* Get SOC revision */
plat_get_soc_revision(void)317 int32_t plat_get_soc_revision(void)
318 {
319 return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK);
320 }
321
stm32_display_board_info(uint32_t board_id)322 void stm32_display_board_info(uint32_t board_id)
323 {
324 char rev[2];
325
326 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A';
327 rev[1] = '\0';
328 NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n",
329 BOARD_ID2NB(board_id),
330 BOARD_ID2VARCPN(board_id),
331 BOARD_ID2VARFG(board_id),
332 rev,
333 BOARD_ID2BOM(board_id));
334 }
335
stm32_save_boot_info(boot_api_context_t * boot_context)336 void stm32_save_boot_info(boot_api_context_t *boot_context)
337 {
338 uint32_t auth_status;
339
340 assert(boot_context->boot_interface_instance <= (BOOT_INST_MASK >> BOOT_INST_SHIFT));
341 assert(boot_context->boot_interface_selected <= (BOOT_ITF_MASK >> BOOT_ITF_SHIFT));
342 assert(boot_context->boot_partition_used_toboot <= (BOOT_PART_MASK >> BOOT_PART_SHIFT));
343
344 switch (boot_context->auth_status) {
345 case BOOT_API_CTX_AUTH_NO:
346 auth_status = 0x0U;
347 break;
348
349 case BOOT_API_CTX_AUTH_SUCCESS:
350 auth_status = 0x2U;
351 break;
352
353 case BOOT_API_CTX_AUTH_FAILED:
354 default:
355 auth_status = 0x1U;
356 break;
357 }
358
359 clk_enable(TAMP_BKP_REG_CLK);
360
361 mmio_clrsetbits_32(stm32_get_bkpr_boot_mode_addr(),
362 BOOT_ITF_MASK | BOOT_INST_MASK | BOOT_PART_MASK | BOOT_AUTH_MASK,
363 (boot_context->boot_interface_instance << BOOT_INST_SHIFT) |
364 (boot_context->boot_interface_selected << BOOT_ITF_SHIFT) |
365 (boot_context->boot_partition_used_toboot << BOOT_PART_SHIFT) |
366 (auth_status << BOOT_AUTH_SHIFT));
367
368 clk_disable(TAMP_BKP_REG_CLK);
369 }
370
stm32_get_boot_interface(uint32_t * interface,uint32_t * instance)371 void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance)
372 {
373 static uint32_t itf;
374
375 if (itf == 0U) {
376 clk_enable(TAMP_BKP_REG_CLK);
377
378 itf = mmio_read_32(stm32_get_bkpr_boot_mode_addr()) &
379 (BOOT_ITF_MASK | BOOT_INST_MASK);
380
381 clk_disable(TAMP_BKP_REG_CLK);
382 }
383
384 *interface = (itf & BOOT_ITF_MASK) >> BOOT_ITF_SHIFT;
385 *instance = (itf & BOOT_INST_MASK) >> BOOT_INST_SHIFT;
386 }
387
388 #if PSA_FWU_SUPPORT
stm32_fwu_set_boot_idx(void)389 void stm32_fwu_set_boot_idx(void)
390 {
391 clk_enable(TAMP_BKP_REG_CLK);
392 mmio_clrsetbits_32(stm32_get_bkpr_fwu_info_addr(),
393 FWU_INFO_IDX_MSK,
394 (plat_fwu_get_boot_idx() << FWU_INFO_IDX_OFF) &
395 FWU_INFO_IDX_MSK);
396 clk_disable(TAMP_BKP_REG_CLK);
397 }
398
stm32_get_and_dec_fwu_trial_boot_cnt(void)399 uint32_t stm32_get_and_dec_fwu_trial_boot_cnt(void)
400 {
401 uintptr_t bkpr_fwu_cnt = stm32_get_bkpr_fwu_info_addr();
402 uint32_t try_cnt;
403
404 clk_enable(TAMP_BKP_REG_CLK);
405 try_cnt = (mmio_read_32(bkpr_fwu_cnt) & FWU_INFO_CNT_MSK) >> FWU_INFO_CNT_OFF;
406
407 assert(try_cnt <= FWU_MAX_TRIAL_REBOOT);
408
409 if (try_cnt != 0U) {
410 mmio_clrsetbits_32(bkpr_fwu_cnt, FWU_INFO_CNT_MSK,
411 (try_cnt - 1U) << FWU_INFO_CNT_OFF);
412 }
413 clk_disable(TAMP_BKP_REG_CLK);
414
415 return try_cnt;
416 }
417
stm32_set_max_fwu_trial_boot_cnt(void)418 void stm32_set_max_fwu_trial_boot_cnt(void)
419 {
420 uintptr_t bkpr_fwu_cnt = stm32_get_bkpr_fwu_info_addr();
421
422 clk_enable(TAMP_BKP_REG_CLK);
423 mmio_clrsetbits_32(bkpr_fwu_cnt, FWU_INFO_CNT_MSK,
424 (FWU_MAX_TRIAL_REBOOT << FWU_INFO_CNT_OFF) & FWU_INFO_CNT_MSK);
425 clk_disable(TAMP_BKP_REG_CLK);
426 }
427
stm32_clear_fwu_trial_boot_cnt(void)428 void stm32_clear_fwu_trial_boot_cnt(void)
429 {
430 uintptr_t bkpr_fwu_cnt = stm32_get_bkpr_fwu_info_addr();
431
432 clk_enable(TAMP_BKP_REG_CLK);
433 mmio_clrbits_32(bkpr_fwu_cnt, FWU_INFO_CNT_MSK);
434 clk_disable(TAMP_BKP_REG_CLK);
435 }
436 #endif /* PSA_FWU_SUPPORT */
437