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Searched defs:tCWL (Results 1 – 21 of 21) sorted by relevance

/external/coreboot/util/inteltool/
Divy_memory.c71 unsigned int tRCD[2], tXP[2], tXPDLL[2], tRAS[2], tCWL[2], tRP[2], in ivybridge_dump_timings() local
/external/coreboot/src/northbridge/intel/haswell/native_raminit/
Draminit_native.h77 uint32_t tCWL; member
/external/coreboot/src/include/device/dram/
Dddr3.h135 u32 tCWL; member
/external/coreboot/src/northbridge/intel/sandybridge/
Draminit_common.h182 u32 tCWL : 4; /* [15..12] */ member
378 u32 tCWL; member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/jasperlake/
DMemInfoHob.h148 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
DFspmUpd.h492 UINT8 tCWL; member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/
DMemInfoHob.h162 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
DFspmUpd.h628 UINT8 tCWL; member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/raptorlake/
DMemInfoHob.h160 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
DFspmUpd.h641 UINT8 tCWL; member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/iot/raptorlake_s/
DMemInfoHob.h157 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/alderlake/
DMemInfoHob.h162 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
DFspmUpd.h628 UINT8 tCWL; member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/
DMemInfoHob.h172 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
DFspmUpd.h626 UINT8 tCWL; member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/
DMemInfoHob.h191 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
DFspmUpd.h626 UINT8 tCWL; member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/twinlake/
DMemInfoHob.h162 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
DFspmUpd.h628 UINT8 tCWL; member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/geminilake/2.2.3.1/
DFspmUpd.h75 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/geminilake/2.2.0.0/
DFspmUpd.h75 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. member