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Searched defs:tWR (Results 1 – 25 of 26) sorted by relevance

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/external/coreboot/src/northbridge/intel/pineview/
Draminit.h51 unsigned int tWR; member
73 unsigned int tWR; member
/external/coreboot/util/inteltool/
Divy_memory.c64 int tWR = 0, tRFC = 0; in ivybridge_dump_timings() local
/external/coreboot/src/northbridge/intel/haswell/native_raminit/
Draminit_native.h67 uint32_t tWR; member
/external/coreboot/src/include/device/dram/
Dddr3.h125 u32 tWR; member
Dddr2.h123 u32 tWR; member
/external/coreboot/src/northbridge/intel/sandybridge/
Draminit_common.h196 u32 tWR : 5; /* [28..24] */ member
369 u32 tWR; member
/external/coreboot/src/northbridge/intel/x4x/
Draminit.h152 unsigned int tWR; member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/jasperlake/
DMemInfoHob.h162 UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. member
DFspmUpd.h549 UINT8 tWR; member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/
DMemInfoHob.h176 UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. member
DFspmUpd.h687 UINT8 tWR; member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/raptorlake/
DMemInfoHob.h174 UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/iot/raptorlake_s/
DMemInfoHob.h171 UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/alderlake/
DMemInfoHob.h176 UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. member
DFspmUpd.h687 UINT8 tWR; member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/
DMemInfoHob.h186 UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. member
DFspmUpd.h680 UINT8 tWR; member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/
DMemInfoHob.h205 UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. member
DFspmUpd.h680 UINT8 tWR; member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/twinlake/
DMemInfoHob.h176 UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. member
DFspmUpd.h687 UINT8 tWR; member
/external/coreboot/src/northbridge/intel/gm45/
Draminit.c349 unsigned int tWR; member
Dgm45.h97 unsigned int tWR; member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/geminilake/2.2.3.1/
DFspmUpd.h89 UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. member
/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/geminilake/2.2.0.0/
DFspmUpd.h89 UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. member

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