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1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
2 
3 /*
4  * This file is created based on MT8188 Functional Specification
5  * Chapter number: 4.1
6  */
7 
8 #ifndef SOC_MEDIATEK_MT8188_PLL_H
9 #define SOC_MEDIATEK_MT8188_PLL_H
10 
11 #include <device/mmio.h>
12 #include <soc/pll_common.h>
13 #include <types.h>
14 
15 struct mtk_topckgen_regs {
16 	u32 reserved1[1];
17 	u32 clk_cfg_update;
18 	u32 clk_cfg_update1;
19 	u32 clk_cfg_update2;
20 	u32 clk_cfg_update3;
21 	u32 reserved2[3];
22 	u32 clk_cfg_0;
23 	u32 clk_cfg_0_set;
24 	u32 clk_cfg_0_clr;
25 	u32 clk_cfg_1;
26 	u32 clk_cfg_1_set;
27 	u32 clk_cfg_1_clr;
28 	u32 clk_cfg_2;
29 	u32 clk_cfg_2_set;
30 	u32 clk_cfg_2_clr;
31 	u32 clk_cfg_3;
32 	u32 clk_cfg_3_set;
33 	u32 clk_cfg_3_clr;
34 	u32 clk_cfg_4;
35 	u32 clk_cfg_4_set;
36 	u32 clk_cfg_4_clr;
37 	u32 clk_cfg_5;
38 	u32 clk_cfg_5_set;
39 	u32 clk_cfg_5_clr;
40 	u32 clk_cfg_6;
41 	u32 clk_cfg_6_set;
42 	u32 clk_cfg_6_clr;
43 	u32 clk_cfg_7;
44 	u32 clk_cfg_7_set;
45 	u32 clk_cfg_7_clr;
46 	u32 clk_cfg_8;
47 	u32 clk_cfg_8_set;
48 	u32 clk_cfg_8_clr;
49 	u32 clk_cfg_9;
50 	u32 clk_cfg_9_set;
51 	u32 clk_cfg_9_clr;
52 	u32 clk_cfg_10;
53 	u32 clk_cfg_10_set;
54 	u32 clk_cfg_10_clr;
55 	u32 clk_cfg_11;
56 	u32 clk_cfg_11_set;
57 	u32 clk_cfg_11_clr;
58 	u32 clk_cfg_12;
59 	u32 clk_cfg_12_set;
60 	u32 clk_cfg_12_clr;
61 	u32 clk_cfg_13;
62 	u32 clk_cfg_13_set;
63 	u32 clk_cfg_13_clr;
64 	u32 clk_cfg_14;
65 	u32 clk_cfg_14_set;
66 	u32 clk_cfg_14_clr;
67 	u32 clk_cfg_15;
68 	u32 clk_cfg_15_set;
69 	u32 clk_cfg_15_clr;
70 	u32 clk_cfg_16;
71 	u32 clk_cfg_16_set;
72 	u32 clk_cfg_16_clr;
73 	u32 clk_cfg_17;
74 	u32 clk_cfg_17_set;
75 	u32 clk_cfg_17_clr;
76 	u32 clk_cfg_18;
77 	u32 clk_cfg_18_set;
78 	u32 clk_cfg_18_clr;
79 	u32 clk_cfg_19;
80 	u32 clk_cfg_19_set;
81 	u32 clk_cfg_19_clr;
82 	u32 clk_cfg_20;
83 	u32 clk_cfg_20_set;
84 	u32 clk_cfg_20_clr;
85 	u32 clk_cfg_21;
86 	u32 clk_cfg_21_set;
87 	u32 clk_cfg_21_clr;
88 	u32 clk_cfg_22;
89 	u32 clk_cfg_22_set;
90 	u32 clk_cfg_22_clr;
91 	u32 clk_cfg_23;
92 	u32 clk_cfg_23_set;
93 	u32 clk_cfg_23_clr;
94 	u32 clk_cfg_24;
95 	u32 clk_cfg_24_set;
96 	u32 clk_cfg_24_clr;
97 	u32 clk_cfg_25;
98 	u32 clk_cfg_25_set;
99 	u32 clk_cfg_25_clr;
100 	u32 clk_cfg_26;
101 	u32 clk_cfg_26_set;
102 	u32 clk_cfg_26_clr;
103 	u32 clk_cfg_27;
104 	u32 clk_cfg_27_set;
105 	u32 clk_cfg_27_clr;
106 	u32 clk_cfg_28;
107 	u32 clk_cfg_28_set;
108 	u32 clk_cfg_28_clr;
109 	u32 clk_cfg_29;
110 	u32 clk_cfg_29_set;
111 	u32 clk_cfg_29_clr;
112 	u32 clk_cfg_30;
113 	u32 clk_cfg_30_set;
114 	u32 clk_cfg_30_clr;
115 	u32 clk_cfg_31;
116 	u32 clk_cfg_31_set;
117 	u32 clk_cfg_31_clr;
118 	u32 clk_cfg_32;
119 	u32 clk_cfg_32_set;
120 	u32 clk_cfg_32_clr;
121 	u32 clk_cfg_33;
122 	u32 clk_cfg_33_set;
123 	u32 clk_cfg_33_clr;
124 	u32 clk_cfg_34;
125 	u32 clk_cfg_34_set;
126 	u32 clk_cfg_34_clr;
127 	u32 clk_cfg_35;
128 	u32 clk_cfg_35_set;
129 	u32 clk_cfg_35_clr;
130 	u32 clk_cfg_36;
131 	u32 clk_cfg_36_set;
132 	u32 clk_cfg_36_clr;
133 	u32 clk_cfg_37;
134 	u32 clk_cfg_37_set;
135 	u32 clk_cfg_37_clr;
136 	u32 reserved3[7];
137 	u32 clk_extck_reg;
138 	u32 reserved4[1];
139 	u32 clk_dbg_cfg;
140 	u32 reserved5[2];
141 	u32 clk26cali_0;
142 	u32 clk26cali_1;
143 	u32 reserved6[3];
144 	u32 clk_misc_cfg_0;
145 	u32 reserved7[2];
146 	u32 clk_misc_cfg_1;
147 	u32 reserved8[2];
148 	u32 clk_misc_cfg_2;
149 	u32 reserved9[2];
150 	u32 clk_misc_cfg_3;
151 	u32 reserved10[2];
152 	u32 clk_misc_cfg_6;
153 	u32 reserved11[1];
154 	u32 clk_scp_cfg_0;
155 };
156 check_member(mtk_topckgen_regs, clk_cfg_update1, 0x0008);
157 check_member(mtk_topckgen_regs, clk_cfg_0, 0x0020);
158 check_member(mtk_topckgen_regs, clk_cfg_10_set, 0x009c);
159 check_member(mtk_topckgen_regs, clk_cfg_10_clr, 0x00a0);
160 check_member(mtk_topckgen_regs, clk_cfg_11_clr, 0x00ac);
161 check_member(mtk_topckgen_regs, clk_extck_reg, 0x0204);
162 check_member(mtk_topckgen_regs, clk26cali_0, 0x0218);
163 check_member(mtk_topckgen_regs, clk_misc_cfg_0, 0x022c);
164 check_member(mtk_topckgen_regs, clk_misc_cfg_1, 0x0238);
165 check_member(mtk_topckgen_regs, clk_misc_cfg_2, 0x0244);
166 check_member(mtk_topckgen_regs, clk_misc_cfg_3, 0x0250);
167 check_member(mtk_topckgen_regs, clk_misc_cfg_6, 0x025c);
168 check_member(mtk_topckgen_regs, clk_scp_cfg_0, 0x264);
169 
170 struct mtk_apmixed_regs {
171 	u32 ap_pll_con0;
172 	u32 ap_pll_con1;
173 	u32 ap_pll_con2;
174 	u32 ap_pll_con3;
175 	u32 reserved12[9];
176 	u32 apll1_tuner_con0;
177 	u32 apll2_tuner_con0;
178 	u32 apll3_tuner_con0;
179 	u32 apll4_tuner_con0;
180 	u32 apll5_tuner_con0;
181 	u32 ref_clk_con0;
182 	u32 ulposc_ctrl_sel;
183 	u32 reserved13[109];
184 	u32 armpll_ll_con0;
185 	u32 armpll_ll_con1;
186 	u32 armpll_ll_con2;
187 	u32 armpll_ll_con3;
188 	u32 armpll_bl_con0;
189 	u32 armpll_bl_con1;
190 	u32 armpll_bl_con2;
191 	u32 armpll_bl_con3;
192 	u32 ccipll_con0;
193 	u32 ccipll_con1;
194 	u32 ccipll_con2;
195 	u32 ccipll_con3;
196 	u32 reserved14[52];
197 	u32 apll1_con0;
198 	u32 apll1_con1;
199 	u32 apll1_con2;
200 	u32 apll1_con3;
201 	u32 apll1_con4;
202 	u32 apll2_con0;
203 	u32 apll2_con1;
204 	u32 apll2_con2;
205 	u32 apll2_con3;
206 	u32 apll2_con4;
207 	u32 apll3_con0;
208 	u32 apll3_con1;
209 	u32 apll3_con2;
210 	u32 apll3_con3;
211 	u32 apll3_con4;
212 	u32 mfgpll_con0;
213 	u32 mfgpll_con1;
214 	u32 mfgpll_con2;
215 	u32 mfgpll_con3;
216 	u32 reserved15[45];
217 	u32 apll4_con0;
218 	u32 apll4_con1;
219 	u32 apll4_con2;
220 	u32 apll4_con3;
221 	u32 apll4_con4;
222 	u32 apll5_con0;
223 	u32 apll5_con1;
224 	u32 apll5_con2;
225 	u32 apll5_con3;
226 	u32 apll5_con4;
227 	u32 adsppll_con0;
228 	u32 adsppll_con1;
229 	u32 adsppll_con2;
230 	u32 adsppll_con3;
231 	u32 mpll_con0;
232 	u32 mpll_con1;
233 	u32 mpll_con2;
234 	u32 mpll_con3;
235 	u32 ethpll_con0;
236 	u32 ethpll_con1;
237 	u32 ethpll_con2;
238 	u32 ethpll_con3;
239 	u32 mainpll_con0;
240 	u32 mainpll_con1;
241 	u32 mainpll_con2;
242 	u32 mainpll_con3;
243 	u32 reserved16[38];
244 	u32 univpll_con0;
245 	u32 univpll_con1;
246 	u32 univpll_con2;
247 	u32 univpll_con3;
248 	u32 msdcpll_con0;
249 	u32 msdcpll_con1;
250 	u32 msdcpll_con2;
251 	u32 msdcpll_con3;
252 	u32 tvdpll1_con0;
253 	u32 tvdpll1_con1;
254 	u32 tvdpll1_con2;
255 	u32 tvdpll1_con3;
256 	u32 tvdpll2_con0;
257 	u32 tvdpll2_con1;
258 	u32 tvdpll2_con2;
259 	u32 tvdpll2_con3;
260 	u32 mmpll_con0;
261 	u32 mmpll_con1;
262 	u32 mmpll_con2;
263 	u32 mmpll_con3;
264 	u32 imgpll_con0;
265 	u32 imgpll_con1;
266 	u32 imgpll_con2;
267 	u32 imgpll_con3;
268 	u32 reserved17[39];
269 	u32 ulposc1_con0;
270 	u32 ulposc1_con1;
271 	u32 ulposc1_con2;
272 };
273 check_member(mtk_apmixed_regs, ap_pll_con0, 0x0000);
274 check_member(mtk_apmixed_regs, apll4_tuner_con0, 0x0040);
275 check_member(mtk_apmixed_regs, ulposc_ctrl_sel, 0x004c);
276 check_member(mtk_apmixed_regs, armpll_ll_con0, 0x0204);
277 check_member(mtk_apmixed_regs, armpll_bl_con3, 0x0220);
278 check_member(mtk_apmixed_regs, ccipll_con3, 0x0230);
279 check_member(mtk_apmixed_regs, apll1_con3, 0x0310);
280 check_member(mtk_apmixed_regs, apll2_con2, 0x0320);
281 check_member(mtk_apmixed_regs, apll3_con1, 0x0330);
282 check_member(mtk_apmixed_regs, mainpll_con0, 0x045c);
283 check_member(mtk_apmixed_regs, univpll_con0, 0x0504);
284 check_member(mtk_apmixed_regs, mfgpll_con0, 0x0340);
285 check_member(mtk_apmixed_regs, apll4_con3, 0x0410);
286 check_member(mtk_apmixed_regs, apll5_con2, 0x0420);
287 check_member(mtk_apmixed_regs, mpll_con1, 0x0440);
288 check_member(mtk_apmixed_regs, mainpll_con1, 0x0460);
289 check_member(mtk_apmixed_regs, univpll_con3, 0x0510);
290 check_member(mtk_apmixed_regs, msdcpll_con3, 0x0520);
291 check_member(mtk_apmixed_regs, tvdpll2_con3, 0x0540);
292 check_member(mtk_apmixed_regs, mmpll_con3, 0x0550);
293 check_member(mtk_apmixed_regs, imgpll_con3, 0x0560);
294 check_member(mtk_apmixed_regs, ulposc1_con0, 0x0600);
295 check_member(mtk_apmixed_regs, ulposc1_con1, 0x0604);
296 check_member(mtk_apmixed_regs, ulposc1_con2, 0x0608);
297 
298 struct mt8188_pericfg_ao_regs {
299 	u32 reserved1[4];
300 	u32 peri_module_sw_cg_0_set;	/* 0x0010 */
301 	u32 peri_module_sw_cg_0_clr;	/* 0x0014 */
302 };
303 check_member(mt8188_pericfg_ao_regs, peri_module_sw_cg_0_set, 0x0010);
304 check_member(mt8188_pericfg_ao_regs, peri_module_sw_cg_0_clr, 0x0014);
305 static struct mt8188_pericfg_ao_regs *const mt8188_pericfg_ao = (void *)PERICFG_AO_BASE;
306 
307 enum {
308 	PLL_CKSQ_ON_DELAY = 100,
309 	PLL_PWR_ON_DELAY = 30,
310 	PLL_ISO_DELAY = 1,
311 	PLL_EN_DELAY = 20,
312 };
313 
314 enum {
315 	PCW_INTEGER_BITS = 8,
316 };
317 
318 enum {
319 	MT8188_PLL_EN = BIT(9),
320 	MT8188_APLL5_EN = BIT(9) | BIT(20),
321 	GLITCH_FREE_EN = BIT(12),
322 	PLL_DIV_EN = BIT(24) | BIT(25) | BIT(26) | BIT(27) |
323 		     BIT(28) | BIT(29) | BIT(30) | BIT(31),
324 };
325 
326 enum {
327 	MCU_DIV_MASK = 0x1f << 17,
328 	MCU_DIV_1 = 0x8 << 17,
329 
330 	MCU_MUX_MASK = 0x3 << 9,
331 	MCU_MUX_SRC_PLL = 0x1 << 9,
332 	MCU_MUX_SRC_26M = 0x0 << 9,
333 };
334 
335 /* PLL rate */
336 enum {
337 	ARMPLL_LL_HZ	= 500 * MHz,
338 	ARMPLL_BL_HZ	= 650 * MHz,
339 	CCIPLL_HZ	= 520 * MHz,
340 	ETHPLL_HZ	= 500 * MHz,
341 	MSDCPLL_HZ	= 384 * MHz,
342 	TVDPLL1_HZ	= 594 * MHz,
343 	TVDPLL2_HZ	= 594 * MHz,
344 	MMPLL_HZ	= 2750UL * MHz,
345 	MAINPLL_HZ	= 2184UL * MHz,
346 	IMGPLL_HZ	= 660 * MHz,
347 	UNIVPLL_HZ	= 2496UL * MHz,
348 	ADSPPLL_HZ	= 800 * MHz,
349 	APLL1_HZ	= 196608 * KHz,
350 	APLL2_HZ	= 180633600,
351 	APLL3_HZ	= 196608 * KHz,
352 	APLL4_HZ	= 196608 * KHz,
353 	APLL5_HZ	= 196608 * KHz,
354 	MFGPLL_HZ	= 390 * MHz,
355 };
356 
357 /* top_div rate */
358 enum {
359 	CLK26M_HZ		= 26 * MHz,
360 	UNIVPLL_D6_D2_HZ	= UNIVPLL_HZ / 6 / 2,
361 };
362 
363 /* top_mux rate */
364 enum {
365 	SPI_HZ		= UNIVPLL_D6_D2_HZ,
366 	UART_HZ		= CLK26M_HZ,
367 };
368 
369 DEFINE_BITFIELD(CLK_DBG_CFG_ABIST_CK_SEL, 14, 8)
370 DEFINE_BITFIELD(CLK_DBG_CFG_CKGEN_CK_SEL, 23, 16)
371 DEFINE_BITFIELD(CLK_DBG_CFG_METER_CK_SEL, 1, 0)
372 DEFINE_BITFIELD(CLK_DBG_CFG_CKGEN_EN, 24, 24)
373 DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24)
374 DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4)
375 DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16)
376 
377 enum {
378 	INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = (0x1f << 12) | (0x1 << 17) | (0x1 << 18),
379 	INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON = (0x10 << 12) | (0x1 << 17) | (0x0 << 18),
380 	INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK = (0x1 << 0) |
381 					      (0x1 << 1) |
382 					      (0x1 << 3) |
383 					      (0x1 << 4) |
384 					      (0x1f << 5) |
385 					      (0x1 << 20) |
386 					      (0x1 << 23) |
387 					      (0x1 << 30),
388 	INFRACFG_AO_INFRA_BUS_DCM_REG0_ON = (0x1 << 0) |
389 					    (0x1 << 1) |
390 					    (0x0 << 3) |
391 					    (0x0 << 4) |
392 					    (0x10 << 5) |
393 					    (0x1 << 20) |
394 					    (0x1 << 23) |
395 					    (0x1 << 30),
396 	INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK = (0xf << 0),
397 	INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON = (0x0 << 0),
398 	INFRACFG_AO_PERI_BUS_DCM_REG0_MASK = (0x1 << 0) |
399 					     (0x1 << 1) |
400 					     (0x1 << 3) |
401 					     (0x1 << 4) |
402 					     (0x1f << 5) |
403 					     (0x1f << 15) |
404 					     (0x1 << 20) |
405 					     (0x1 << 21),
406 	INFRACFG_AO_PERI_BUS_DCM_REG0_ON = (0x1 << 0) |
407 					   (0x1 << 1) |
408 					   (0x0 << 3) |
409 					   (0x0 << 4) |
410 					   (0x1f << 5) |
411 					   (0x1f << 15) |
412 					   (0x1 << 20) |
413 					   (0x1 << 21),
414 	INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK = (0x1 << 29) | (0x1 << 31),
415 	INFRACFG_AO_PERI_MODULE_DCM_REG0_ON = (0x1 << 29) | (0x1 << 31),
416 };
417 
418 #endif /* SOC_MEDIATEK_MT8188_PLL_H */
419