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Searched defs:usb_phy_config (Results 1 – 5 of 5) sorted by relevance

/external/coreboot/src/vendorcode/amd/fsp/cezanne/
DFspUsb.h46 struct usb_phy_config { struct
47 uint8_t Version_Major; ///< USB IP version
48 uint8_t Version_Minor; ///< USB IP version
49 uint8_t TableLength; ///< TableLength
50 uint8_t Reserved0;
51 struct fch_usb2_phy Usb2PhyPort[USB2_PORT_COUNT]; ///< USB 2.0 Driving Strength
52 struct fch_usb3_phy Usb3PhyPort[USB3_PORT_COUNT]; ///< USB3 PHY Adjustment
53 uint8_t BatteryChargerEnable; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
54 uint8_t PhyP3CpmP4Support; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
55 …hyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP
[all …]
/external/coreboot/src/vendorcode/amd/fsp/mendocino/
DFspUsb.h49 struct usb_phy_config { struct
50 uint8_t Version_Major; ///< USB IP version
51 uint8_t Version_Minor; ///< USB IP version
52 uint8_t TableLength; ///< TableLength
53 uint8_t Reserved0;
54 struct fch_usb2_phy Usb2PhyPort[USB2_PORT_COUNT]; ///< USB 2.0 Driving Strength
55 struct fch_usb3_phy Usb3PhyPort[USB3_PORT_COUNT]; ///< USB3 PHY Adjustment
56 uint8_t BatteryChargerEnable; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
57 uint8_t PhyP3CpmP4Support; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
58 …hyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP
[all …]
/external/coreboot/src/vendorcode/amd/fsp/phoenix/
DFspUsb.h49 struct usb_phy_config { struct
50 uint8_t Version_Major; ///< USB IP version
51 uint8_t Version_Minor; ///< USB IP version
52 uint8_t TableLength; ///< TableLength
53 uint8_t Reserved0;
54 struct fch_usb2_phy Usb2PhyPort[USB2_PORT_COUNT]; ///< USB 2.0 Driving Strength
55 struct fch_usb3_phy Usb3PhyPort[USB3_PORT_COUNT]; ///< USB3 PHY Adjustment
56 uint8_t BatteryChargerEnable; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
57 uint8_t PhyP3CpmP4Support; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
58 …hyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP
[all …]
/external/coreboot/src/vendorcode/amd/fsp/glinda/
DFspUsb.h51 struct usb_phy_config { struct
52 uint8_t Version_Major; ///< USB IP version
53 uint8_t Version_Minor; ///< USB IP version
54 uint8_t TableLength; ///< TableLength
55 uint8_t Reserved0;
56 struct fch_usb2_phy Usb2PhyPort[USB2_PORT_COUNT]; ///< USB 2.0 Driving Strength
57 struct fch_usb3_phy Usb3PhyPort[USB3_PORT_COUNT]; ///< USB3 PHY Adjustment
58 uint8_t BatteryChargerEnable; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
59 uint8_t PhyP3CpmP4Support; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
60 …hyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP
[all …]
/external/coreboot/src/soc/amd/phoenix/
Dchip_opensil.h77 struct usb_phy_config { struct
78 struct fch_usb2_phy Usb2PhyPort[USB2_PORT_COUNT]; ///< USB 2.0 Driving Strength
79 struct fch_usb3_phy Usb3PhyPort[USB3_PORT_COUNT]; ///< USB3 PHY Adjustment
80 uint8_t BatteryChargerEnable; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
81 uint8_t PhyP3CpmP4Support; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
82 …hyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP