1 /*
2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
4 * Copyright (c) 2024, Altera Corporation. All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include <assert.h>
10 #include <common/debug.h>
11 #include <common/runtime_svc.h>
12 #include <lib/mmio.h>
13 #include <tools_share/uuid.h>
14
15 #include "socfpga_fcs.h"
16 #include "socfpga_mailbox.h"
17 #include "socfpga_plat_def.h"
18 #include "socfpga_reset_manager.h"
19 #include "socfpga_sip_svc.h"
20 #include "socfpga_system_manager.h"
21
22 /* Total buffer the driver can hold */
23 #define FPGA_CONFIG_BUFFER_SIZE 4
24
25 static config_type request_type = NO_REQUEST;
26 static int current_block, current_buffer;
27 static int read_block, max_blocks;
28 static uint32_t send_id, rcv_id;
29 static uint32_t bytes_per_block, blocks_submitted;
30 static bool bridge_disable;
31 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
32 static uint32_t g_remapper_bypass;
33 #endif
34
35 /* RSU static variables */
36 static uint32_t rsu_dcmf_ver[4] = {0};
37 static uint16_t rsu_dcmf_stat[4] = {0};
38 static uint32_t rsu_max_retry;
39
40 /* SiP Service UUID */
41 DEFINE_SVC_UUID2(intl_svc_uid,
42 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a,
43 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81);
44
socfpga_sip_handler(uint32_t smc_fid,uint64_t x1,uint64_t x2,uint64_t x3,uint64_t x4,void * cookie,void * handle,uint64_t flags)45 static uint64_t socfpga_sip_handler(uint32_t smc_fid,
46 uint64_t x1,
47 uint64_t x2,
48 uint64_t x3,
49 uint64_t x4,
50 void *cookie,
51 void *handle,
52 uint64_t flags)
53 {
54 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
55 SMC_RET1(handle, SMC_UNK);
56 }
57
58 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE];
59
intel_fpga_sdm_write_buffer(struct fpga_config_info * buffer)60 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
61 {
62 uint32_t args[3];
63
64 while (max_blocks > 0 && buffer->size > buffer->size_written) {
65 args[0] = (1<<8);
66 args[1] = buffer->addr + buffer->size_written;
67 if (buffer->size - buffer->size_written <= bytes_per_block) {
68 args[2] = buffer->size - buffer->size_written;
69 current_buffer++;
70 current_buffer %= FPGA_CONFIG_BUFFER_SIZE;
71 } else {
72 args[2] = bytes_per_block;
73 }
74
75 buffer->size_written += args[2];
76 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args,
77 3U, CMD_INDIRECT);
78
79 buffer->subblocks_sent++;
80 max_blocks--;
81 }
82
83 return !max_blocks;
84 }
85
intel_fpga_sdm_write_all(void)86 static int intel_fpga_sdm_write_all(void)
87 {
88 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
89 if (intel_fpga_sdm_write_buffer(
90 &fpga_config_buffers[current_buffer])) {
91 break;
92 }
93 }
94 return 0;
95 }
96
intel_mailbox_fpga_config_isdone(void)97 static uint32_t intel_mailbox_fpga_config_isdone(void)
98 {
99 uint32_t ret;
100
101 switch (request_type) {
102 case RECONFIGURATION:
103 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
104 true);
105 break;
106 case BITSTREAM_AUTH:
107 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
108 false);
109 break;
110 default:
111 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS,
112 false);
113 break;
114 }
115
116 if (ret != 0U) {
117 if (ret == MBOX_CFGSTAT_STATE_CONFIG) {
118 return INTEL_SIP_SMC_STATUS_BUSY;
119 } else {
120 request_type = NO_REQUEST;
121 return INTEL_SIP_SMC_STATUS_ERROR;
122 }
123 }
124
125 if (bridge_disable != 0U) {
126 socfpga_bridges_enable(~0); /* Enable bridge */
127 bridge_disable = false;
128 }
129 request_type = NO_REQUEST;
130
131 return INTEL_SIP_SMC_STATUS_OK;
132 }
133
mark_last_buffer_xfer_completed(uint32_t * buffer_addr_completed)134 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed)
135 {
136 int i;
137
138 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
139 if (fpga_config_buffers[i].block_number == current_block) {
140 fpga_config_buffers[i].subblocks_sent--;
141 if (fpga_config_buffers[i].subblocks_sent == 0
142 && fpga_config_buffers[i].size <=
143 fpga_config_buffers[i].size_written) {
144 fpga_config_buffers[i].write_requested = 0;
145 current_block++;
146 *buffer_addr_completed =
147 fpga_config_buffers[i].addr;
148 return 0;
149 }
150 }
151 }
152
153 return -1;
154 }
155
intel_fpga_config_completed_write(uint32_t * completed_addr,uint32_t * count,uint32_t * job_id)156 static int intel_fpga_config_completed_write(uint32_t *completed_addr,
157 uint32_t *count, uint32_t *job_id)
158 {
159 uint32_t resp[5];
160 unsigned int resp_len = ARRAY_SIZE(resp);
161 int status = INTEL_SIP_SMC_STATUS_OK;
162 int all_completed = 1;
163 *count = 0;
164
165 while (*count < 3) {
166
167 status = mailbox_read_response(job_id,
168 resp, &resp_len);
169
170 if (status < 0) {
171 break;
172 }
173
174 max_blocks++;
175
176 if (mark_last_buffer_xfer_completed(
177 &completed_addr[*count]) == 0) {
178 *count = *count + 1;
179 } else {
180 break;
181 }
182 }
183
184 if (*count <= 0) {
185 if (status != MBOX_NO_RESPONSE &&
186 status != MBOX_TIMEOUT && resp_len != 0) {
187 mailbox_clear_response();
188 request_type = NO_REQUEST;
189 return INTEL_SIP_SMC_STATUS_ERROR;
190 }
191
192 *count = 0;
193 }
194
195 intel_fpga_sdm_write_all();
196
197 if (*count > 0) {
198 status = INTEL_SIP_SMC_STATUS_OK;
199 } else if (*count == 0) {
200 status = INTEL_SIP_SMC_STATUS_BUSY;
201 }
202
203 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
204 if (fpga_config_buffers[i].write_requested != 0) {
205 all_completed = 0;
206 break;
207 }
208 }
209
210 if (all_completed == 1) {
211 return INTEL_SIP_SMC_STATUS_OK;
212 }
213
214 return status;
215 }
216
intel_fpga_config_start(uint32_t flag)217 static int intel_fpga_config_start(uint32_t flag)
218 {
219 uint32_t argument = 0x1;
220 uint32_t response[3];
221 int status = 0;
222 unsigned int size = 0;
223 unsigned int resp_len = ARRAY_SIZE(response);
224
225 request_type = RECONFIGURATION;
226
227 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) {
228 bridge_disable = true;
229 }
230
231 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) {
232 size = 1;
233 bridge_disable = false;
234 request_type = BITSTREAM_AUTH;
235 }
236
237 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
238 intel_smmu_hps_remapper_init(0U);
239 #endif
240
241 mailbox_clear_response();
242
243 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U,
244 CMD_CASUAL, NULL, NULL);
245
246 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size,
247 CMD_CASUAL, response, &resp_len);
248
249 if (status < 0) {
250 bridge_disable = false;
251 request_type = NO_REQUEST;
252 return INTEL_SIP_SMC_STATUS_ERROR;
253 }
254
255 max_blocks = response[0];
256 bytes_per_block = response[1];
257
258 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
259 fpga_config_buffers[i].size = 0;
260 fpga_config_buffers[i].size_written = 0;
261 fpga_config_buffers[i].addr = 0;
262 fpga_config_buffers[i].write_requested = 0;
263 fpga_config_buffers[i].block_number = 0;
264 fpga_config_buffers[i].subblocks_sent = 0;
265 }
266
267 blocks_submitted = 0;
268 current_block = 0;
269 read_block = 0;
270 current_buffer = 0;
271
272 /* Disable bridge on full reconfiguration */
273 if (bridge_disable) {
274 socfpga_bridges_disable(~0);
275 }
276
277 return INTEL_SIP_SMC_STATUS_OK;
278 }
279
is_fpga_config_buffer_full(void)280 static bool is_fpga_config_buffer_full(void)
281 {
282 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
283 if (!fpga_config_buffers[i].write_requested) {
284 return false;
285 }
286 }
287 return true;
288 }
289
is_address_in_ddr_range(uint64_t addr,uint64_t size)290 bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
291 {
292 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE;
293 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size;
294
295 if (!addr && !size) {
296 return true;
297 }
298 if (size > (UINT64_MAX - addr)) {
299 return false;
300 }
301 if (addr < BL31_LIMIT) {
302 return false;
303 }
304 if (dram_region_end > dram_max_sz) {
305 return false;
306 }
307
308 return true;
309 }
310
intel_fpga_config_write(uint64_t mem,uint64_t size)311 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size)
312 {
313 int i;
314
315 intel_fpga_sdm_write_all();
316
317 if (!is_address_in_ddr_range(mem, size) ||
318 is_fpga_config_buffer_full()) {
319 return INTEL_SIP_SMC_STATUS_REJECTED;
320 }
321
322 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
323 intel_smmu_hps_remapper_init(&mem);
324 #endif
325
326 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
327 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE;
328
329 if (!fpga_config_buffers[j].write_requested) {
330 fpga_config_buffers[j].addr = mem;
331 fpga_config_buffers[j].size = size;
332 fpga_config_buffers[j].size_written = 0;
333 fpga_config_buffers[j].write_requested = 1;
334 fpga_config_buffers[j].block_number =
335 blocks_submitted++;
336 fpga_config_buffers[j].subblocks_sent = 0;
337 break;
338 }
339 }
340
341 if (is_fpga_config_buffer_full()) {
342 return INTEL_SIP_SMC_STATUS_BUSY;
343 }
344
345 return INTEL_SIP_SMC_STATUS_OK;
346 }
347
is_out_of_sec_range(uint64_t reg_addr)348 static int is_out_of_sec_range(uint64_t reg_addr)
349 {
350 #if DEBUG
351 return 0;
352 #endif
353
354 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
355 switch (reg_addr) {
356 case(0xF8011100): /* ECCCTRL1 */
357 case(0xF8011104): /* ECCCTRL2 */
358 case(0xF8011110): /* ERRINTEN */
359 case(0xF8011114): /* ERRINTENS */
360 case(0xF8011118): /* ERRINTENR */
361 case(0xF801111C): /* INTMODE */
362 case(0xF8011120): /* INTSTAT */
363 case(0xF8011124): /* DIAGINTTEST */
364 case(0xF801112C): /* DERRADDRA */
365 case(0xFA000000): /* SMMU SCR0 */
366 case(0xFA000004): /* SMMU SCR1 */
367 case(0xFA000400): /* SMMU NSCR0 */
368 case(0xFA004000): /* SMMU SSD0_REG */
369 case(0xFA000820): /* SMMU SMR8 */
370 case(0xFA000c20): /* SMMU SCR8 */
371 case(0xFA028000): /* SMMU CB8_SCTRL */
372 case(0xFA001020): /* SMMU CBAR8 */
373 case(0xFA028030): /* SMMU TCR_LPAE */
374 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */
375 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */
376 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */
377 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */
378 case(0xFA028010): /* SMMU_CB8)TCR2 */
379 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */
380 case(0xFA001820): /* SMMU_CBA2R8 */
381 case(0xFA000074): /* SMMU_STLBGSTATUS */
382 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */
383 case(0xFA000060): /* SMMU_STLBIALL */
384 case(0xFA000070): /* SMMU_STLBGSYNC */
385 case(0xFA028618): /* CB8_TLBALL */
386 case(0xFA0287F0): /* CB8_TLBSYNC */
387 case(0xFFD12028): /* SDMMCGRP_CTRL */
388 case(0xFFD12044): /* EMAC0 */
389 case(0xFFD12048): /* EMAC1 */
390 case(0xFFD1204C): /* EMAC2 */
391 case(0xFFD12090): /* ECC_INT_MASK_VALUE */
392 case(0xFFD12094): /* ECC_INT_MASK_SET */
393 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */
394 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */
395 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */
396 case(0xFFD120C0): /* NOC_TIMEOUT */
397 case(0xFFD120C4): /* NOC_IDLEREQ_SET */
398 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */
399 case(0xFFD120D0): /* NOC_IDLEACK */
400 case(0xFFD120D4): /* NOC_IDLESTATUS */
401 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */
402 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */
403 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */
404 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */
405 return 0;
406 #else
407 switch (reg_addr) {
408
409 case(0xF8011104): /* ECCCTRL2 */
410 case(0xFFD12028): /* SDMMCGRP_CTRL */
411 case(0xFFD120C4): /* NOC_IDLEREQ_SET */
412 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */
413 case(0xFFD120D0): /* NOC_IDLEACK */
414
415
416 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */
417 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */
418 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */
419 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */
420 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */
421 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */
422 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */
423 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */
424
425 case(SOCFPGA_ECC_QSPI(INITSTAT)): /* ECC_QSPI_INITSTAT */
426 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */
427 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */
428 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */
429 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */
430 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */
431 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */
432 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */
433 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */
434 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */
435 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */
436 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */
437 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */
438 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */
439 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */
440 #endif
441 case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */
442 case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */
443 case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */
444 case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */
445 case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */
446 case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */
447 case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */
448 case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */
449 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */
450 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */
451 return 0;
452
453 default:
454 break;
455 }
456
457 return -1;
458 }
459
460 /* Secure register access */
461 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval)
462 {
463 if (is_out_of_sec_range(reg_addr)) {
464 return INTEL_SIP_SMC_STATUS_ERROR;
465 }
466
467 *retval = mmio_read_32(reg_addr);
468
469 return INTEL_SIP_SMC_STATUS_OK;
470 }
471
472 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val,
473 uint32_t *retval)
474 {
475 if (is_out_of_sec_range(reg_addr)) {
476 return INTEL_SIP_SMC_STATUS_ERROR;
477 }
478
479 switch (reg_addr) {
480 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */
481 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */
482 mmio_write_16(reg_addr, val);
483 break;
484 default:
485 mmio_write_32(reg_addr, val);
486 break;
487 }
488
489 return intel_secure_reg_read(reg_addr, retval);
490 }
491
492 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask,
493 uint32_t val, uint32_t *retval)
494 {
495 if (!intel_secure_reg_read(reg_addr, retval)) {
496 *retval &= ~mask;
497 *retval |= val & mask;
498 return intel_secure_reg_write(reg_addr, *retval, retval);
499 }
500
501 return INTEL_SIP_SMC_STATUS_ERROR;
502 }
503
504 /* Intel Remote System Update (RSU) services */
505 uint64_t intel_rsu_update_address;
506
507 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz)
508 {
509 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) {
510 return INTEL_SIP_SMC_RSU_ERROR;
511 }
512
513 return INTEL_SIP_SMC_STATUS_OK;
514 }
515
516 static uint32_t intel_rsu_get_device_info(uint32_t *respbuf,
517 unsigned int respbuf_sz)
518 {
519 if (mailbox_rsu_get_device_info((uint32_t *)respbuf, respbuf_sz) < 0) {
520 return INTEL_SIP_SMC_RSU_ERROR;
521 }
522
523 return INTEL_SIP_SMC_STATUS_OK;
524 }
525
526 uint32_t intel_rsu_update(uint64_t update_address)
527 {
528 if (update_address > SIZE_MAX) {
529 return INTEL_SIP_SMC_STATUS_REJECTED;
530 }
531
532 intel_rsu_update_address = update_address;
533 return INTEL_SIP_SMC_STATUS_OK;
534 }
535
536 static uint32_t intel_rsu_notify(uint32_t execution_stage)
537 {
538 if (mailbox_hps_stage_notify(execution_stage) < 0) {
539 return INTEL_SIP_SMC_RSU_ERROR;
540 }
541
542 return INTEL_SIP_SMC_STATUS_OK;
543 }
544
545 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz,
546 uint32_t *ret_stat)
547 {
548 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) {
549 return INTEL_SIP_SMC_RSU_ERROR;
550 }
551
552 *ret_stat = respbuf[8];
553 return INTEL_SIP_SMC_STATUS_OK;
554 }
555
556 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0,
557 uint64_t dcmf_ver_3_2)
558 {
559 rsu_dcmf_ver[0] = dcmf_ver_1_0;
560 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32;
561 rsu_dcmf_ver[2] = dcmf_ver_3_2;
562 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32;
563
564 return INTEL_SIP_SMC_STATUS_OK;
565 }
566
567 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat)
568 {
569 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16));
570 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16));
571 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16));
572 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16));
573
574 return INTEL_SIP_SMC_STATUS_OK;
575 }
576
577 /* Intel HWMON services */
578 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval)
579 {
580 if (mailbox_hwmon_readtemp(chan, retval) < 0) {
581 return INTEL_SIP_SMC_STATUS_ERROR;
582 }
583
584 return INTEL_SIP_SMC_STATUS_OK;
585 }
586
587 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval)
588 {
589 if (mailbox_hwmon_readvolt(chan, retval) < 0) {
590 return INTEL_SIP_SMC_STATUS_ERROR;
591 }
592
593 return INTEL_SIP_SMC_STATUS_OK;
594 }
595
596 /* Mailbox services */
597 static uint32_t intel_smc_fw_version(uint32_t *fw_version)
598 {
599 int status;
600 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE;
601 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U};
602
603 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U,
604 CMD_CASUAL, resp_data, &resp_len);
605
606 if (status < 0) {
607 return INTEL_SIP_SMC_STATUS_ERROR;
608 }
609
610 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) {
611 return INTEL_SIP_SMC_STATUS_ERROR;
612 }
613
614 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK;
615
616 return INTEL_SIP_SMC_STATUS_OK;
617 }
618
619 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args,
620 unsigned int len, uint32_t urgent, uint64_t response,
621 unsigned int resp_len, int *mbox_status,
622 unsigned int *len_in_resp)
623 {
624 *len_in_resp = 0;
625 *mbox_status = GENERIC_RESPONSE_ERROR;
626
627 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) {
628 return INTEL_SIP_SMC_STATUS_REJECTED;
629 }
630
631 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent,
632 (uint32_t *) response, &resp_len);
633
634 if (status < 0) {
635 *mbox_status = -status;
636 return INTEL_SIP_SMC_STATUS_ERROR;
637 }
638
639 *mbox_status = 0;
640 *len_in_resp = resp_len;
641
642 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE);
643
644 return INTEL_SIP_SMC_STATUS_OK;
645 }
646
647 static int intel_smc_get_usercode(uint32_t *user_code)
648 {
649 int status;
650 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE;
651
652 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL,
653 0U, CMD_CASUAL, user_code, &resp_len);
654
655 if (status < 0) {
656 return INTEL_SIP_SMC_STATUS_ERROR;
657 }
658
659 return INTEL_SIP_SMC_STATUS_OK;
660 }
661
662 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size,
663 uint32_t mode, uint32_t *job_id,
664 uint32_t *ret_size, uint32_t *mbox_error)
665 {
666 int status = 0;
667 uint32_t resp_len = size / MBOX_WORD_BYTE;
668
669 if (resp_len > MBOX_DATA_MAX_LEN) {
670 return INTEL_SIP_SMC_STATUS_REJECTED;
671 }
672
673 if (!is_address_in_ddr_range(addr, size)) {
674 return INTEL_SIP_SMC_STATUS_REJECTED;
675 }
676
677 if (mode == SERVICE_COMPLETED_MODE_ASYNC) {
678 status = mailbox_read_response_async(job_id,
679 NULL, (uint32_t *) addr, &resp_len, 0);
680 } else {
681 status = mailbox_read_response(job_id,
682 (uint32_t *) addr, &resp_len);
683
684 if (status == MBOX_NO_RESPONSE) {
685 status = MBOX_BUSY;
686 }
687 }
688
689 if (status == MBOX_NO_RESPONSE) {
690 return INTEL_SIP_SMC_STATUS_NO_RESPONSE;
691 }
692
693 if (status == MBOX_BUSY) {
694 return INTEL_SIP_SMC_STATUS_BUSY;
695 }
696
697 *ret_size = resp_len * MBOX_WORD_BYTE;
698 flush_dcache_range(addr, *ret_size);
699
700 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 ||
701 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) {
702 *mbox_error = -status;
703 } else if (status != MBOX_RET_OK) {
704 *mbox_error = -status;
705 return INTEL_SIP_SMC_STATUS_ERROR;
706 }
707
708 return INTEL_SIP_SMC_STATUS_OK;
709 }
710
711 /* Miscellaneous HPS services */
712 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask)
713 {
714 int status = 0;
715
716 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) {
717 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) {
718 status = socfpga_bridges_enable((uint32_t)mask);
719 } else {
720 status = socfpga_bridges_enable(~0);
721 }
722 } else {
723 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) {
724 status = socfpga_bridges_disable((uint32_t)mask);
725 } else {
726 status = socfpga_bridges_disable(~0);
727 }
728 }
729
730 if (status < 0) {
731 return INTEL_SIP_SMC_STATUS_ERROR;
732 }
733
734 return INTEL_SIP_SMC_STATUS_OK;
735 }
736
737 /* SDM SEU Error services */
738 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz)
739 {
740 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) {
741 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR;
742 }
743
744 return INTEL_SIP_SMC_STATUS_OK;
745 }
746
747 /* SDM SAFE SEU Error inject services */
748 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len)
749 {
750 if (mailbox_safe_inject_seu_err(command, len) < 0) {
751 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR;
752 }
753
754 return INTEL_SIP_SMC_STATUS_OK;
755 }
756
757 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
758 /* SMMU HPS Remapper */
759 void intel_smmu_hps_remapper_init(uint64_t *mem)
760 {
761 /* Read out Bit 1 value */
762 uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02);
763
764 if ((remap == 0x00) && (g_remapper_bypass == 0x00)) {
765 /* Update DRAM Base address for SDM SMMU */
766 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE);
767 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE);
768 *mem = *mem - DRAM_BASE;
769 } else {
770 *mem = *mem - DRAM_BASE;
771 }
772 }
773
774 int intel_smmu_hps_remapper_config(uint32_t remapper_bypass)
775 {
776 /* Read out the JTAG-ID from boot scratch register */
777 if (is_agilex5_A5F0() != 0) {
778 if (remapper_bypass == 0x01) {
779 g_remapper_bypass = remapper_bypass;
780 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), 0);
781 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), 0);
782 }
783 }
784 return INTEL_SIP_SMC_STATUS_OK;
785 }
786 #endif
787
788 /*
789 * This function is responsible for handling all SiP calls from the NS world
790 */
791
792 uintptr_t sip_smc_handler_v1(uint32_t smc_fid,
793 u_register_t x1,
794 u_register_t x2,
795 u_register_t x3,
796 u_register_t x4,
797 void *cookie,
798 void *handle,
799 u_register_t flags)
800 {
801 uint32_t retval = 0, completed_addr[3];
802 uint32_t retval2 = 0;
803 uint32_t mbox_error = 0;
804 uint64_t retval64, rsu_respbuf[9];
805 uint32_t seu_respbuf[3];
806 int status = INTEL_SIP_SMC_STATUS_OK;
807 int mbox_status;
808 unsigned int len_in_resp;
809 u_register_t x5, x6, x7;
810
811 switch (smc_fid) {
812 case SIP_SVC_UID:
813 /* Return UID to the caller */
814 SMC_UUID_RET(handle, intl_svc_uid);
815
816 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
817 status = intel_mailbox_fpga_config_isdone();
818 SMC_RET4(handle, status, 0, 0, 0);
819
820 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
821 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
822 INTEL_SIP_SMC_FPGA_CONFIG_ADDR,
823 INTEL_SIP_SMC_FPGA_CONFIG_SIZE -
824 INTEL_SIP_SMC_FPGA_CONFIG_ADDR);
825
826 case INTEL_SIP_SMC_FPGA_CONFIG_START:
827 status = intel_fpga_config_start(x1);
828 SMC_RET4(handle, status, 0, 0, 0);
829
830 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE:
831 status = intel_fpga_config_write(x1, x2);
832 SMC_RET4(handle, status, 0, 0, 0);
833
834 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE:
835 status = intel_fpga_config_completed_write(completed_addr,
836 &retval, &rcv_id);
837 switch (retval) {
838 case 1:
839 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
840 completed_addr[0], 0, 0);
841
842 case 2:
843 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
844 completed_addr[0],
845 completed_addr[1], 0);
846
847 case 3:
848 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
849 completed_addr[0],
850 completed_addr[1],
851 completed_addr[2]);
852
853 case 0:
854 SMC_RET4(handle, status, 0, 0, 0);
855
856 default:
857 mailbox_clear_response();
858 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
859 }
860
861 case INTEL_SIP_SMC_REG_READ:
862 status = intel_secure_reg_read(x1, &retval);
863 SMC_RET3(handle, status, retval, x1);
864
865 case INTEL_SIP_SMC_REG_WRITE:
866 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval);
867 SMC_RET3(handle, status, retval, x1);
868
869 case INTEL_SIP_SMC_REG_UPDATE:
870 status = intel_secure_reg_update(x1, (uint32_t)x2,
871 (uint32_t)x3, &retval);
872 SMC_RET3(handle, status, retval, x1);
873
874 case INTEL_SIP_SMC_RSU_STATUS:
875 status = intel_rsu_status(rsu_respbuf,
876 ARRAY_SIZE(rsu_respbuf));
877 if (status) {
878 SMC_RET1(handle, status);
879 } else {
880 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1],
881 rsu_respbuf[2], rsu_respbuf[3]);
882 }
883
884 case INTEL_SIP_SMC_RSU_UPDATE:
885 status = intel_rsu_update(x1);
886 SMC_RET1(handle, status);
887
888 case INTEL_SIP_SMC_RSU_NOTIFY:
889 status = intel_rsu_notify(x1);
890 SMC_RET1(handle, status);
891
892 case INTEL_SIP_SMC_RSU_RETRY_COUNTER:
893 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf,
894 ARRAY_SIZE(rsu_respbuf), &retval);
895 if (status) {
896 SMC_RET1(handle, status);
897 } else {
898 SMC_RET2(handle, status, retval);
899 }
900
901 case INTEL_SIP_SMC_RSU_DCMF_VERSION:
902 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
903 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0],
904 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]);
905
906 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION:
907 status = intel_rsu_copy_dcmf_version(x1, x2);
908 SMC_RET1(handle, status);
909
910 case INTEL_SIP_SMC_RSU_GET_DEVICE_INFO:
911 status = intel_rsu_get_device_info((uint32_t *)rsu_respbuf,
912 ARRAY_SIZE(rsu_respbuf));
913 if (status) {
914 SMC_RET1(handle, status);
915 } else {
916 SMC_RET5(handle, status, rsu_respbuf[0], rsu_respbuf[1],
917 rsu_respbuf[2], rsu_respbuf[3]);
918 }
919
920 case INTEL_SIP_SMC_RSU_DCMF_STATUS:
921 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK,
922 ((uint64_t)rsu_dcmf_stat[3] << 48) |
923 ((uint64_t)rsu_dcmf_stat[2] << 32) |
924 ((uint64_t)rsu_dcmf_stat[1] << 16) |
925 rsu_dcmf_stat[0]);
926
927 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS:
928 status = intel_rsu_copy_dcmf_status(x1);
929 SMC_RET1(handle, status);
930
931 case INTEL_SIP_SMC_RSU_MAX_RETRY:
932 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry);
933
934 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY:
935 rsu_max_retry = x1;
936 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK);
937
938 case INTEL_SIP_SMC_ECC_DBE:
939 status = intel_ecc_dbe_notification(x1);
940 SMC_RET1(handle, status);
941
942 case INTEL_SIP_SMC_SERVICE_COMPLETED:
943 status = intel_smc_service_completed(x1, x2, x3, &rcv_id,
944 &len_in_resp, &mbox_error);
945 SMC_RET4(handle, status, mbox_error, x1, len_in_resp);
946
947 case INTEL_SIP_SMC_FIRMWARE_VERSION:
948 status = intel_smc_fw_version(&retval);
949 SMC_RET2(handle, status, retval);
950
951 case INTEL_SIP_SMC_MBOX_SEND_CMD:
952 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
953 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
954 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6,
955 &mbox_status, &len_in_resp);
956 SMC_RET3(handle, status, mbox_status, len_in_resp);
957
958 case INTEL_SIP_SMC_GET_USERCODE:
959 status = intel_smc_get_usercode(&retval);
960 SMC_RET2(handle, status, retval);
961
962 case INTEL_SIP_SMC_FCS_CRYPTION:
963 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
964
965 if (x1 == FCS_MODE_DECRYPT) {
966 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id);
967 } else if (x1 == FCS_MODE_ENCRYPT) {
968 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id);
969 } else {
970 status = INTEL_SIP_SMC_STATUS_REJECTED;
971 }
972
973 SMC_RET3(handle, status, x4, x5);
974
975 case INTEL_SIP_SMC_FCS_CRYPTION_EXT:
976 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
977 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
978 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
979
980 if (x3 == FCS_MODE_DECRYPT) {
981 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6,
982 (uint32_t *) &x7, &mbox_error);
983 } else if (x3 == FCS_MODE_ENCRYPT) {
984 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6,
985 (uint32_t *) &x7, &mbox_error);
986 } else {
987 status = INTEL_SIP_SMC_STATUS_REJECTED;
988 }
989
990 SMC_RET4(handle, status, mbox_error, x6, x7);
991
992 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER:
993 status = intel_fcs_random_number_gen(x1, &retval64,
994 &mbox_error);
995 SMC_RET4(handle, status, mbox_error, x1, retval64);
996
997 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT:
998 status = intel_fcs_random_number_gen_ext(x1, x2, x3,
999 &send_id);
1000 SMC_RET1(handle, status);
1001
1002 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE:
1003 status = intel_fcs_send_cert(x1, x2, &send_id);
1004 SMC_RET1(handle, status);
1005
1006 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA:
1007 status = intel_fcs_get_provision_data(&send_id);
1008 SMC_RET1(handle, status);
1009
1010 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH:
1011 status = intel_fcs_cntr_set_preauth(x1, x2, x3,
1012 &mbox_error);
1013 SMC_RET2(handle, status, mbox_error);
1014
1015 case INTEL_SIP_SMC_HPS_SET_BRIDGES:
1016 status = intel_hps_set_bridges(x1, x2);
1017 SMC_RET1(handle, status);
1018
1019 case INTEL_SIP_SMC_HWMON_READTEMP:
1020 status = intel_hwmon_readtemp(x1, &retval);
1021 SMC_RET2(handle, status, retval);
1022
1023 case INTEL_SIP_SMC_HWMON_READVOLT:
1024 status = intel_hwmon_readvolt(x1, &retval);
1025 SMC_RET2(handle, status, retval);
1026
1027 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN:
1028 status = intel_fcs_sigma_teardown(x1, &mbox_error);
1029 SMC_RET2(handle, status, mbox_error);
1030
1031 case INTEL_SIP_SMC_FCS_CHIP_ID:
1032 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error);
1033 SMC_RET4(handle, status, mbox_error, retval, retval2);
1034
1035 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY:
1036 status = intel_fcs_attestation_subkey(x1, x2, x3,
1037 (uint32_t *) &x4, &mbox_error);
1038 SMC_RET4(handle, status, mbox_error, x3, x4);
1039
1040 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS:
1041 status = intel_fcs_get_measurement(x1, x2, x3,
1042 (uint32_t *) &x4, &mbox_error);
1043 SMC_RET4(handle, status, mbox_error, x3, x4);
1044
1045 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT:
1046 status = intel_fcs_get_attestation_cert(x1, x2,
1047 (uint32_t *) &x3, &mbox_error);
1048 SMC_RET4(handle, status, mbox_error, x2, x3);
1049
1050 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD:
1051 status = intel_fcs_create_cert_on_reload(x1, &mbox_error);
1052 SMC_RET2(handle, status, mbox_error);
1053
1054 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION:
1055 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error);
1056 SMC_RET3(handle, status, mbox_error, retval);
1057
1058 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION:
1059 status = intel_fcs_close_crypto_service_session(x1, &mbox_error);
1060 SMC_RET2(handle, status, mbox_error);
1061
1062 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY:
1063 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id);
1064 SMC_RET1(handle, status);
1065
1066 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY:
1067 status = intel_fcs_export_crypto_service_key(x1, x2, x3,
1068 (uint32_t *) &x4, &mbox_error);
1069 SMC_RET4(handle, status, mbox_error, x3, x4);
1070
1071 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY:
1072 status = intel_fcs_remove_crypto_service_key(x1, x2,
1073 &mbox_error);
1074 SMC_RET2(handle, status, mbox_error);
1075
1076 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO:
1077 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3,
1078 (uint32_t *) &x4, &mbox_error);
1079 SMC_RET4(handle, status, mbox_error, x3, x4);
1080
1081 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT:
1082 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1083 status = intel_fcs_get_digest_init(x1, x2, x3,
1084 x4, x5, &mbox_error);
1085 SMC_RET2(handle, status, mbox_error);
1086
1087 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE:
1088 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1089 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1090 status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
1091 x4, x5, (uint32_t *) &x6, false,
1092 &mbox_error);
1093 SMC_RET4(handle, status, mbox_error, x5, x6);
1094
1095 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE:
1096 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1097 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1098 status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
1099 x4, x5, (uint32_t *) &x6, true,
1100 &mbox_error);
1101 SMC_RET4(handle, status, mbox_error, x5, x6);
1102
1103 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE:
1104 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1105 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1106 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
1107 x4, x5, (uint32_t *) &x6, false,
1108 &mbox_error, &send_id);
1109 SMC_RET4(handle, status, mbox_error, x5, x6);
1110
1111 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE:
1112 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1113 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1114 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
1115 x4, x5, (uint32_t *) &x6, true,
1116 &mbox_error, &send_id);
1117 SMC_RET4(handle, status, mbox_error, x5, x6);
1118
1119 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT:
1120 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1121 status = intel_fcs_mac_verify_init(x1, x2, x3,
1122 x4, x5, &mbox_error);
1123 SMC_RET2(handle, status, mbox_error);
1124
1125 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE:
1126 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1127 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1128 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1129 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
1130 x4, x5, (uint32_t *) &x6, x7,
1131 false, &mbox_error);
1132 SMC_RET4(handle, status, mbox_error, x5, x6);
1133
1134 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE:
1135 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1136 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1137 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1138 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
1139 x4, x5, (uint32_t *) &x6, x7,
1140 true, &mbox_error);
1141 SMC_RET4(handle, status, mbox_error, x5, x6);
1142
1143 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE:
1144 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1145 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1146 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1147 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
1148 x4, x5, (uint32_t *) &x6, x7,
1149 false, &mbox_error, &send_id);
1150 SMC_RET4(handle, status, mbox_error, x5, x6);
1151
1152 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE:
1153 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1154 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1155 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1156 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
1157 x4, x5, (uint32_t *) &x6, x7,
1158 true, &mbox_error, &send_id);
1159 SMC_RET4(handle, status, mbox_error, x5, x6);
1160
1161 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT:
1162 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1163 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3,
1164 x4, x5, &mbox_error);
1165 SMC_RET2(handle, status, mbox_error);
1166
1167 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE:
1168 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1169 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1170 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2,
1171 x3, x4, x5, (uint32_t *) &x6, false,
1172 &mbox_error);
1173 SMC_RET4(handle, status, mbox_error, x5, x6);
1174
1175 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE:
1176 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1177 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1178 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2,
1179 x3, x4, x5, (uint32_t *) &x6, true,
1180 &mbox_error);
1181 SMC_RET4(handle, status, mbox_error, x5, x6);
1182
1183 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE:
1184 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1185 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1186 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1,
1187 x2, x3, x4, x5, (uint32_t *) &x6, false,
1188 &mbox_error, &send_id);
1189 SMC_RET4(handle, status, mbox_error, x5, x6);
1190
1191 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE:
1192 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1193 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1194 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1,
1195 x2, x3, x4, x5, (uint32_t *) &x6, true,
1196 &mbox_error, &send_id);
1197 SMC_RET4(handle, status, mbox_error, x5, x6);
1198
1199 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT:
1200 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1201 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3,
1202 x4, x5, &mbox_error);
1203 SMC_RET2(handle, status, mbox_error);
1204
1205 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE:
1206 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1207 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1208 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3,
1209 x4, x5, (uint32_t *) &x6, &mbox_error);
1210 SMC_RET4(handle, status, mbox_error, x5, x6);
1211
1212 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT:
1213 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1214 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3,
1215 x4, x5, &mbox_error);
1216 SMC_RET2(handle, status, mbox_error);
1217
1218 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE:
1219 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1220 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1221 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3,
1222 x4, x5, (uint32_t *) &x6, &mbox_error);
1223 SMC_RET4(handle, status, mbox_error, x5, x6);
1224
1225 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT:
1226 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1227 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3,
1228 x4, x5, &mbox_error);
1229 SMC_RET2(handle, status, mbox_error);
1230
1231 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE:
1232 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1233 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1234 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1235 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
1236 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1237 x7, false, &mbox_error);
1238 SMC_RET4(handle, status, mbox_error, x5, x6);
1239
1240 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE:
1241 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1242 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1243 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1244 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(
1245 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1246 x7, false, &mbox_error, &send_id);
1247 SMC_RET4(handle, status, mbox_error, x5, x6);
1248
1249 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE:
1250 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1251 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1252 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1253 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(
1254 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1255 x7, true, &mbox_error, &send_id);
1256 SMC_RET4(handle, status, mbox_error, x5, x6);
1257
1258 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE:
1259 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1260 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1261 x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
1262 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
1263 x1, x2, x3, x4, x5, (uint32_t *) &x6,
1264 x7, true, &mbox_error);
1265 SMC_RET4(handle, status, mbox_error, x5, x6);
1266
1267 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT:
1268 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1269 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3,
1270 x4, x5, &mbox_error);
1271 SMC_RET2(handle, status, mbox_error);
1272
1273 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE:
1274 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3,
1275 (uint32_t *) &x4, &mbox_error);
1276 SMC_RET4(handle, status, mbox_error, x3, x4);
1277
1278 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT:
1279 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1280 status = intel_fcs_ecdh_request_init(x1, x2, x3,
1281 x4, x5, &mbox_error);
1282 SMC_RET2(handle, status, mbox_error);
1283
1284 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE:
1285 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1286 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1287 status = intel_fcs_ecdh_request_finalize(x1, x2, x3,
1288 x4, x5, (uint32_t *) &x6, &mbox_error);
1289 SMC_RET4(handle, status, mbox_error, x5, x6);
1290
1291 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT:
1292 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1293 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5,
1294 &mbox_error);
1295 SMC_RET2(handle, status, mbox_error);
1296
1297 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE:
1298 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1299 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1300 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
1301 x5, x6, false, &send_id);
1302 SMC_RET1(handle, status);
1303
1304 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE:
1305 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1306 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
1307 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
1308 x5, x6, true, &send_id);
1309 SMC_RET1(handle, status);
1310
1311 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
1312 case INTEL_SIP_SMC_FCS_SDM_REMAPPER_CONFIG:
1313 status = intel_smmu_hps_remapper_config(x1);
1314 SMC_RET1(handle, status);
1315 #endif
1316
1317 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384:
1318 status = intel_fcs_get_rom_patch_sha384(x1, &retval64,
1319 &mbox_error);
1320 SMC_RET4(handle, status, mbox_error, x1, retval64);
1321
1322 case INTEL_SIP_SMC_SVC_VERSION:
1323 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
1324 SIP_SVC_VERSION_MAJOR,
1325 SIP_SVC_VERSION_MINOR);
1326
1327 case INTEL_SIP_SMC_SEU_ERR_STATUS:
1328 status = intel_sdm_seu_err_read(seu_respbuf,
1329 ARRAY_SIZE(seu_respbuf));
1330 if (status) {
1331 SMC_RET1(handle, status);
1332 } else {
1333 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]);
1334 }
1335
1336 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR:
1337 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2);
1338 SMC_RET1(handle, status);
1339
1340 default:
1341 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
1342 cookie, handle, flags);
1343 }
1344 }
1345
1346 uintptr_t sip_smc_handler(uint32_t smc_fid,
1347 u_register_t x1,
1348 u_register_t x2,
1349 u_register_t x3,
1350 u_register_t x4,
1351 void *cookie,
1352 void *handle,
1353 u_register_t flags)
1354 {
1355 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK;
1356
1357 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN &&
1358 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) {
1359 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4,
1360 cookie, handle, flags);
1361 } else {
1362 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4,
1363 cookie, handle, flags);
1364 }
1365 }
1366
1367 DECLARE_RT_SVC(
1368 socfpga_sip_svc,
1369 OEN_SIP_START,
1370 OEN_SIP_END,
1371 SMC_TYPE_FAST,
1372 NULL,
1373 sip_smc_handler
1374 );
1375
1376 DECLARE_RT_SVC(
1377 socfpga_sip_svc_std,
1378 OEN_SIP_START,
1379 OEN_SIP_END,
1380 SMC_TYPE_YIELD,
1381 NULL,
1382 sip_smc_handler
1383 );
1384