1 /* SPDX-License-Identifier: BSD-3-Clause */
2
3 //-----------------------------------------------------------------------------
4 // Include files
5 //-----------------------------------------------------------------------------
6 #include "dramc_common.h"
7 #include "x_hal_io.h"
8 #include "dramc_actiming.h"
9 #include "dramc_int_global.h"
10
11 //-----------------------------------------------------------------------------
12 // Global variables
13 //-----------------------------------------------------------------------------
14
15 //-------------------------------------------------------------------------
16 /** u1GetACTimingIdx()
17 * Retrieve internal ACTimingTbl's index according to dram type, freqGroup, Read DBI status
18 * @param p Pointer of context created by DramcCtxCreate.
19 * @retval u1TimingIdx Return ACTimingTbl entry's index
20 */
21 //-------------------------------------------------------------------------
u1GetACTimingIdx(DRAMC_CTX_T * p)22 static U8 u1GetACTimingIdx(DRAMC_CTX_T *p)
23 {
24 U8 u1TimingIdx = 0xff, u1TmpIdx;
25 U8 u1TmpDramType = p->dram_type;
26
27 #if (__LP5_COMBO__ == TRUE)
28 if (TRUE == is_lp5_family(p))
29 {
30 u1TmpDramType = TYPE_LPDDR5;
31 }
32 else
33 #endif
34 {
35 // LP4/LP4P/LP4X use same table
36 if (u1TmpDramType == TYPE_LPDDR4X || u1TmpDramType == TYPE_LPDDR4P)
37 u1TmpDramType = TYPE_LPDDR4;
38 }
39
40 #if (__LP5_COMBO__ == TRUE)
41 if (TRUE == is_lp5_family(p))
42 {
43 for (u1TmpIdx = 0; u1TmpIdx < AC_TIMING_NUMBER_LP5; u1TmpIdx++)
44 {
45 if ((ACTimingTbl_LP5[u1TmpIdx].dramType == u1TmpDramType) &&
46 /* p->frequency may not be in ACTimingTable, use p->freqGroup */
47 (ACTimingTbl_LP5[u1TmpIdx].freq == p->freqGroup) &&
48 (ACTimingTbl_LP5[u1TmpIdx].readDBI == p->DBI_R_onoff[p->dram_fsp]) &&
49 (ACTimingTbl_LP5[u1TmpIdx].DivMode == vGet_Div_Mode(p)) && // Darren for LP4 1:4 and 1:8 mode
50 (ACTimingTbl_LP5[u1TmpIdx].cbtMode == vGet_Dram_CBT_Mode(p)) //LP4 byte/mixed mode dram both use byte mode ACTiming
51 )
52 {
53 u1TimingIdx = u1TmpIdx;
54 msg("match AC timing %d\n", u1TimingIdx);
55 reg_msg("match AC timing %d\n", u1TimingIdx);
56 break;
57 }
58 }
59 }
60 else
61 #endif
62 {
63 for (u1TmpIdx = 0; u1TmpIdx < AC_TIMING_NUMBER_LP4; u1TmpIdx++)
64 {
65 if ((ACTimingTbl_LP4[u1TmpIdx].dramType == u1TmpDramType) &&
66 /* p->frequency may not be in ACTimingTable, use p->freqGroup */
67 (ACTimingTbl_LP4[u1TmpIdx].freq == p->freqGroup) &&
68 (ACTimingTbl_LP4[u1TmpIdx].readDBI == p->DBI_R_onoff[p->dram_fsp]) &&
69 (ACTimingTbl_LP4[u1TmpIdx].DivMode == vGet_Div_Mode(p)) && // Darren for LP4 1:4 and 1:8 mode
70 (ACTimingTbl_LP4[u1TmpIdx].cbtMode == vGet_Dram_CBT_Mode(p)) //LP4 byte/mixed mode dram both use byte mode ACTiming
71 )
72 {
73 u1TimingIdx = u1TmpIdx;
74 msg("match AC timing %d\n", u1TimingIdx);
75 reg_msg("match AC timing %d\n", u1TimingIdx);
76 msg("dramType %d, freq %d, readDBI %d, DivMode %d, cbtMode %d\n", u1TmpDramType, p->freqGroup, p->DBI_R_onoff[p->dram_fsp], vGet_Div_Mode(p), vGet_Dram_CBT_Mode(p));
77 break;
78 }
79 }
80 }
81
82 return u1TimingIdx;
83 }
84
85 //-------------------------------------------------------------------------
86 /** UpdateACTimingReg()
87 * ACTiming related register field update
88 * @param p Pointer of context created by DramcCtxCreate.
89 * @param ACTbl Pointer to correct ACTiming table struct
90 * @retval status (DRAM_STATUS_T): DRAM_OK or DRAM_FAIL
91 */
92 //-------------------------------------------------------------------------
93 #if __LP5_COMBO__
DdrUpdateACTimingReg_LP5(DRAMC_CTX_T * p,const ACTime_T_LP5 * ACTbl)94 DRAM_STATUS_T DdrUpdateACTimingReg_LP5(DRAMC_CTX_T *p, const ACTime_T_LP5 *ACTbl)
95 {
96 ACTime_T_LP5 ACTblFinal;
97 U8 backup_rank = p->rank;
98 DRAM_ODT_MODE_T r2w_odt_onoff = p->odt_onoff; //Variable used in step 1 (decide to use odt on or off ACTiming)
99 // ACTiming regs that have ODT on/off values -> declare variables to save the wanted value
100 // -> Used to retrieve correct SHU_ACTIM2_TR2W value and write into final register field
101 #ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
102 U8 u1RANKINCTL = 0;
103 #endif
104 U8 RODT_TRACKING_SAVEING_MCK = 0, u1ROOT = 0, u1TXRANKINCTL = 0, u1TXDLY = 0, u1DATLAT_DSEL = 0; //Used to store tmp ACTiming values
105
106 #if SAMSUNG_LP4_NWR_WORKAROUND
107 U8 u1TWTR = 0, u1TWTR_05T = 0, u1TWTR_TMP = 0;
108 #endif
109 // ACTiming regs that aren't currently in ACTime_T struct
110 U8 u1TREFBW = 0; //REFBW_FR (tREFBW) for LP3, REFBW_FR=0 & TREFBWIG=1 (by CF)
111 U8 u1TFAW_05T=0, u1TRRD_05T=0;
112 U16 u2XRTWTW = 0, u2XTRTRT = 0, u2XRTW2R = 0, u2XRTR2W = 0, u2TFAW = 0;
113 U16 u2TRTW=0, u2TRTW_05T=0, u2TMRR2W=0, u2TRRD=0;
114
115 #if XRTRTR_NEW_CROSS_RK_MODE
116 U16 u2PHSINCTL = 0;
117 #endif
118
119 U32 u4RankINCTL_ROOT;
120
121 if(ACTbl == NULL)
122 return DRAM_FAIL;
123 ACTblFinal = *ACTbl;
124
125 // ----Step 1: Perform ACTiming table adjustments according to different usage/scenarios--------------------------
126 #if ENABLE_TX_WDQS
127 r2w_odt_onoff = ODT_ON;
128 #else
129 r2w_odt_onoff = p->odt_onoff;
130 #endif
131
132 // ACTimings that have different values for odt on/off, retrieve the correct one and store in local variable
133 if (r2w_odt_onoff == ODT_ON) //odt_on
134 {
135 u2TRTW = ACTblFinal.tr2w_odt_on;
136 u2TRTW_05T = ACTblFinal.tr2w_odt_on_05T;
137 u2XRTW2R = ACTblFinal.xrtw2r_odt_on_otf_off;
138 u2XRTR2W = ACTblFinal.xrtr2w_odt_on;
139 }
140 else //odt_off
141 {
142 u2TRTW = ACTblFinal.tr2w_odt_off;
143 u2TRTW_05T = ACTblFinal.tr2w_odt_off_05T;
144 u2XRTW2R = ACTblFinal.xrtw2r_odt_off_otf_off;
145 u2XRTR2W = ACTblFinal.xrtr2w_odt_off;
146 }
147
148 // Override the above tRTW & tRTW_05T selection for Hynix LPDDR4P dram (always use odt_on's value for tRTW)
149 if ((p->dram_type == TYPE_LPDDR4P) && (p->vendor_id == VENDOR_HYNIX)) //!SUPPORT_HYNIX_RX_DQS_WEAK_PULL (temp solution, need to discuss with SY)
150 {
151 u2TRTW = ACTblFinal.tr2w_odt_on;
152 u2TRTW_05T = ACTblFinal.tr2w_odt_on_05T;
153 }
154
155 if (r2w_odt_onoff == ODT_ON)
156 {
157 u2XTRTRT = ACTblFinal.xrtr2r_odt_on;
158 u2XRTWTW = ACTblFinal.xrtw2w_odt_on;
159 }
160 else
161 {
162 u2XTRTRT = ACTblFinal.xrtr2r_odt_off;
163 u2XRTWTW = ACTblFinal.xrtw2w_odt_off;
164 }
165
166 #if ENABLE_RODT_TRACKING_SAVE_MCK
167 // for rodt tracking save 1 MCK and rodt tracking enable or not(RODTENSTB_TRACK_EN)
168 u1ODT_ON = p->odt_onoff;
169 u1RODT_TRACK = ENABLE_RODT_TRACKING;
170 u1ROEN = u1WDQS_ON | u1ODT_ON;
171 u1ModeSel = u1RODT_TRACK & u1ROEN;
172
173 // when WDQS on and RODT Track define open and un-term, RODT_TRACKING_SAVEING_MCK = 1 for the future setting
174 // Maybe "Save 1 MCK" will be set after Vins_on project, but Bian_co & Vins_on can not.(different with performance team)
175 //if (u1RODT_TRACK && (u1ROEN==1))
176 // RODT_TRACKING_SAVEING_MCK = 1;
177 #endif
178
179 #if (ENABLE_RODT_TRACKING || defined(XRTR2W_PERFORM_ENHANCE_RODTEN))
180 /* yr: same code
181 // set to 0, let TRTW & XRTR2W setting values are the smae with DV-sim's value that DE provided
182 if (r2w_odt_onoff == ODT_ON) RODT_TRACKING_SAVEING_MCK = 0; //RODT_TRACKING eanble can save r2w 1 MCK
183 else RODT_TRACKING_SAVEING_MCK = 0;
184 */
185 RODT_TRACKING_SAVEING_MCK = 0;
186 #endif
187
188 // Update values that are used by RODT_TRACKING_SAVEING_MCK
189 u2TRTW = u2TRTW - RODT_TRACKING_SAVEING_MCK;
190 u2XRTR2W = u2XRTR2W - RODT_TRACKING_SAVEING_MCK;
191
192 #if SAMSUNG_LP4_NWR_WORKAROUND
193 // If nWR is fixed to 30 for all freqs, tWTR@800Mhz should add 2tCK gap, allowing sufficient Samsung DRAM internal IO precharge time
194 if ((p->vendor_id == VENDOR_SAMSUNG) && (p->frequency == 800)) //LP4X, Samsung, DDR1600
195 {
196 u1TWTR_TMP = (ACTblFinal.twtr * 4 - ACTblFinal.twtr_05T * 2) + 2; //Convert TWTR to tCK, and add 2tCK
197 if ((u1TWTR_TMP % 4) == 0) //TWTR can be transferred to TWTR directly
198 {
199 u1TWTR = u1TWTR_TMP >> 2;
200 u1TWTR_05T = 0;
201 }
202 else //Can't be transfered to TWTR directly
203 {
204 u1TWTR = (u1TWTR_TMP + 2) >> 2; //Add 2 tCK and set TWTR value (Then minus 2tCK using 05T)
205 u1TWTR_05T = 1; //05T means minus 2tCK
206 }
207
208 ACTblFinal.twtr = u1TWTR;
209 ACTblFinal.twtr_05T = u1TWTR_05T;
210 }
211 #endif
212
213 //DATLAT related
214 if (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL), SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN))
215 u1DATLAT_DSEL = ACTblFinal.datlat;
216 else
217 u1DATLAT_DSEL = ACTblFinal.datlat - 1;
218
219 #if TX_OE_EXTEND
220 u2XRTWTW += 1;
221 u2XRTW2R += 1;
222 #endif
223
224 #if 0//(!CMD_CKE_WORKAROUND_FIX)
225 U8 u1Txp = 0, u1Txp0p5 = 0;
226
227 if (((p->frequency <= 1866) && (p->frequency >= 1600)) || ((vGet_Div_Mode(p) == DIV4_MODE) && (p->frequency == 400)))
228 {
229 u1Txp = 1;
230 }
231 else if ((p->frequency == 2133) || ((vGet_Div_Mode(p) == DIV4_MODE) && ((p->frequency <= 800) || (p->frequency >= 600))))
232 {
233 u1Txp = 2;
234 }
235
236 if ((p->frequency == 1866) || ((p->frequency <= 1333) && (p->frequency >= 1200)))
237 {
238 u1Txp0p5 = 1;
239 }
240
241 ACTblFinal.txp = u1Txp;
242 ACTblFinal.txp_05T = u1Txp0p5;
243 ACTblFinal.ckelckcnt = 4;
244 ACTblFinal.earlyckecnt = 0;
245 ACTblFinal.ckeprd -= 1;
246 #endif
247
248 // ----Step 2: Perform register writes for entries in ACTblFinal struct & ACTiming excel file (all actiming adjustments should be done in Step 1)-------
249
250 vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM1, P_Fld(ACTblFinal.tras, SHU_ACTIM1_TRAS)
251 | P_Fld(ACTblFinal.trp, SHU_ACTIM1_TRP)
252 | P_Fld(ACTblFinal.trpab, SHU_ACTIM1_TRPAB)
253 | P_Fld(ACTblFinal.tmrwckel, SHU_ACTIM1_TMRWCKEL)
254 | P_Fld(ACTblFinal.trc, SHU_ACTIM1_TRC));
255
256 vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM3, P_Fld(ACTblFinal.trfc, SHU_ACTIM3_TRFC)
257 | P_Fld(ACTblFinal.tr2mrr, SHU_ACTIM3_TR2MRR)
258 | P_Fld(ACTblFinal.trfcpb, SHU_ACTIM3_TRFCPB));
259
260 vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM2, P_Fld(ACTblFinal.txp, SHU_ACTIM2_TXP)
261 | P_Fld(ACTblFinal.tmrri, SHU_ACTIM2_TMRRI)
262 | P_Fld(ACTblFinal.tfaw, SHU_ACTIM2_TFAW)
263 | P_Fld(u2TRTW, SHU_ACTIM2_TR2W) // Value has odt_on/off difference, use local variable u1TRTW
264 | P_Fld(ACTblFinal.trtp, SHU_ACTIM2_TRTP));
265
266 vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM0, P_Fld(ACTblFinal.trcd, SHU_ACTIM0_TRCD)
267 | P_Fld(ACTblFinal.twr, SHU_ACTIM0_TWR)
268 | P_Fld(ACTblFinal.trrd, SHU_ACTIM0_TRRD));
269
270 vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM5, P_Fld(ACTblFinal.tpbr2pbr, SHU_ACTIM5_TPBR2PBR)
271 | P_Fld(ACTblFinal.twtpd, SHU_ACTIM5_TWTPD)
272 | P_Fld(ACTblFinal.tpbr2act, SHU_ACTIM5_TPBR2ACT));
273
274 vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM6, P_Fld(ACTblFinal.tr2mrw, SHU_ACTIM6_TR2MRW)
275 | P_Fld(ACTblFinal.tw2mrw, SHU_ACTIM6_TW2MRW)
276 | P_Fld(ACTblFinal.tmrd, SHU_ACTIM6_TMRD)
277 | P_Fld(ACTblFinal.zqlat2, SHU_ACTIM6_TZQLAT2)
278 | P_Fld(ACTblFinal.tmrw, SHU_ACTIM6_TMRW));
279
280 vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM4, P_Fld(ACTblFinal.tmrr2mrw, SHU_ACTIM4_TMRR2MRW)
281 | P_Fld(ACTblFinal.tmrr2w, SHU_ACTIM4_TMRR2W)
282 | P_Fld(ACTblFinal.tzqcs, SHU_ACTIM4_TZQCS)
283 | P_Fld(ACTblFinal.txrefcnt, SHU_ACTIM4_TXREFCNT));
284
285 vIO32WriteFldAlign_All(DRAMC_REG_SHU_CKECTRL, ACTblFinal.ckeprd, SHU_CKECTRL_TCKEPRD);
286
287 vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(u2XRTWTW, SHU_ACTIM_XRT_XRTW2W)
288 | P_Fld(u2XRTW2R, SHU_ACTIM_XRT_XRTW2R)
289 | P_Fld(u2XRTR2W, SHU_ACTIM_XRT_XRTR2W)
290 | P_Fld(u2XTRTRT, SHU_ACTIM_XRT_XRTR2R));
291
292 vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_VRCG, ACTblFinal.vrcgdis_prdcnt, SHU_HWSET_VRCG_VRCGDIS_PRDCNT);
293 // vIO32WriteFldMulti_All(DRAMC_REG_SHU_HWSET_VRCG, P_Fld(ACTblFinal.vrcgdis_prdcnt, SHU_HWSET_VRCG_VRCGDIS_PRDCNT)
294 // | P_Fld(ACTblFinal.hwset_vrcg_op, SHU_HWSET_VRCG_HWSET_VRCG_OP));
295 vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_MR2, ACTblFinal.hwset_mr2_op, SHU_HWSET_MR2_HWSET_MR2_OP);
296 vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_MR13, ACTblFinal.hwset_mr13_op, SHU_HWSET_MR13_HWSET_MR13_OP);
297
298 // AC timing 0.5T
299 vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(ACTblFinal.twtr_05T, SHU_AC_TIME_05T_TWTR_M05T)
300 | P_Fld(ACTblFinal.twtr_l_05T, SHU_AC_TIME_05T_BGTWTR_M05T)
301 | P_Fld(u2TRTW_05T, SHU_AC_TIME_05T_TR2W_05T) // Value has odt_on/off difference, use local variable u1TRTW
302 | P_Fld(ACTblFinal.twtpd_05T, SHU_AC_TIME_05T_TWTPD_M05T)
303 | P_Fld(ACTblFinal.tfaw_05T, SHU_AC_TIME_05T_TFAW_05T)
304 | P_Fld(ACTblFinal.trrd_05T, SHU_AC_TIME_05T_TRRD_05T)
305 | P_Fld(ACTblFinal.twr_05T, SHU_AC_TIME_05T_TWR_M05T)
306 | P_Fld(ACTblFinal.tras_05T, SHU_AC_TIME_05T_TRAS_05T)
307 | P_Fld(ACTblFinal.trpab_05T, SHU_AC_TIME_05T_TRPAB_05T)
308 | P_Fld(ACTblFinal.trp_05T, SHU_AC_TIME_05T_TRP_05T)
309 | P_Fld(ACTblFinal.trcd_05T, SHU_AC_TIME_05T_TRCD_05T)
310 | P_Fld(ACTblFinal.trtp_05T, SHU_AC_TIME_05T_TRTP_05T)
311 | P_Fld(ACTblFinal.txp_05T, SHU_AC_TIME_05T_TXP_05T)
312 | P_Fld(ACTblFinal.trfc_05T, SHU_AC_TIME_05T_TRFC_05T)
313 | P_Fld(ACTblFinal.trfcpb_05T, SHU_AC_TIME_05T_TRFCPB_05T)
314 | P_Fld(ACTblFinal.tpbr2pbr_05T, SHU_AC_TIME_05T_TPBR2PBR_05T)
315 | P_Fld(ACTblFinal.tpbr2act_05T, SHU_AC_TIME_05T_TPBR2ACT_05T)
316 | P_Fld(ACTblFinal.tr2mrw_05T, SHU_AC_TIME_05T_TR2MRW_05T)
317 | P_Fld(ACTblFinal.tw2mrw_05T, SHU_AC_TIME_05T_TW2MRW_05T)
318 | P_Fld(ACTblFinal.tmrr2mrw_05T, SHU_AC_TIME_05T_TMRR2MRW_05T)
319 | P_Fld(ACTblFinal.tmrw_05T, SHU_AC_TIME_05T_TMRW_05T)
320 | P_Fld(ACTblFinal.tmrd_05T, SHU_AC_TIME_05T_TMRD_05T)
321 | P_Fld(ACTblFinal.tmrwckel_05T, SHU_AC_TIME_05T_TMRWCKEL_05T)
322 | P_Fld(ACTblFinal.tmrri_05T, SHU_AC_TIME_05T_TMRRI_05T)
323 | P_Fld(ACTblFinal.trc_05T, SHU_AC_TIME_05T_TRC_05T));
324
325 {
326 vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM0, ACTblFinal.twtr_l, SHU_ACTIM0_TWTR_L);
327 vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM7, P_Fld(ACTblFinal.tcsh_cscal, SHU_ACTIM7_TCSH_CSCAL)
328 | P_Fld(ACTblFinal.tcacsh, SHU_ACTIM7_TCACSH));
329 }
330 {
331 vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM0, ACTblFinal.twtr, SHU_ACTIM0_TWTR);
332 vIO32WriteFldMulti_All(DRAMC_REG_SHU_CKECTRL, P_Fld(ACTblFinal.tpde, SHU_CKECTRL_TPDE)
333 | P_Fld(ACTblFinal.tpdx, SHU_CKECTRL_TPDX)
334 | P_Fld(ACTblFinal.tpde_05T, SHU_CKECTRL_TPDE_05T)
335 | P_Fld(ACTblFinal.tpdx_05T, SHU_CKECTRL_TPDX_05T));
336 vIO32WriteFldMulti_All(DRAMC_REG_SHU_WCKCTRL, P_Fld(ACTblFinal.wckrdoff, SHU_WCKCTRL_WCKRDOFF)
337 | P_Fld(ACTblFinal.wckrdoff_05T, SHU_WCKCTRL_WCKRDOFF_05T)
338 | P_Fld(ACTblFinal.wckwroff, SHU_WCKCTRL_WCKWROFF)
339 | P_Fld(ACTblFinal.wckwroff_05T, SHU_WCKCTRL_WCKWROFF_05T));
340 vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM5, ACTblFinal.trtpd, SHU_ACTIM5_TR2PD);
341 vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_TIME_05T, ACTblFinal.trtpd_05T, SHU_AC_TIME_05T_TR2PD_05T);
342 vIO32WriteFldAlign_All(DRAMC_REG_SHU_LP5_CMD, ACTblFinal.tcsh, SHU_LP5_CMD_TCSH);
343 }
344
345 #if AC_TIMING_DERATE_ENABLE
346 if (u1IsLP4Family(p->dram_type))
347 {
348 vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING0, P_Fld(ACTblFinal.trcd_derate, SHU_AC_DERATING0_TRCD_DERATE)
349 | P_Fld(ACTblFinal.trrd_derate, SHU_AC_DERATING0_TRRD_DERATE));
350 vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING1, P_Fld(ACTblFinal.trc_derate, SHU_AC_DERATING1_TRC_DERATE)
351 | P_Fld(ACTblFinal.tras_derate, SHU_AC_DERATING1_TRAS_DERATE)
352 | P_Fld(ACTblFinal.trp_derate, SHU_AC_DERATING1_TRP_DERATE)
353 | P_Fld(ACTblFinal.trpab_derate, SHU_AC_DERATING1_TRPAB_DERATE));
354 vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING_05T, P_Fld(ACTblFinal.trrd_05T_derate, SHU_AC_DERATING_05T_TRRD_05T_DERATE)
355 | P_Fld(ACTblFinal.tras_05T_derate, SHU_AC_DERATING_05T_TRAS_05T_DERATE)
356 | P_Fld(ACTblFinal.trpab_05T_derate, SHU_AC_DERATING_05T_TRPAB_05T_DERATE)
357 | P_Fld(ACTblFinal.trp_05T_derate, SHU_AC_DERATING_05T_TRP_05T_DERATE)
358 | P_Fld(ACTblFinal.trcd_05T_derate, SHU_AC_DERATING_05T_TRCD_05T_DERATE)
359 | P_Fld(ACTblFinal.trc_05T_derate, SHU_AC_DERATING_05T_TRC_05T_DERATE));
360 vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL3, 0xc0, REFCTRL3_REF_DERATING_EN);
361 vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_DERATING0, 0x1, SHU_AC_DERATING0_ACDERATEEN); //enable derating for AC timing
362 }
363 #endif
364
365 // DQSINCTL related
366 vSetRank(p, RANK_0);
367 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RK_DQSCTL, ACTblFinal.dqsinctl, MISC_SHU_RK_DQSCTL_DQSINCTL);// Rank 0 DQSINCTL
368 vSetRank(p, RANK_1);
369 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RK_DQSCTL, ACTblFinal.dqsinctl, MISC_SHU_RK_DQSCTL_DQSINCTL);// Rank 1 DQSINCTL
370 vSetRank(p, backup_rank);
371 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_ODTCTRL, ACTblFinal.dqsinctl, MISC_SHU_ODTCTRL_RODT_LAT);
372
373 if (ACTblFinal.dqsinctl >= 2)
374 {
375 u4RankINCTL_ROOT = ACTblFinal.dqsinctl - 2;
376 }
377 else
378 {
379 err("u4RankINCTL_ROOT <2, Please check\n");
380 u4RankINCTL_ROOT = 0;
381 }
382
383 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(ACTblFinal.dqsinctl, MISC_SHU_RANKCTL_RANKINCTL_PHY)
384 | P_Fld(u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL_ROOT1)
385 | P_Fld(u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL));
386
387 #if XRTRTR_NEW_CROSS_RK_MODE
388 u2PHSINCTL = (ACTblFinal.dqsinctl == 0)? 0: (ACTblFinal.dqsinctl - 1);
389 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, u2PHSINCTL, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL);
390 #endif
391
392 // DATLAT related, tREFBW
393 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(ACTblFinal.datlat, MISC_SHU_RDAT_DATLAT)
394 | P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL)
395 | P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
396
397 vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIMING_CONF, u1TREFBW, SHU_ACTIMING_CONF_REFBW_FR);
398
399 // ----Step 3: Perform register writes/calculation for other regs (That aren't in ACTblFinal struct)------------------------------------------------
400 #ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
401 //Wei-Jen: Ininital setting values are the same, RANKINCTL_RXDLY = RANKINCTL = RANKINCTL_ROOT1
402 //XRTR2R setting will be updated in RxdqsGatingPostProcess
403 u1RANKINCTL = u4IO32ReadFldAlign(DDRPHY_REG_MISC_SHU_RANKCTL, MISC_SHU_RANKCTL_RANKINCTL);
404 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RANKCTL, u1RANKINCTL, MISC_SHU_RANKCTL_RANKINCTL_RXDLY);
405 #endif
406
407 //Update releated RG of XRTW2W
408 if (p->frequency <= 800)
409 {
410 if (vGet_Div_Mode(p) == DIV4_MODE)
411 {
412 u1ROOT = 0; u1TXRANKINCTL = 1; u1TXDLY = 2;
413 }
414 else
415 {
416 u1ROOT = 0; u1TXRANKINCTL = 0; u1TXDLY = 1;
417 }
418 }
419 else
420 {
421 u1ROOT = (p->frequency == 1866)? 1: 0;
422 u1TXRANKINCTL = 1; u1TXDLY = 2;
423 }
424 #if TX_OE_EXTEND
425 if (p->frequency >= 1333)
426 {
427 u1TXRANKINCTL += 1;
428 u1TXDLY += 1;
429 }
430 #endif
431
432 vIO32WriteFldMulti_All(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(u1ROOT, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)
433 | P_Fld(u1TXRANKINCTL, SHU_TX_RANKCTL_TXRANKINCTL)
434 | P_Fld(u1TXDLY, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY));
435
436 return DRAM_OK;
437 }
438 #endif
439
440 #if ENABLE_WDQS_MODE_2
WDQSMode2AcTimingEnlarge(DRAMC_CTX_T * p,U16 * u2_XRTW2W,U16 * u2_XRTR2W,U16 * u2_XRTW2R,U16 * u2_TRTW)441 static void WDQSMode2AcTimingEnlarge(DRAMC_CTX_T *p, U16 *u2_XRTW2W, U16 *u2_XRTR2W, U16 *u2_XRTW2R, U16 *u2_TRTW)
442 {
443 U16 u2XRTW2W_enlarge = 0, u2XRTR2W_enlarge = 0;
444 U16 u2XRTW2R_enlarge = 0, u2TRTW_enlarge = 0;
445
446 switch (p->frequency)
447 {
448 case 1866:
449 u2XRTW2W_enlarge = 3;
450 break;
451 case 1600:
452 u2XRTW2W_enlarge = 2;
453 u2XRTR2W_enlarge = 1;
454 break;
455 case 1200:
456 u2XRTW2W_enlarge = 2;
457 if (vGet_Dram_CBT_Mode(p) == CBT_BYTE_MODE1)
458 u2XRTR2W_enlarge = 1;
459 break;
460 case 933:
461 u2XRTW2W_enlarge = 1;
462 if (vGet_Dram_CBT_Mode(p) == CBT_NORMAL_MODE)
463 u2XRTR2W_enlarge = 1;
464 break;
465 case 800:
466 u2XRTW2W_enlarge = 2;
467 u2TRTW_enlarge = 1;
468 if (vGet_Dram_CBT_Mode(p) == CBT_NORMAL_MODE)
469 u2XRTW2R_enlarge = 1;
470 break;
471 case 600:
472 u2XRTW2W_enlarge = 2;
473 u2TRTW_enlarge = 1;
474 if (vGet_Dram_CBT_Mode(p) == CBT_NORMAL_MODE)
475 u2XRTW2R_enlarge = 1;
476 break;
477 case 400:
478 u2XRTW2W_enlarge = 3;
479 u2TRTW_enlarge = 2;
480 u2XRTR2W_enlarge = 1;
481 break;
482 default:
483 err("[WDQSMode2AcTimingEnlarge] frequency err!\n");
484 #if __ETT__
485 while (1);
486 #endif
487 }
488
489 *u2_XRTW2W += u2XRTW2W_enlarge;
490 *u2_XRTR2W += u2XRTR2W_enlarge;
491 *u2_XRTW2R += u2XRTW2R_enlarge;
492 *u2_TRTW += u2TRTW_enlarge;
493 }
494 #endif
495
DdrUpdateACTimingReg_LP4(DRAMC_CTX_T * p,const ACTime_T_LP4 * ACTbl)496 static DRAM_STATUS_T DdrUpdateACTimingReg_LP4(DRAMC_CTX_T *p, const ACTime_T_LP4 *ACTbl)
497 {
498 ACTime_T_LP4 ACTblFinal;
499 U8 backup_rank = p->rank;
500 DRAM_ODT_MODE_T r2w_odt_onoff = p->odt_onoff; //Variable used in step 1 (decide to use odt on or off ACTiming)
501 // ACTiming regs that have ODT on/off values -> declare variables to save the wanted value
502 // -> Used to retrieve correct SHU_ACTIM2_TR2W value and write into final register field
503 #ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
504 U8 u1RANKINCTL = 0;
505 #endif
506 U8 RODT_TRACKING_SAVEING_MCK = 0, u1ROOT = 0, u1TXRANKINCTL = 0, u1TXDLY = 0, u1DATLAT_DSEL = 0; //Used to store tmp ACTiming values
507
508 #if SAMSUNG_LP4_NWR_WORKAROUND
509 U8 u1TWTR = 0, u1TWTR_05T = 0, u1TWTR_TMP = 0;
510 #endif
511 // ACTiming regs that aren't currently in ACTime_T struct
512 U8 u1TREFBW = 0; //REFBW_FR (tREFBW) for LP3, REFBW_FR=0 & TREFBWIG=1 (by CF)
513 U8 u1TFAW_05T=0, u1TRRD_05T=0;
514 U16 u2XRTWTW = 0, u2XTRTRT = 0, u2XRTW2R = 0, u2XRTR2W = 0, u2TFAW = 0;
515 U16 u2TRTW=0, u2TRTW_05T=0, u2TMRR2W=0, u2TRRD=0;
516
517 #if XRTRTR_NEW_CROSS_RK_MODE
518 U16 u2PHSINCTL = 0;
519 #endif
520
521 U32 u4RankINCTL_ROOT;
522
523 if(ACTbl == NULL)
524 return DRAM_FAIL;
525 ACTblFinal = *ACTbl;
526
527 // ----Step 1: Perform ACTiming table adjustments according to different usage/scenarios--------------------------
528 #if ENABLE_TX_WDQS
529 r2w_odt_onoff = ODT_ON;
530 #else
531 r2w_odt_onoff = p->odt_onoff;
532 #endif
533 // ACTimings that have different values for odt on/off, retrieve the correct one and store in local variable
534 if (r2w_odt_onoff == ODT_ON) //odt_on
535 {
536 u2TRTW = ACTblFinal.trtw_odt_on;
537 u2TRTW_05T = ACTblFinal.trtw_odt_on_05T;
538 u2XRTW2R = ACTblFinal.xrtw2r_odt_on;
539 u2XRTR2W = ACTblFinal.xrtr2w_odt_on;
540 }
541 else //odt_off
542 {
543 u2TRTW = ACTblFinal.trtw_odt_off;
544 u2TRTW_05T = ACTblFinal.trtw_odt_off_05T;
545 u2XRTW2R = ACTblFinal.xrtw2r_odt_off;
546 u2XRTR2W = ACTblFinal.xrtr2w_odt_off;
547 }
548
549 // Override the above tRTW & tRTW_05T selection for Hynix LPDDR4P dram (always use odt_on's value for tRTW)
550 if ((p->dram_type == TYPE_LPDDR4P) && (p->vendor_id == VENDOR_HYNIX)) //!SUPPORT_HYNIX_RX_DQS_WEAK_PULL (temp solution, need to discuss with SY)
551 {
552 u2TRTW = ACTblFinal.trtw_odt_on;
553 u2TRTW_05T = ACTblFinal.trtw_odt_on_05T;
554 }
555
556 {
557 u2TFAW = ACTblFinal.tfaw_4266;
558 u1TFAW_05T = ACTblFinal.tfaw_4266_05T;
559 u2TRRD = ACTblFinal.trrd_4266;
560 u1TRRD_05T = ACTblFinal.trrd_4266_05T;
561 #if XRTRTR_NEW_CROSS_RK_MODE
562 u2XTRTRT = ACTblFinal.xrtr2r_new_mode;
563 #else
564 u2XTRTRT = ACTblFinal.xrtr2r_old_mode;
565 #endif
566
567 #if XRTWTW_NEW_CROSS_RK_MODE
568 u2XRTWTW = ACTblFinal.xrtw2w_new_mode;
569 #else
570 u2XRTWTW = ACTblFinal.xrtw2w_old_mode;
571 #endif
572
573 #if ENABLE_WDQS_MODE_2
574 WDQSMode2AcTimingEnlarge(p, &u2XRTWTW, &u2XRTR2W, &u2XRTW2R, &u2TRTW);
575 #endif
576
577 if (r2w_odt_onoff == ODT_ON)
578 u2TMRR2W = ACTblFinal.tmrr2w_odt_on;
579 else
580 u2TMRR2W = ACTblFinal.tmrr2w_odt_off;
581 }
582
583 #if ENABLE_RODT_TRACKING_SAVE_MCK
584 // for rodt tracking save 1 MCK and rodt tracking enable or not(RODTENSTB_TRACK_EN)
585 u1ODT_ON = p->odt_onoff;
586 u1RODT_TRACK = ENABLE_RODT_TRACKING;
587 u1ROEN = u1WDQS_ON | u1ODT_ON;
588 u1ModeSel = u1RODT_TRACK & u1ROEN;
589
590 // when WDQS on and RODT Track define open and un-term, RODT_TRACKING_SAVEING_MCK = 1 for the future setting
591 // Maybe "Save 1 MCK" will be set after Vins_on project, but Bian_co & Vins_on can not.(different with performance team)
592 //if (u1RODT_TRACK && (u1ROEN==1))
593 // RODT_TRACKING_SAVEING_MCK = 1;
594 #endif
595
596 #if (ENABLE_RODT_TRACKING || defined(XRTR2W_PERFORM_ENHANCE_RODTEN))
597 /* yr: same code
598 // set to 0, let TRTW & XRTR2W setting values are the smae with DV-sim's value that DE provided
599 if (r2w_odt_onoff == ODT_ON) RODT_TRACKING_SAVEING_MCK = 0; //RODT_TRACKING eanble can save r2w 1 MCK
600 else RODT_TRACKING_SAVEING_MCK = 0;
601 */
602 RODT_TRACKING_SAVEING_MCK = 0;
603 #endif
604
605 // Update values that are used by RODT_TRACKING_SAVEING_MCK
606 u2TRTW = u2TRTW - RODT_TRACKING_SAVEING_MCK;
607 u2XRTR2W = u2XRTR2W - RODT_TRACKING_SAVEING_MCK;
608
609 #if SAMSUNG_LP4_NWR_WORKAROUND
610 // If nWR is fixed to 30 for all freqs, tWTR@800Mhz should add 2tCK gap, allowing sufficient Samsung DRAM internal IO precharge time
611 if ((p->vendor_id == VENDOR_SAMSUNG) && (p->frequency == 800)) //LP4X, Samsung, DDR1600
612 {
613 u1TWTR_TMP = (ACTblFinal.twtr * 4 - ACTblFinal.twtr_05T * 2) + 2; //Convert TWTR to tCK, and add 2tCK
614 if ((u1TWTR_TMP % 4) == 0) //TWTR can be transferred to TWTR directly
615 {
616 u1TWTR = u1TWTR_TMP >> 2;
617 u1TWTR_05T = 0;
618 }
619 else //Can't be transfered to TWTR directly
620 {
621 u1TWTR = (u1TWTR_TMP + 2) >> 2; //Add 2 tCK and set TWTR value (Then minus 2tCK using 05T)
622 u1TWTR_05T = 1; //05T means minus 2tCK
623 }
624
625 ACTblFinal.twtr = u1TWTR;
626 ACTblFinal.twtr_05T = u1TWTR_05T;
627 }
628 #endif
629
630 //DATLAT related
631 if (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RX_PIPE_CTRL), SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN))
632 u1DATLAT_DSEL = ACTblFinal.datlat;
633 else
634 u1DATLAT_DSEL = ACTblFinal.datlat - 1;
635
636 #if TX_OE_EXTEND
637 u2XRTWTW += 1;
638 u2XRTW2R += 1;
639 #endif
640
641 #if 0//(!CMD_CKE_WORKAROUND_FIX)
642 U8 u1Txp = 0, u1Txp0p5 = 0;
643
644 if (((p->frequency <= 1866) && (p->frequency >= 1600)) || ((vGet_Div_Mode(p) == DIV4_MODE) && (p->frequency == 400)))
645 {
646 u1Txp = 1;
647 }
648 else if ((p->frequency == 2133) || ((vGet_Div_Mode(p) == DIV4_MODE) && ((p->frequency <= 800) || (p->frequency >= 600))))
649 {
650 u1Txp = 2;
651 }
652
653 if ((p->frequency == 1866) || ((p->frequency <= 1333) && (p->frequency >= 1200)))
654 {
655 u1Txp0p5 = 1;
656 }
657
658 ACTblFinal.txp = u1Txp;
659 ACTblFinal.txp_05T = u1Txp0p5;
660 ACTblFinal.ckelckcnt = 4;
661 ACTblFinal.earlyckecnt = 0;
662 ACTblFinal.ckeprd -= 1;
663 #endif
664
665 // ----Step 2: Perform register writes for entries in ACTblFinal struct & ACTiming excel file (all actiming adjustments should be done in Step 1)-------
666
667 vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM1, P_Fld(ACTblFinal.tras, SHU_ACTIM1_TRAS)
668 | P_Fld(ACTblFinal.trp, SHU_ACTIM1_TRP)
669 | P_Fld(ACTblFinal.trpab, SHU_ACTIM1_TRPAB)
670 | P_Fld(ACTblFinal.tmrwckel, SHU_ACTIM1_TMRWCKEL)
671 | P_Fld(ACTblFinal.trc, SHU_ACTIM1_TRC));
672
673 vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM3, P_Fld(ACTblFinal.trfc, SHU_ACTIM3_TRFC)
674 | P_Fld(ACTblFinal.tr2mrr, SHU_ACTIM3_TR2MRR)
675 | P_Fld(ACTblFinal.trfcpb, SHU_ACTIM3_TRFCPB));
676
677 vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM2, P_Fld(ACTblFinal.txp, SHU_ACTIM2_TXP)
678 | P_Fld(ACTblFinal.tmrri, SHU_ACTIM2_TMRRI)
679 | P_Fld(u2TFAW, SHU_ACTIM2_TFAW)
680 | P_Fld(u2TRTW, SHU_ACTIM2_TR2W) // Value has odt_on/off difference, use local variable u1TRTW
681 | P_Fld(ACTblFinal.trtp, SHU_ACTIM2_TRTP));
682
683 vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM0, P_Fld(ACTblFinal.trcd, SHU_ACTIM0_TRCD)
684 | P_Fld(ACTblFinal.twr, SHU_ACTIM0_TWR)
685 | P_Fld(u2TRRD, SHU_ACTIM0_TRRD));
686
687 vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM5, P_Fld(ACTblFinal.tpbr2pbr, SHU_ACTIM5_TPBR2PBR)
688 | P_Fld(ACTblFinal.twtpd, SHU_ACTIM5_TWTPD)
689 | P_Fld(ACTblFinal.tpbr2act, SHU_ACTIM5_TPBR2ACT));
690
691 vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM6, P_Fld(ACTblFinal.tr2mrw, SHU_ACTIM6_TR2MRW)
692 | P_Fld(ACTblFinal.tw2mrw, SHU_ACTIM6_TW2MRW)
693 | P_Fld(ACTblFinal.tmrd, SHU_ACTIM6_TMRD)
694 | P_Fld(ACTblFinal.zqlat2, SHU_ACTIM6_TZQLAT2)
695 | P_Fld(ACTblFinal.tmrw, SHU_ACTIM6_TMRW));
696
697 vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM4, P_Fld(ACTblFinal.tmrr2mrw, SHU_ACTIM4_TMRR2MRW)
698 | P_Fld(u2TMRR2W, SHU_ACTIM4_TMRR2W)
699 | P_Fld(ACTblFinal.tzqcs, SHU_ACTIM4_TZQCS)
700 | P_Fld(ACTblFinal.txrefcnt, SHU_ACTIM4_TXREFCNT));
701
702 vIO32WriteFldAlign_All(DRAMC_REG_SHU_CKECTRL, ACTblFinal.ckeprd, SHU_CKECTRL_TCKEPRD);
703
704 vIO32WriteFldMulti_All(DRAMC_REG_SHU_ACTIM_XRT, P_Fld(u2XRTWTW, SHU_ACTIM_XRT_XRTW2W)
705 | P_Fld(u2XRTW2R, SHU_ACTIM_XRT_XRTW2R)
706 | P_Fld(u2XRTR2W, SHU_ACTIM_XRT_XRTR2W)
707 | P_Fld(u2XTRTRT, SHU_ACTIM_XRT_XRTR2R));
708
709 vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_VRCG, ACTblFinal.vrcgdis_prdcnt, SHU_HWSET_VRCG_VRCGDIS_PRDCNT);
710 // vIO32WriteFldMulti_All(DRAMC_REG_SHU_HWSET_VRCG, P_Fld(ACTblFinal.vrcgdis_prdcnt, SHU_HWSET_VRCG_VRCGDIS_PRDCNT)
711 // | P_Fld(ACTblFinal.hwset_vrcg_op, SHU_HWSET_VRCG_HWSET_VRCG_OP));
712 vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_MR2, ACTblFinal.hwset_mr2_op, SHU_HWSET_MR2_HWSET_MR2_OP);
713 vIO32WriteFldAlign_All(DRAMC_REG_SHU_HWSET_MR13, ACTblFinal.hwset_mr13_op, SHU_HWSET_MR13_HWSET_MR13_OP);
714
715 // AC timing 0.5T
716 vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_TIME_05T, P_Fld(ACTblFinal.twtr_05T, SHU_AC_TIME_05T_TWTR_M05T)
717 | P_Fld(u2TRTW_05T, SHU_AC_TIME_05T_TR2W_05T) // Value has odt_on/off difference, use local variable u1TRTW
718 | P_Fld(ACTblFinal.twtpd_05T, SHU_AC_TIME_05T_TWTPD_M05T)
719 | P_Fld(u1TFAW_05T, SHU_AC_TIME_05T_TFAW_05T)
720 | P_Fld(u1TRRD_05T, SHU_AC_TIME_05T_TRRD_05T)
721 | P_Fld(ACTblFinal.twr_05T, SHU_AC_TIME_05T_TWR_M05T)
722 | P_Fld(ACTblFinal.tras_05T, SHU_AC_TIME_05T_TRAS_05T)
723 | P_Fld(ACTblFinal.trpab_05T, SHU_AC_TIME_05T_TRPAB_05T)
724 | P_Fld(ACTblFinal.trp_05T, SHU_AC_TIME_05T_TRP_05T)
725 | P_Fld(ACTblFinal.trcd_05T, SHU_AC_TIME_05T_TRCD_05T)
726 | P_Fld(ACTblFinal.trtp_05T, SHU_AC_TIME_05T_TRTP_05T)
727 | P_Fld(ACTblFinal.txp_05T, SHU_AC_TIME_05T_TXP_05T)
728 | P_Fld(ACTblFinal.trfc_05T, SHU_AC_TIME_05T_TRFC_05T)
729 | P_Fld(ACTblFinal.trfcpb_05T, SHU_AC_TIME_05T_TRFCPB_05T)
730 | P_Fld(ACTblFinal.tpbr2pbr_05T, SHU_AC_TIME_05T_TPBR2PBR_05T)
731 | P_Fld(ACTblFinal.tpbr2act_05T, SHU_AC_TIME_05T_TPBR2ACT_05T)
732 | P_Fld(ACTblFinal.tr2mrw_05T, SHU_AC_TIME_05T_TR2MRW_05T)
733 | P_Fld(ACTblFinal.tw2mrw_05T, SHU_AC_TIME_05T_TW2MRW_05T)
734 | P_Fld(ACTblFinal.tmrr2mrw_05T, SHU_AC_TIME_05T_TMRR2MRW_05T)
735 | P_Fld(ACTblFinal.tmrw_05T, SHU_AC_TIME_05T_TMRW_05T)
736 | P_Fld(ACTblFinal.tmrd_05T, SHU_AC_TIME_05T_TMRD_05T)
737 | P_Fld(ACTblFinal.tmrwckel_05T, SHU_AC_TIME_05T_TMRWCKEL_05T)
738 | P_Fld(ACTblFinal.tmrri_05T, SHU_AC_TIME_05T_TMRRI_05T)
739 | P_Fld(ACTblFinal.trc_05T, SHU_AC_TIME_05T_TRC_05T));
740
741 {
742 vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM0, ACTblFinal.twtr, SHU_ACTIM0_TWTR);
743 vIO32WriteFldMulti_All(DRAMC_REG_SHU_CKECTRL, P_Fld(ACTblFinal.tpde, SHU_CKECTRL_TPDE)
744 | P_Fld(ACTblFinal.tpdx, SHU_CKECTRL_TPDX)
745 | P_Fld(ACTblFinal.tpde_05T, SHU_CKECTRL_TPDE_05T)
746 | P_Fld(ACTblFinal.tpdx_05T, SHU_CKECTRL_TPDX_05T));
747 vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM5, ACTblFinal.trtpd, SHU_ACTIM5_TR2PD);
748 vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_TIME_05T, ACTblFinal.trtpd_05T, SHU_AC_TIME_05T_TR2PD_05T);
749 }
750
751 #if AC_TIMING_DERATE_ENABLE
752 if (u1IsLP4Family(p->dram_type))
753 {
754 vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING0, P_Fld(ACTblFinal.trcd_derate, SHU_AC_DERATING0_TRCD_DERATE)
755 | P_Fld(ACTblFinal.trrd_derate, SHU_AC_DERATING0_TRRD_DERATE));
756 vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING1, P_Fld(ACTblFinal.trc_derate, SHU_AC_DERATING1_TRC_DERATE)
757 | P_Fld(ACTblFinal.tras_derate, SHU_AC_DERATING1_TRAS_DERATE)
758 | P_Fld(ACTblFinal.trp_derate, SHU_AC_DERATING1_TRP_DERATE)
759 | P_Fld(ACTblFinal.trpab_derate, SHU_AC_DERATING1_TRPAB_DERATE));
760 vIO32WriteFldMulti_All(DRAMC_REG_SHU_AC_DERATING_05T, P_Fld(ACTblFinal.trrd_derate_05T, SHU_AC_DERATING_05T_TRRD_05T_DERATE)
761 | P_Fld(ACTblFinal.tras_derate_05T, SHU_AC_DERATING_05T_TRAS_05T_DERATE)
762 | P_Fld(ACTblFinal.trpab_derate_05T, SHU_AC_DERATING_05T_TRPAB_05T_DERATE)
763 | P_Fld(ACTblFinal.trp_derate_05T, SHU_AC_DERATING_05T_TRP_05T_DERATE)
764 | P_Fld(ACTblFinal.trcd_derate_05T, SHU_AC_DERATING_05T_TRCD_05T_DERATE)
765 | P_Fld(ACTblFinal.trc_derate_05T, SHU_AC_DERATING_05T_TRC_05T_DERATE));
766 vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL3, 0xc0, REFCTRL3_REF_DERATING_EN);
767 vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_DERATING0, 0x1, SHU_AC_DERATING0_ACDERATEEN); //enable derating for AC timing
768 }
769 #endif
770
771 // DQSINCTL related
772 vSetRank(p, RANK_0);
773 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RK_DQSCTL, ACTblFinal.dqsinctl, MISC_SHU_RK_DQSCTL_DQSINCTL);// Rank 0 DQSINCTL
774 vSetRank(p, RANK_1);
775 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RK_DQSCTL, ACTblFinal.dqsinctl, MISC_SHU_RK_DQSCTL_DQSINCTL);// Rank 1 DQSINCTL
776 vSetRank(p, backup_rank);
777 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_ODTCTRL, ACTblFinal.dqsinctl, MISC_SHU_ODTCTRL_RODT_LAT);
778
779 if (ACTblFinal.dqsinctl >= 2)
780 {
781 u4RankINCTL_ROOT = ACTblFinal.dqsinctl - 2;
782 }
783 else
784 {
785 err("u4RankINCTL_ROOT <2, Please check\n");
786 u4RankINCTL_ROOT = 0;
787 }
788
789 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RANKCTL, P_Fld(ACTblFinal.dqsinctl, MISC_SHU_RANKCTL_RANKINCTL_PHY)
790 | P_Fld(u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL_ROOT1)
791 | P_Fld(u4RankINCTL_ROOT, MISC_SHU_RANKCTL_RANKINCTL));
792
793 #if XRTRTR_NEW_CROSS_RK_MODE
794 u2PHSINCTL = (ACTblFinal.dqsinctl == 0)? 0: (ACTblFinal.dqsinctl - 1);
795 vIO32WriteFldAlign_All(DDRPHY_REG_SHU_MISC_RANK_SEL_STB, u2PHSINCTL, SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL);
796 #endif
797
798 // DATLAT related, tREFBW
799 vIO32WriteFldMulti_All(DDRPHY_REG_MISC_SHU_RDAT, P_Fld(ACTblFinal.datlat, MISC_SHU_RDAT_DATLAT)
800 | P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL)
801 | P_Fld(u1DATLAT_DSEL, MISC_SHU_RDAT_DATLAT_DSEL_PHY));
802
803 vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIMING_CONF, u1TREFBW, SHU_ACTIMING_CONF_REFBW_FR);
804
805 // ----Step 3: Perform register writes/calculation for other regs (That aren't in ACTblFinal struct)------------------------------------------------
806 #ifdef XRTR2R_PERFORM_ENHANCE_DQSG_RX_DLY
807 //Wei-Jen: Ininital setting values are the same, RANKINCTL_RXDLY = RANKINCTL = RANKINCTL_ROOT1
808 //XRTR2R setting will be updated in RxdqsGatingPostProcess
809 u1RANKINCTL = u4IO32ReadFldAlign(DDRPHY_REG_MISC_SHU_RANKCTL, MISC_SHU_RANKCTL_RANKINCTL);
810 vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SHU_RANKCTL, u1RANKINCTL, MISC_SHU_RANKCTL_RANKINCTL_RXDLY);
811 #endif
812
813 //Update releated RG of XRTW2W
814 if (p->frequency <= 800)
815 {
816 if (vGet_Div_Mode(p) == DIV4_MODE)
817 {
818 u1ROOT = 0; u1TXRANKINCTL = 1; u1TXDLY = 2;
819 }
820 else
821 {
822 u1ROOT = 0; u1TXRANKINCTL = 0; u1TXDLY = 1;
823 }
824 }
825 else
826 {
827 u1ROOT = (p->frequency == 1866)? 1: 0;
828 u1TXRANKINCTL = 1; u1TXDLY = 2;
829 }
830 #if TX_OE_EXTEND
831 if (p->frequency >= 1333)
832 {
833 u1TXRANKINCTL += 1;
834 u1TXDLY += 1;
835 }
836 #endif
837
838 vIO32WriteFldMulti_All(DRAMC_REG_SHU_TX_RANKCTL, P_Fld(u1ROOT, SHU_TX_RANKCTL_TXRANKINCTL_ROOT)
839 | P_Fld(u1TXRANKINCTL, SHU_TX_RANKCTL_TXRANKINCTL)
840 | P_Fld(u1TXDLY, SHU_TX_RANKCTL_TXRANKINCTL_TXDLY));
841
842 return DRAM_OK;
843 }
844
845
DdrUpdateACTiming(DRAMC_CTX_T * p)846 DRAM_STATUS_T DdrUpdateACTiming(DRAMC_CTX_T *p)
847 {
848 U8 u1TimingIdx = 0;
849
850 msg3("[UpdateACTiming]\n");
851
852 //Retrieve ACTimingTable's corresponding index
853 u1TimingIdx = u1GetACTimingIdx(p);
854
855 if (u1TimingIdx == 0xff)
856 {
857 #if 0
858 if (u1TmpDramType = TYPE_LPDDR4)
859 u1TimingIdx = 0;
860 else // LPDDR3
861 u1TimingIdx = 6;
862 err("Error, no match AC timing, use default timing %d\n", u1TimingIdx);
863 #else
864 err("Error, no match AC timing, not apply table\n");
865 return DRAM_FAIL;
866 #endif
867 }
868
869 //Set ACTiming registers
870 #if (__LP5_COMBO__ == TRUE)
871 if (TRUE == is_lp5_family(p))
872 {
873 DdrUpdateACTimingReg_LP5(p, &ACTimingTbl_LP5[u1TimingIdx]);
874 }
875 else
876 #endif
877 {
878 DdrUpdateACTimingReg_LP4(p, &ACTimingTbl_LP4[u1TimingIdx]);
879 }
880
881 return DRAM_OK;
882 }
883 #if 0
884 #if ((!SW_CHANGE_FOR_SIMULATION) && (!FOR_DV_SIMULATION_USED && SW_CHANGE_FOR_SIMULATION == 0) && (!__ETT__))
885 DRAM_STATUS_T DdrUpdateACTiming_EMI(DRAMC_CTX_T *p, AC_TIMING_EXTERNAL_T *ACRegFromEmi)
886 {
887 U8 u1TimingIdx = 0;
888 #if (__LP5_COMBO__ == TRUE)
889 ACTime_T_LP5 ACTime_LP5;
890 #endif
891 ACTime_T_LP4 ACTime_LP4;
892 msg3("[DdrUpdateACTiming_EMI]\n");
893
894 if (ACRegFromEmi == NULL)
895 return DRAM_FAIL;
896
897 //Retrieve ACTimingTable's corresponding index
898 u1TimingIdx = u1GetACTimingIdx(p);
899 #if (__LP5_COMBO__ == TRUE)
900 if (TRUE == is_lp5_family(p))
901 {
902 ACTime_LP5 = ACTimingTbl_LP5[u1TimingIdx];
903 }
904 #endif
905 ACTime_LP4 = ACTimingTbl_LP4[u1TimingIdx];
906
907 //Overwrite AC timing from emi settings
908 ACTime.dramType = p->dram_type;
909 #if 1 // Will use MDL ac timing, Others from internal ac timing
910 ACTime.trp = ACRegFromEmi->AC_TIME_EMI_TRP;
911 ACTime.trpab = ACRegFromEmi->AC_TIME_EMI_TRPAB;
912 ACTime.trc = ACRegFromEmi->AC_TIME_EMI_TRC;
913 ACTime.trcd = ACRegFromEmi->AC_TIME_EMI_TRCD;
914
915 ACTime.trp_05T = ACRegFromEmi->AC_TIME_EMI_TRP_05T;
916 ACTime.trpab_05T = ACRegFromEmi->AC_TIME_EMI_TRPAB_05T;
917 ACTime.trc_05T = ACRegFromEmi->AC_TIME_EMI_TRC_05T;
918 ACTime.trcd_05T = ACRegFromEmi->AC_TIME_EMI_TRCD_05T;
919 #else
920 ACTime.freq = ACRegFromEmi->AC_TIME_EMI_FREQUENCY;
921 ACTime.tras = ACRegFromEmi->AC_TIME_EMI_TRAS;
922 ACTime.trp = ACRegFromEmi->AC_TIME_EMI_TRP;
923
924 ACTime.trpab = ACRegFromEmi->AC_TIME_EMI_TRPAB;
925 ACTime.trc = ACRegFromEmi->AC_TIME_EMI_TRC;
926 ACTime.trfc = ACRegFromEmi->AC_TIME_EMI_TRFC;
927 ACTime.trfcpb = ACRegFromEmi->AC_TIME_EMI_TRFCPB;
928
929 ACTime.txp = ACRegFromEmi->AC_TIME_EMI_TXP;
930 ACTime.trtp = ACRegFromEmi->AC_TIME_EMI_TRTP;
931 ACTime.trcd = ACRegFromEmi->AC_TIME_EMI_TRCD;
932 ACTime.twr = ACRegFromEmi->AC_TIME_EMI_TWR;
933
934 ACTime.twtr = ACRegFromEmi->AC_TIME_EMI_TWTR;
935 ACTime.trrd = ACRegFromEmi->AC_TIME_EMI_TRRD;
936 ACTime.tfaw = ACRegFromEmi->AC_TIME_EMI_TFAW;
937 ACTime.trtw_ODT_off = ACRegFromEmi->AC_TIME_EMI_TRTW_ODT_OFF;
938 ACTime.trtw_ODT_on = ACRegFromEmi->AC_TIME_EMI_TRTW_ODT_ON;
939
940 ACTime.refcnt = ACRegFromEmi->AC_TIME_EMI_REFCNT; //(REFFRERUN = 0)
941 ACTime.refcnt_fr_clk = ACRegFromEmi->AC_TIME_EMI_REFCNT_FR_CLK; //(REFFRERUN = 1)
942 ACTime.txrefcnt = ACRegFromEmi->AC_TIME_EMI_TXREFCNT;
943 ACTime.tzqcs = ACRegFromEmi->AC_TIME_EMI_TZQCS;
944
945 ACTime.trtpd = ACRegFromEmi->AC_TIME_EMI_TRTPD;
946 ACTime.twtpd = ACRegFromEmi->AC_TIME_EMI_TWTPD;
947 ACTime.tmrr2w_ODT_off = ACRegFromEmi->AC_TIME_EMI_TMRR2W_ODT_OFF;
948 ACTime.tmrr2w_ODT_on = ACRegFromEmi->AC_TIME_EMI_TMRR2W_ODT_ON;
949
950 ACTime.tras_05T = ACRegFromEmi->AC_TIME_EMI_TRAS_05T;
951 ACTime.trp_05T = ACRegFromEmi->AC_TIME_EMI_TRP_05T;
952 ACTime.trpab_05T = ACRegFromEmi->AC_TIME_EMI_TRPAB_05T;
953 ACTime.trc_05T = ACRegFromEmi->AC_TIME_EMI_TRC_05T;
954 ACTime.trfc_05T = ACRegFromEmi->AC_TIME_EMI_TRFC_05T;
955 ACTime.trfcpb_05T = ACRegFromEmi->AC_TIME_EMI_TRFCPB_05T;
956 ACTime.txp_05T = ACRegFromEmi->AC_TIME_EMI_TXP_05T;
957 ACTime.trtp_05T = ACRegFromEmi->AC_TIME_EMI_TRTP_05T;
958 ACTime.trcd_05T = ACRegFromEmi->AC_TIME_EMI_TRCD_05T;
959 ACTime.twr_05T = ACRegFromEmi->AC_TIME_EMI_TWR_05T;
960 ACTime.twtr_05T = ACRegFromEmi->AC_TIME_EMI_TWTR_05T;
961 ACTime.trrd_05T = ACRegFromEmi->AC_TIME_EMI_TRRD_05T;
962 ACTime.tfaw_05T = ACRegFromEmi->AC_TIME_EMI_TFAW_05T;
963 ACTime.trtw_ODT_off_05T = ACRegFromEmi->AC_TIME_EMI_TRTW_ODT_OFF_05T;
964 ACTime.trtw_ODT_on_05T = ACRegFromEmi->AC_TIME_EMI_TRTW_ODT_ON_05T;
965 ACTime.trtpd_05T = ACRegFromEmi->AC_TIME_EMI_TRTPD_05T;
966 ACTime.twtpd_05T = ACRegFromEmi->AC_TIME_EMI_TWTPD_05T;
967 #endif
968
969 //Set ACTiming registers
970 DdrUpdateACTimingReg(p, &ACTime);
971
972 return DRAM_OK;
973 }
974 #endif
975 #endif
976 ///TODO: wait for porting +++
977 #if __A60868_TO_BE_PORTING__
978
vDramcACTimingGetDatLat(DRAMC_CTX_T * p)979 U8 vDramcACTimingGetDatLat(DRAMC_CTX_T *p)
980 {
981 U8 u1TimingIdx = u1GetACTimingIdx(p);
982 #if (__LP5_COMBO__ == TRUE)
983 ACTime_T_LP5 ACTime = ACTimingTbl_LP5[u1TimingIdx];
984 #else
985 ACTime_T_LP4 ACTime = ACTimingTbl_LP4[u1TimingIdx];
986 #endif
987
988 return ACTime.datlat;
989 }
990 #endif // __A60868_TO_BE_PORTING__
991 ///TODO: wait for porting +++
992
993 /* Optimize all-bank refresh parameters (by density) for LP4 */
vDramcACTimingOptimize(DRAMC_CTX_T * p)994 void vDramcACTimingOptimize(DRAMC_CTX_T *p)
995 {
996 /* TRFC: tRFCab
997 * Refresh Cycle Time (All Banks)
998 * TXREFCNT: tXSR max((tRFCab + 7.5ns), 2nCK)
999 * Min self refresh time (Entry to Exit)
1000 * u1ExecuteOptimize: Indicate if ACTimings are updated at the end of this function
1001 */
1002 U8 u1RFCabGrpIdx = 0, u1FreqGrpIdx = 0, u1ExecuteOptimize = ENABLE;
1003 U8 u1TRFC=101, u1TRFC_05T=0, u1TRFCpb=44, u1TRFCpb_05T=0,u1TXREFCNT=118;
1004 typedef struct
1005 { /* Bitfield sizes set to current project register field's size */
1006 U8 u1TRFC : 8;
1007 U8 u1TRFRC_05T : 1;
1008 U8 u1TRFCpb : 8;
1009 U8 u1TRFRCpb_05T : 1;
1010 U16 u2TXREFCNT : 10;
1011 } optimizeACTime;
1012 /* JESD209-4B: tRFCab has 4 settings for 7 density settings (130, 180, 280, 380)
1013 * tRFCAB_NUM: Used to indicate tRFCab group (since some densities share the same tRFCab)
1014 */
1015 enum tRFCABIdx{tRFCAB_130 = 0, tRFCAB_180, tRFCAB_280, tRFCAB_380, tRFCAB_NUM};
1016 enum ACTimeIdx{GRP_DDR1200_ACTIM, GRP_DDR1600_ACTIM, GRP_DDR1866_ACTIM, GRP_DDR2400_ACTIM, GRP_DDR2667_ACTIM, GRP_DDR3200_ACTIM, GRP_DDR3733_ACTIM, GRP_DDR4266_ACTIM, GRP_ACTIM_NUM};
1017 enum ACTimeIdxDiv4{GRP_DDR800_DIV4_ACTIM = 0, GRP_DDR1200_DIV4_ACTIM, GRP_DDR1600_DIV4_ACTIM, GRP_ACTIM_NUM_DIV4};
1018 /* Values retrieved from 1. Alaska ACTiming excel file 2. JESD209-4B Refresh requirement table */
1019
1020 optimizeACTime *ptRFCab_Opt;
1021
1022 optimizeACTime tRFCab_Opt [GRP_ACTIM_NUM][tRFCAB_NUM] =
1023 {
1024 //For freqGroup DDR1200
1025 {{.u1TRFC = 8, .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 21}, //tRFCab = 130, tRFCpb = 60, @Robert Not enough to Optimize
1026 {.u1TRFC = 15, .u1TRFRC_05T = 1, .u1TRFCpb = 2, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 29}, //tRFCab = 180, tRFCpb = 90
1027 {.u1TRFC = 30, .u1TRFRC_05T = 1, .u1TRFCpb = 9, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 44}, //tRFCab = 280, tRFCpb = 140
1028 {.u1TRFC = 45, .u1TRFRC_05T = 1, .u1TRFCpb = 17, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 59}},//tRFCab = 380, tRFCpb = 190
1029 //For freqGroup DDR1600
1030 {{.u1TRFC = 14, .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 28}, //tRFCab = 130, tRFCpb = 60
1031 {.u1TRFC = 24, .u1TRFRC_05T = 0, .u1TRFCpb = 6, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 38}, //tRFCab = 180, tRFCpb = 90
1032 {.u1TRFC = 44, .u1TRFRC_05T = 0, .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 58}, //tRFCab = 280, tRFCpb = 140
1033 {.u1TRFC = 64, .u1TRFRC_05T = 0, .u1TRFCpb = 26, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 78}},//tRFCab = 380, tRFCpb = 190
1034 //For freqGroup DDR1866
1035 {{.u1TRFC = 18, .u1TRFRC_05T = 1, .u1TRFCpb = 2, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 33}, //tRFCab = 130, tRFCpb = 60
1036 {.u1TRFC = 30, .u1TRFRC_05T = 0, .u1TRFCpb = 9, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 44}, //tRFCab = 180, tRFCpb = 90
1037 {.u1TRFC = 53, .u1TRFRC_05T = 1, .u1TRFCpb = 21, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 68}, //tRFCab = 280, tRFCpb = 140
1038 {.u1TRFC = 77, .u1TRFRC_05T = 0, .u1TRFCpb = 32, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 91}},//tRFCab = 380, tRFCpb = 190
1039 //For freqGroup DDR2400
1040 {{.u1TRFC = 27, .u1TRFRC_05T = 1, .u1TRFCpb = 6, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 42}, //tRFCab = 130, tRFCpb = 60
1041 {.u1TRFC = 42, .u1TRFRC_05T = 1, .u1TRFCpb = 15, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 57}, //tRFCab = 180, tRFCpb = 90
1042 {.u1TRFC = 72, .u1TRFRC_05T = 1, .u1TRFCpb = 30, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 87}, //tRFCab = 280, tRFCpb = 140
1043 {.u1TRFC = 102, .u1TRFRC_05T = 1, .u1TRFCpb = 45, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 117}},//tRFCab = 380, tRFCpb = 190
1044 //For freqGroup DDR2667
1045 {{.u1TRFC = 31, .u1TRFRC_05T = 1, .u1TRFCpb = 8, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 46}, //tRFCab = 130, tRFCpb = 60
1046 {.u1TRFC = 48, .u1TRFRC_05T = 1, .u1TRFCpb = 18, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 63}, //tRFCab = 180, tRFCpb = 90
1047 {.u1TRFC = 81, .u1TRFRC_05T = 1, .u1TRFCpb = 35, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 96}, //tRFCab = 280, tRFCpb = 140
1048 {.u1TRFC = 115, .u1TRFRC_05T = 0, .u1TRFCpb = 51, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 130}}, //tRFCab = 380, tRFCpb = 190
1049 //For freqGroup DDR3200
1050 {{.u1TRFC = 40, .u1TRFRC_05T = 0, .u1TRFCpb = 12, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 55}, //tRFCab = 130, tRFCpb = 60
1051 {.u1TRFC = 60, .u1TRFRC_05T = 0, .u1TRFCpb = 24, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 75}, //tRFCab = 180, tRFCpb = 90
1052 {.u1TRFC = 100, .u1TRFRC_05T = 0, .u1TRFCpb = 44, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 115}, //tRFCab = 280, tRFCpb = 140
1053 {.u1TRFC = 140, .u1TRFRC_05T = 0, .u1TRFCpb = 64, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 155}}, //tRFCab = 380, tRFCpb = 190
1054 //For freqGroup DDR3733
1055 {{.u1TRFC = 49, .u1TRFRC_05T = 0, .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 65}, //tRFCab = 130, tRFCpb = 60
1056 {.u1TRFC = 72, .u1TRFRC_05T = 0, .u1TRFCpb = 30, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 88}, //tRFCab = 180, tRFCpb = 90
1057 {.u1TRFC = 119, .u1TRFRC_05T = 0, .u1TRFCpb = 53, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 135}, //tRFCab = 280, tRFCpb = 140
1058 {.u1TRFC = 165, .u1TRFRC_05T = 1, .u1TRFCpb = 77, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 181}}, //tRFCab = 380, tRFCpb = 190
1059 //For freqGroup DDR4266
1060 {{.u1TRFC = 57, .u1TRFRC_05T = 1, .u1TRFCpb = 20, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 74}, //tRFCab = 130, tRFCpb = 60
1061 {.u1TRFC = 84, .u1TRFRC_05T = 0, .u1TRFCpb = 36, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 100}, //tRFCab = 180, tRFCpb = 90
1062 {.u1TRFC = 137, .u1TRFRC_05T = 1, .u1TRFCpb = 63, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 154}, //tRFCab = 280, tRFCpb = 140
1063 {.u1TRFC = 191, .u1TRFRC_05T = 0, .u1TRFCpb = 89, .u1TRFRCpb_05T = 1, .u2TXREFCNT = 207}} //tRFCab = 380, tRFCpb = 190
1064 };
1065
1066 optimizeACTime tRFCab_Opt_Div4 [GRP_ACTIM_NUM_DIV4][tRFCAB_NUM] =
1067 {
1068 //NOTE: @Darren, For freqGroup DDR816
1069 {{.u1TRFC = 14, .u1TRFRC_05T = 0, .u1TRFCpb = 0, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 28}, //tRFCab = 130, tRFCpb = 60
1070 {.u1TRFC = 24, .u1TRFRC_05T = 0, .u1TRFCpb = 6, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 38}, //tRFCab = 180, tRFCpb = 90
1071 {.u1TRFC = 44, .u1TRFRC_05T = 0, .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 58}, //tRFCab = 280, tRFCpb = 140
1072 {.u1TRFC = 64, .u1TRFRC_05T = 0, .u1TRFCpb = 26, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 78}},//tRFCab = 380, tRFCpb = 190
1073 //For freqGroup DDR1200
1074 {{.u1TRFC = 28, .u1TRFRC_05T = 0, .u1TRFCpb = 7, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 42}, //tRFCab = 130, tRFCpb = 60
1075 {.u1TRFC = 43, .u1TRFRC_05T = 0, .u1TRFCpb = 16, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 57}, //tRFCab = 180, tRFCpb = 90
1076 {.u1TRFC = 73, .u1TRFRC_05T = 0, .u1TRFCpb = 31, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 87}, //tRFCab = 280, tRFCpb = 140
1077 {.u1TRFC = 103, .u1TRFRC_05T = 0, .u1TRFCpb = 46, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 117}},//tRFCab = 380, tRFCpb = 190
1078 //For freqGroup DDR1600
1079 {{.u1TRFC = 40, .u1TRFRC_05T = 0, .u1TRFCpb = 12, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 55}, //tRFCab = 130, tRFCpb = 60
1080 {.u1TRFC = 60, .u1TRFRC_05T = 0, .u1TRFCpb = 24, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 75}, //tRFCab = 180, tRFCpb = 90
1081 {.u1TRFC = 100, .u1TRFRC_05T = 0, .u1TRFCpb = 44, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 115}, //tRFCab = 280, tRFCpb = 140
1082 {.u1TRFC = 140, .u1TRFRC_05T = 0, .u1TRFCpb = 64, .u1TRFRCpb_05T = 0, .u2TXREFCNT = 155}}, //tRFCab = 380, tRFCpb = 190
1083 };
1084
1085
1086 msg("[ACTimingOptimize]");
1087
1088 #if __ETT__
1089 if (p->density==0xff)
1090 {
1091 err("Error : No call MR8 to get density!!\n");
1092 while(1);
1093 }
1094 #endif
1095
1096 /* Set tRFCab group idx p->density = MR8 OP[5:2]*/
1097 switch (p->density)
1098 {
1099 case 0x0: //4Gb per die (2Gb per channel), tRFCab=130
1100 u1RFCabGrpIdx = tRFCAB_130;
1101 break;
1102 case 0x1: //6Gb per die (3Gb per channel), tRFCab=180
1103 case 0x2: //8Gb per die (4Gb per channel), tRFCab=180
1104 u1RFCabGrpIdx = tRFCAB_180;
1105 break;
1106 case 0x3: //12Gb per die (6Gb per channel), tRFCab=280
1107 case 0x4: //16Gb per die (8Gb per channel), tRFCab=280
1108 u1RFCabGrpIdx = tRFCAB_280;
1109 break;
1110 case 0x5: //24Gb per die (12Gb per channel), tRFCab=380
1111 case 0x6: //32Gb per die (16Gb per channel), tRFCab=380
1112 u1RFCabGrpIdx = tRFCAB_380;
1113 break;
1114 default:
1115 u1ExecuteOptimize = DISABLE;
1116 err("MR8 density err!\n");
1117 }
1118 /* Set freqGroup Idx */
1119 switch (p->freqGroup)
1120 {
1121 case 400:
1122 if (vGet_Div_Mode(p) == DIV4_MODE)
1123 u1FreqGrpIdx = GRP_DDR800_DIV4_ACTIM;
1124 else
1125 {
1126 u1ExecuteOptimize = DISABLE;
1127 err("freqGroup err!\n");
1128 #if __ETT__
1129 while(1);
1130 #endif
1131 }
1132 break;
1133 case 600:
1134 if (vGet_Div_Mode(p) == DIV4_MODE)
1135 u1FreqGrpIdx = GRP_DDR1200_DIV4_ACTIM;
1136 else
1137 u1FreqGrpIdx = GRP_DDR1200_ACTIM;
1138 break;
1139 case 800:
1140 if (vGet_Div_Mode(p) == DIV4_MODE)
1141 u1FreqGrpIdx = GRP_DDR1600_DIV4_ACTIM;
1142 else
1143 u1FreqGrpIdx = GRP_DDR1600_ACTIM;
1144 break;
1145 case 933:
1146 u1FreqGrpIdx = GRP_DDR1866_ACTIM;
1147 break;
1148 case 1200:
1149 u1FreqGrpIdx = GRP_DDR2400_ACTIM;
1150 break;
1151 case 1333:
1152 u1FreqGrpIdx = GRP_DDR2667_ACTIM;
1153 break;
1154 case 1600:
1155 u1FreqGrpIdx = GRP_DDR3200_ACTIM;
1156 break;
1157 case 1866:
1158 u1FreqGrpIdx = GRP_DDR3733_ACTIM;
1159 break;
1160 case 2133:
1161 u1FreqGrpIdx = GRP_DDR4266_ACTIM;
1162 break;
1163 default:
1164 u1ExecuteOptimize = DISABLE;
1165 err("freqGroup err!\n");
1166 #if __ETT__
1167 while(1);
1168 #endif
1169 }
1170
1171 if (vGet_Div_Mode(p) == DIV4_MODE && u1FreqGrpIdx >= GRP_ACTIM_NUM_DIV4)
1172 {
1173 u1ExecuteOptimize = DISABLE;
1174 err("freqGroup err!\n");
1175 #if __ETT__
1176 while(1);
1177 #endif
1178 }
1179 if (vGet_Div_Mode(p) == DIV4_MODE && u1FreqGrpIdx < GRP_ACTIM_NUM_DIV4)
1180 ptRFCab_Opt = &tRFCab_Opt_Div4[u1FreqGrpIdx][0];
1181 else
1182 ptRFCab_Opt = &tRFCab_Opt[u1FreqGrpIdx][0];
1183
1184 u1TRFC = ptRFCab_Opt[u1RFCabGrpIdx].u1TRFC;
1185 u1TRFC_05T = ptRFCab_Opt[u1RFCabGrpIdx].u1TRFRC_05T;
1186 u1TRFCpb = ptRFCab_Opt[u1RFCabGrpIdx].u1TRFCpb;
1187 u1TRFCpb_05T = ptRFCab_Opt[u1RFCabGrpIdx].u1TRFRCpb_05T;
1188 u1TXREFCNT = ptRFCab_Opt[u1RFCabGrpIdx].u2TXREFCNT;
1189
1190 /* Only execute ACTimingOptimize(write to regs) when corresponding values have been found */
1191 if (u1ExecuteOptimize == ENABLE)
1192 {
1193 vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM3, u1TRFC, SHU_ACTIM3_TRFC);
1194 vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_TIME_05T, u1TRFC_05T, SHU_AC_TIME_05T_TRFC_05T);
1195 vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM4, u1TXREFCNT, SHU_ACTIM4_TXREFCNT);
1196 vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM3, u1TRFCpb, SHU_ACTIM3_TRFCPB);
1197 vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_TIME_05T, u1TRFCpb_05T, SHU_AC_TIME_05T_TRFCPB_05T);
1198
1199 msg("Density (MR8 OP[5:2]) %u, TRFC %u, TRFC_05T %u, TXREFCNT %u, TRFCpb %u, TRFCpb_05T %u\n", p->density, u1TRFC, u1TRFC_05T, u1TXREFCNT, u1TRFCpb, u1TRFCpb_05T);
1200 }
1201
1202 return;
1203 }
1204
1205 /* ACTimingTbl: All freq's ACTiming from ACTiming excel file
1206 * (Some fields don't exist for LP3 -> set to 0)
1207 * Note: !!All ACTiming adjustments should not be set in-table should be moved into UpdateACTimingReg()!!
1208 * Or else preloader's highest freq ACTimings may be set to different values than expected.
1209 */
1210 const ACTime_T_LP4 ACTimingTbl_LP4[AC_TIMING_NUMBER_LP4] = {
1211 //----------LPDDR4---------------------------
1212 #if SUPPORT_LP4_DDR4266_ACTIM
1213 //LP4_DDR4266 ACTiming---------------------------------
1214 #if (ENABLE_READ_DBI == 1)
1215 //LPDDR4 4X_4266_Div 8_DBI1.csv Read 1
1216 {
1217 .dramType = TYPE_LPDDR4, .freq = 2133, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1,
1218 .readLat = 40, .writeLat = 18, .DivMode = DIV8_MODE,
1219
1220 .tras = 14, .tras_05T = 0,
1221 .trp = 8, .trp_05T = 1,
1222 .trpab = 10, .trpab_05T = 0,
1223 .trc = 23, .trc_05T = 0,
1224 .trfc = 137, .trfc_05T = 1,
1225 .trfcpb = 63, .trfcpb_05T = 0,
1226 .txp = 1, .txp_05T = 0,
1227 .trtp = 2, .trtp_05T = 1,
1228 .trcd = 10, .trcd_05T = 0,
1229 .twr = 15, .twr_05T = 0,
1230 .twtr = 10, .twtr_05T = 1,
1231 .tpbr2pbr = 41, .tpbr2pbr_05T = 0,
1232 .tpbr2act = 0, .tpbr2act_05T = 0,
1233 .tr2mrw = 18, .tr2mrw_05T = 0,
1234 .tw2mrw = 11, .tw2mrw_05T = 0,
1235 .tmrr2mrw = 15, .tmrr2mrw_05T = 0,
1236 .tmrw = 6, .tmrw_05T = 0,
1237 .tmrd = 8, .tmrd_05T = 0,
1238 .tmrwckel = 9, .tmrwckel_05T = 0,
1239 .tpde = 1, .tpde_05T = 1,
1240 .tpdx = 1, .tpdx_05T = 0,
1241 .tmrri = 14, .tmrri_05T = 0,
1242 .trrd = 4, .trrd_05T = 1,
1243 .trrd_4266 = 3, .trrd_4266_05T = 0,
1244 .tfaw = 13, .tfaw_05T = 1,
1245 .tfaw_4266 = 8, .tfaw_4266_05T = 0,
1246 .trtw_odt_off = 7, .trtw_odt_off_05T = 0,
1247 .trtw_odt_on = 9, .trtw_odt_on_05T = 0,
1248 .txrefcnt = 154,
1249 .tzqcs = 46,
1250 .xrtw2w_new_mode = 5,
1251 .xrtw2w_old_mode = 6,
1252 .xrtw2r_odt_on = 1,
1253 .xrtw2r_odt_off = 1,
1254 .xrtr2w_odt_on = 8,
1255 .xrtr2w_odt_off = 8,
1256 .xrtr2r_new_mode = 3,
1257 .xrtr2r_old_mode = 7,
1258 .tr2mrr = 4,
1259 .vrcgdis_prdcnt = 54,
1260 .hwset_mr2_op = 63,
1261 .hwset_mr13_op = 216,
1262 .hwset_vrcg_op = 208,
1263 .trcd_derate = 11, .trcd_derate_05T = 0,
1264 .trc_derate = 26, .trc_derate_05T = 0,
1265 .tras_derate = 15, .tras_derate_05T = 0,
1266 .trpab_derate = 11, .trpab_derate_05T = 0,
1267 .trp_derate = 9, .trp_derate_05T = 1,
1268 .trrd_derate = 5, .trrd_derate_05T = 1,
1269 .trtpd = 15, .trtpd_05T = 1,
1270 .twtpd = 18, .twtpd_05T = 0,
1271 .tmrr2w_odt_off = 11,
1272 .tmrr2w_odt_on = 13,
1273 .ckeprd = 3,
1274 .ckelckcnt = 3,
1275 .zqlat2 = 16,
1276
1277 //DQSINCTL, DATLAT aren't in ACTiming excel file
1278 .dqsinctl = 7, .datlat = 18
1279 },
1280 //LPDDR4 4X_4266_BT_Div 8_DBI1.csv Read 1
1281 {
1282 .dramType = TYPE_LPDDR4, .freq = 2133, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1,
1283 .readLat = 44, .writeLat = 18, .DivMode = DIV8_MODE,
1284
1285 .tras = 14, .tras_05T = 0,
1286 .trp = 8, .trp_05T = 1,
1287 .trpab = 10, .trpab_05T = 0,
1288 .trc = 23, .trc_05T = 0,
1289 .trfc = 137, .trfc_05T = 1,
1290 .trfcpb = 63, .trfcpb_05T = 0,
1291 .txp = 1, .txp_05T = 0,
1292 .trtp = 2, .trtp_05T = 1,
1293 .trcd = 10, .trcd_05T = 0,
1294 .twr = 16, .twr_05T = 0,
1295 .twtr = 11, .twtr_05T = 1,
1296 .tpbr2pbr = 41, .tpbr2pbr_05T = 0,
1297 .tpbr2act = 0, .tpbr2act_05T = 0,
1298 .tr2mrw = 19, .tr2mrw_05T = 0,
1299 .tw2mrw = 11, .tw2mrw_05T = 0,
1300 .tmrr2mrw = 16, .tmrr2mrw_05T = 0,
1301 .tmrw = 6, .tmrw_05T = 0,
1302 .tmrd = 8, .tmrd_05T = 0,
1303 .tmrwckel = 9, .tmrwckel_05T = 0,
1304 .tpde = 1, .tpde_05T = 1,
1305 .tpdx = 1, .tpdx_05T = 0,
1306 .tmrri = 14, .tmrri_05T = 0,
1307 .trrd = 4, .trrd_05T = 1,
1308 .trrd_4266 = 3, .trrd_4266_05T = 0,
1309 .tfaw = 13, .tfaw_05T = 1,
1310 .tfaw_4266 = 8, .tfaw_4266_05T = 0,
1311 .trtw_odt_off = 8, .trtw_odt_off_05T = 0,
1312 .trtw_odt_on = 10, .trtw_odt_on_05T = 0,
1313 .txrefcnt = 154,
1314 .tzqcs = 46,
1315 .xrtw2w_new_mode = 5,
1316 .xrtw2w_old_mode = 6,
1317 .xrtw2r_odt_on = 1,
1318 .xrtw2r_odt_off = 1,
1319 .xrtr2w_odt_on = 9,
1320 .xrtr2w_odt_off = 9,
1321 .xrtr2r_new_mode = 3,
1322 .xrtr2r_old_mode = 7,
1323 .tr2mrr = 4,
1324 .vrcgdis_prdcnt = 54,
1325 .hwset_mr2_op = 63,
1326 .hwset_mr13_op = 216,
1327 .hwset_vrcg_op = 208,
1328 .trcd_derate = 11, .trcd_derate_05T = 0,
1329 .trc_derate = 26, .trc_derate_05T = 0,
1330 .tras_derate = 15, .tras_derate_05T = 0,
1331 .trpab_derate = 11, .trpab_derate_05T = 0,
1332 .trp_derate = 9, .trp_derate_05T = 1,
1333 .trrd_derate = 5, .trrd_derate_05T = 1,
1334 .trtpd = 16, .trtpd_05T = 1,
1335 .twtpd = 19, .twtpd_05T = 0,
1336 .tmrr2w_odt_off = 12,
1337 .tmrr2w_odt_on = 14,
1338 .ckeprd = 3,
1339 .ckelckcnt = 3,
1340 .zqlat2 = 16,
1341
1342 //DQSINCTL, DATLAT aren't in ACTiming excel file
1343 .dqsinctl = 7, .datlat = 18
1344 },
1345 #else //ENABLE_READ_DBI == 0)
1346 //LPDDR4 4X_4266_Div 8_DBI0.csv Read 0
1347 {
1348 .dramType = TYPE_LPDDR4, .freq = 2133, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
1349 .readLat = 36, .writeLat = 18, .DivMode = DIV8_MODE,
1350
1351 .tras = 14, .tras_05T = 0,
1352 .trp = 8, .trp_05T = 1,
1353 .trpab = 10, .trpab_05T = 0,
1354 .trc = 23, .trc_05T = 0,
1355 .trfc = 137, .trfc_05T = 1,
1356 .trfcpb = 63, .trfcpb_05T = 0,
1357 .txp = 1, .txp_05T = 0,
1358 .trtp = 2, .trtp_05T = 1,
1359 .trcd = 10, .trcd_05T = 0,
1360 .twr = 15, .twr_05T = 0,
1361 .twtr = 10, .twtr_05T = 1,
1362 .tpbr2pbr = 41, .tpbr2pbr_05T = 0,
1363 .tpbr2act = 0, .tpbr2act_05T = 0,
1364 .tr2mrw = 17, .tr2mrw_05T = 0,
1365 .tw2mrw = 11, .tw2mrw_05T = 0,
1366 .tmrr2mrw = 14, .tmrr2mrw_05T = 0,
1367 .tmrw = 6, .tmrw_05T = 0,
1368 .tmrd = 8, .tmrd_05T = 0,
1369 .tmrwckel = 9, .tmrwckel_05T = 0,
1370 .tpde = 1, .tpde_05T = 1,
1371 .tpdx = 1, .tpdx_05T = 0,
1372 .tmrri = 14, .tmrri_05T = 0,
1373 .trrd = 4, .trrd_05T = 1,
1374 .trrd_4266 = 3, .trrd_4266_05T = 0,
1375 .tfaw = 13, .tfaw_05T = 1,
1376 .tfaw_4266 = 8, .tfaw_4266_05T = 0,
1377 .trtw_odt_off = 6, .trtw_odt_off_05T = 0,
1378 .trtw_odt_on = 8, .trtw_odt_on_05T = 0,
1379 .txrefcnt = 154,
1380 .tzqcs = 46,
1381 .xrtw2w_new_mode = 5,
1382 .xrtw2w_old_mode = 6,
1383 .xrtw2r_odt_on = 1,
1384 .xrtw2r_odt_off = 1,
1385 .xrtr2w_odt_on = 7,
1386 .xrtr2w_odt_off = 7,
1387 .xrtr2r_new_mode = 3,
1388 .xrtr2r_old_mode = 7,
1389 .tr2mrr = 4,
1390 .vrcgdis_prdcnt = 54,
1391 .hwset_mr2_op = 63,
1392 .hwset_mr13_op = 216,
1393 .hwset_vrcg_op = 208,
1394 .trcd_derate = 11, .trcd_derate_05T = 0,
1395 .trc_derate = 26, .trc_derate_05T = 0,
1396 .tras_derate = 15, .tras_derate_05T = 0,
1397 .trpab_derate = 11, .trpab_derate_05T = 0,
1398 .trp_derate = 9, .trp_derate_05T = 1,
1399 .trrd_derate = 5, .trrd_derate_05T = 1,
1400 .trtpd = 14, .trtpd_05T = 1,
1401 .twtpd = 18, .twtpd_05T = 0,
1402 .tmrr2w_odt_off = 10,
1403 .tmrr2w_odt_on = 12,
1404 .ckeprd = 3,
1405 .ckelckcnt = 3,
1406 .zqlat2 = 16,
1407
1408 //DQSINCTL, DATLAT aren't in ACTiming excel file
1409 .dqsinctl = 7, .datlat = 18
1410 },
1411 //LPDDR4 4X_4266_BT_Div 8_DBI0.csv Read 0
1412 {
1413 .dramType = TYPE_LPDDR4, .freq = 2133, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
1414 .readLat = 40, .writeLat = 18, .DivMode = DIV8_MODE,
1415
1416 .tras = 14, .tras_05T = 0,
1417 .trp = 8, .trp_05T = 1,
1418 .trpab = 10, .trpab_05T = 0,
1419 .trc = 23, .trc_05T = 0,
1420 .trfc = 137, .trfc_05T = 1,
1421 .trfcpb = 63, .trfcpb_05T = 0,
1422 .txp = 1, .txp_05T = 0,
1423 .trtp = 2, .trtp_05T = 1,
1424 .trcd = 10, .trcd_05T = 0,
1425 .twr = 16, .twr_05T = 0,
1426 .twtr = 11, .twtr_05T = 1,
1427 .tpbr2pbr = 41, .tpbr2pbr_05T = 0,
1428 .tpbr2act = 0, .tpbr2act_05T = 0,
1429 .tr2mrw = 18, .tr2mrw_05T = 0,
1430 .tw2mrw = 11, .tw2mrw_05T = 0,
1431 .tmrr2mrw = 15, .tmrr2mrw_05T = 0,
1432 .tmrw = 6, .tmrw_05T = 0,
1433 .tmrd = 8, .tmrd_05T = 0,
1434 .tmrwckel = 9, .tmrwckel_05T = 0,
1435 .tpde = 1, .tpde_05T = 1,
1436 .tpdx = 1, .tpdx_05T = 0,
1437 .tmrri = 14, .tmrri_05T = 0,
1438 .trrd = 4, .trrd_05T = 1,
1439 .trrd_4266 = 3, .trrd_4266_05T = 0,
1440 .tfaw = 13, .tfaw_05T = 1,
1441 .tfaw_4266 = 8, .tfaw_4266_05T = 0,
1442 .trtw_odt_off = 7, .trtw_odt_off_05T = 0,
1443 .trtw_odt_on = 9, .trtw_odt_on_05T = 0,
1444 .txrefcnt = 154,
1445 .tzqcs = 46,
1446 .xrtw2w_new_mode = 5,
1447 .xrtw2w_old_mode = 6,
1448 .xrtw2r_odt_on = 1,
1449 .xrtw2r_odt_off = 1,
1450 .xrtr2w_odt_on = 8,
1451 .xrtr2w_odt_off = 8,
1452 .xrtr2r_new_mode = 3,
1453 .xrtr2r_old_mode = 7,
1454 .tr2mrr = 4,
1455 .vrcgdis_prdcnt = 54,
1456 .hwset_mr2_op = 63,
1457 .hwset_mr13_op = 216,
1458 .hwset_vrcg_op = 208,
1459 .trcd_derate = 11, .trcd_derate_05T = 0,
1460 .trc_derate = 26, .trc_derate_05T = 0,
1461 .tras_derate = 15, .tras_derate_05T = 0,
1462 .trpab_derate = 11, .trpab_derate_05T = 0,
1463 .trp_derate = 9, .trp_derate_05T = 1,
1464 .trrd_derate = 5, .trrd_derate_05T = 1,
1465 .trtpd = 15, .trtpd_05T = 1,
1466 .twtpd = 19, .twtpd_05T = 0,
1467 .tmrr2w_odt_off = 11,
1468 .tmrr2w_odt_on = 13,
1469 .ckeprd = 3,
1470 .ckelckcnt = 3,
1471 .zqlat2 = 16,
1472
1473 //DQSINCTL, DATLAT aren't in ACTiming excel file
1474 .dqsinctl = 7, .datlat = 18
1475 },
1476 #endif
1477 #endif
1478 #if SUPPORT_LP4_DDR3733_ACTIM
1479 //LP4_DDR3733 ACTiming---------------------------------
1480 #if (ENABLE_READ_DBI == 1)
1481 //LPDDR4 4X_3733_Div 8_DBI1.csv Read 1
1482 {
1483 .dramType = TYPE_LPDDR4, .freq = 1866, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1,
1484 .readLat = 36, .writeLat = 16, .DivMode = DIV8_MODE,
1485
1486 .tras = 11, .tras_05T = 1,
1487 .trp = 7, .trp_05T = 0,
1488 .trpab = 8, .trpab_05T = 1,
1489 .trc = 19, .trc_05T = 0,
1490 .trfc = 119, .trfc_05T = 0,
1491 .trfcpb = 53, .trfcpb_05T = 1,
1492 .txp = 0, .txp_05T = 1,
1493 .trtp = 2, .trtp_05T = 0,
1494 .trcd = 8, .trcd_05T = 1,
1495 .twr = 13, .twr_05T = 1,
1496 .twtr = 8, .twtr_05T = 0,
1497 .tpbr2pbr = 35, .tpbr2pbr_05T = 0,
1498 .tpbr2act = 0, .tpbr2act_05T = 0,
1499 .tr2mrw = 16, .tr2mrw_05T = 1,
1500 .tw2mrw = 10, .tw2mrw_05T = 0,
1501 .tmrr2mrw = 13, .tmrr2mrw_05T = 1,
1502 .tmrw = 5, .tmrw_05T = 1,
1503 .tmrd = 7, .tmrd_05T = 1,
1504 .tmrwckel = 8, .tmrwckel_05T = 1,
1505 .tpde = 1, .tpde_05T = 1,
1506 .tpdx = 1, .tpdx_05T = 0,
1507 .tmrri = 12, .tmrri_05T = 0,
1508 .trrd = 4, .trrd_05T = 0,
1509 .trrd_4266 = 2, .trrd_4266_05T = 1,
1510 .tfaw = 11, .tfaw_05T = 0,
1511 .tfaw_4266 = 6, .tfaw_4266_05T = 0,
1512 .trtw_odt_off = 6, .trtw_odt_off_05T = 0,
1513 .trtw_odt_on = 9, .trtw_odt_on_05T = 0,
1514 .txrefcnt = 135,
1515 .tzqcs = 40,
1516 .xrtw2w_new_mode = 5,
1517 .xrtw2w_old_mode = 6,
1518 .xrtw2r_odt_on = 1,
1519 .xrtw2r_odt_off = 1,
1520 .xrtr2w_odt_on = 8,
1521 .xrtr2w_odt_off = 8,
1522 .xrtr2r_new_mode = 3,
1523 .xrtr2r_old_mode = 7,
1524 .tr2mrr = 4,
1525 .vrcgdis_prdcnt = 47,
1526 .hwset_mr2_op = 54,
1527 .hwset_mr13_op = 216,
1528 .hwset_vrcg_op = 208,
1529 .trcd_derate = 9, .trcd_derate_05T = 1,
1530 .trc_derate = 21, .trc_derate_05T = 1,
1531 .tras_derate = 12, .tras_derate_05T = 0,
1532 .trpab_derate = 9, .trpab_derate_05T = 1,
1533 .trp_derate = 8, .trp_derate_05T = 0,
1534 .trrd_derate = 5, .trrd_derate_05T = 0,
1535 .trtpd = 14, .trtpd_05T = 0,
1536 .twtpd = 16, .twtpd_05T = 1,
1537 .tmrr2w_odt_off = 10,
1538 .tmrr2w_odt_on = 12,
1539 .ckeprd = 3,
1540 .ckelckcnt = 3,
1541 .zqlat2 = 14,
1542
1543 //DQSINCTL, DATLAT aren't in ACTiming excel file
1544 .dqsinctl = 6, .datlat = 16
1545 },
1546 //LPDDR4 4X_3733_BT_Div 8_DBI1.csv Read 1
1547 {
1548 .dramType = TYPE_LPDDR4, .freq = 1866, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1,
1549 .readLat = 40, .writeLat = 16, .DivMode = DIV8_MODE,
1550
1551 .tras = 11, .tras_05T = 1,
1552 .trp = 7, .trp_05T = 0,
1553 .trpab = 8, .trpab_05T = 1,
1554 .trc = 19, .trc_05T = 0,
1555 .trfc = 119, .trfc_05T = 0,
1556 .trfcpb = 53, .trfcpb_05T = 1,
1557 .txp = 0, .txp_05T = 1,
1558 .trtp = 2, .trtp_05T = 0,
1559 .trcd = 8, .trcd_05T = 1,
1560 .twr = 14, .twr_05T = 1,
1561 .twtr = 9, .twtr_05T = 0,
1562 .tpbr2pbr = 35, .tpbr2pbr_05T = 0,
1563 .tpbr2act = 0, .tpbr2act_05T = 0,
1564 .tr2mrw = 17, .tr2mrw_05T = 1,
1565 .tw2mrw = 10, .tw2mrw_05T = 0,
1566 .tmrr2mrw = 14, .tmrr2mrw_05T = 1,
1567 .tmrw = 5, .tmrw_05T = 1,
1568 .tmrd = 7, .tmrd_05T = 1,
1569 .tmrwckel = 8, .tmrwckel_05T = 1,
1570 .tpde = 1, .tpde_05T = 1,
1571 .tpdx = 1, .tpdx_05T = 0,
1572 .tmrri = 12, .tmrri_05T = 0,
1573 .trrd = 4, .trrd_05T = 0,
1574 .trrd_4266 = 2, .trrd_4266_05T = 1,
1575 .tfaw = 11, .tfaw_05T = 0,
1576 .tfaw_4266 = 6, .tfaw_4266_05T = 0,
1577 .trtw_odt_off = 7, .trtw_odt_off_05T = 0,
1578 .trtw_odt_on = 10, .trtw_odt_on_05T = 0,
1579 .txrefcnt = 135,
1580 .tzqcs = 40,
1581 .xrtw2w_new_mode = 5,
1582 .xrtw2w_old_mode = 6,
1583 .xrtw2r_odt_on = 1,
1584 .xrtw2r_odt_off = 1,
1585 .xrtr2w_odt_on = 9,
1586 .xrtr2w_odt_off = 9,
1587 .xrtr2r_new_mode = 3,
1588 .xrtr2r_old_mode = 7,
1589 .tr2mrr = 4,
1590 .vrcgdis_prdcnt = 47,
1591 .hwset_mr2_op = 54,
1592 .hwset_mr13_op = 216,
1593 .hwset_vrcg_op = 208,
1594 .trcd_derate = 9, .trcd_derate_05T = 1,
1595 .trc_derate = 21, .trc_derate_05T = 1,
1596 .tras_derate = 12, .tras_derate_05T = 0,
1597 .trpab_derate = 9, .trpab_derate_05T = 1,
1598 .trp_derate = 8, .trp_derate_05T = 0,
1599 .trrd_derate = 5, .trrd_derate_05T = 0,
1600 .trtpd = 15, .trtpd_05T = 0,
1601 .twtpd = 17, .twtpd_05T = 1,
1602 .tmrr2w_odt_off = 11,
1603 .tmrr2w_odt_on = 13,
1604 .ckeprd = 3,
1605 .ckelckcnt = 3,
1606 .zqlat2 = 14,
1607
1608 //DQSINCTL, DATLAT aren't in ACTiming excel file
1609 .dqsinctl = 6, .datlat = 16
1610 },
1611 #else //ENABLE_READ_DBI == 0)
1612 //LPDDR4 4X_3733_Div 8_DBI0.csv Read 0
1613 {
1614 .dramType = TYPE_LPDDR4, .freq = 1866, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
1615 .readLat = 32, .writeLat = 16, .DivMode = DIV8_MODE,
1616
1617 .tras = 11, .tras_05T = 1,
1618 .trp = 7, .trp_05T = 0,
1619 .trpab = 8, .trpab_05T = 1,
1620 .trc = 19, .trc_05T = 0,
1621 .trfc = 119, .trfc_05T = 0,
1622 .trfcpb = 53, .trfcpb_05T = 1,
1623 .txp = 0, .txp_05T = 1,
1624 .trtp = 2, .trtp_05T = 0,
1625 .trcd = 8, .trcd_05T = 1,
1626 .twr = 13, .twr_05T = 1,
1627 .twtr = 8, .twtr_05T = 0,
1628 .tpbr2pbr = 35, .tpbr2pbr_05T = 0,
1629 .tpbr2act = 0, .tpbr2act_05T = 0,
1630 .tr2mrw = 15, .tr2mrw_05T = 1,
1631 .tw2mrw = 10, .tw2mrw_05T = 0,
1632 .tmrr2mrw = 12, .tmrr2mrw_05T = 1,
1633 .tmrw = 5, .tmrw_05T = 1,
1634 .tmrd = 7, .tmrd_05T = 1,
1635 .tmrwckel = 8, .tmrwckel_05T = 1,
1636 .tpde = 1, .tpde_05T = 1,
1637 .tpdx = 1, .tpdx_05T = 0,
1638 .tmrri = 12, .tmrri_05T = 0,
1639 .trrd = 4, .trrd_05T = 0,
1640 .trrd_4266 = 2, .trrd_4266_05T = 1,
1641 .tfaw = 11, .tfaw_05T = 0,
1642 .tfaw_4266 = 6, .tfaw_4266_05T = 0,
1643 .trtw_odt_off = 5, .trtw_odt_off_05T = 0,
1644 .trtw_odt_on = 8, .trtw_odt_on_05T = 0,
1645 .txrefcnt = 135,
1646 .tzqcs = 40,
1647 .xrtw2w_new_mode = 5,
1648 .xrtw2w_old_mode = 6,
1649 .xrtw2r_odt_on = 1,
1650 .xrtw2r_odt_off = 1,
1651 .xrtr2w_odt_on = 7,
1652 .xrtr2w_odt_off = 7,
1653 .xrtr2r_new_mode = 3,
1654 .xrtr2r_old_mode = 7,
1655 .tr2mrr = 4,
1656 .vrcgdis_prdcnt = 47,
1657 .hwset_mr2_op = 54,
1658 .hwset_mr13_op = 216,
1659 .hwset_vrcg_op = 208,
1660 .trcd_derate = 9, .trcd_derate_05T = 1,
1661 .trc_derate = 21, .trc_derate_05T = 1,
1662 .tras_derate = 12, .tras_derate_05T = 0,
1663 .trpab_derate = 9, .trpab_derate_05T = 1,
1664 .trp_derate = 8, .trp_derate_05T = 0,
1665 .trrd_derate = 5, .trrd_derate_05T = 0,
1666 .trtpd = 13, .trtpd_05T = 0,
1667 .twtpd = 16, .twtpd_05T = 1,
1668 .tmrr2w_odt_off = 9,
1669 .tmrr2w_odt_on = 11,
1670 .ckeprd = 3,
1671 .ckelckcnt = 3,
1672 .zqlat2 = 14,
1673
1674 //DQSINCTL, DATLAT aren't in ACTiming excel file
1675 .dqsinctl = 6, .datlat = 16
1676 },
1677 //LPDDR4 4X_3733_BT_Div 8_DBI0.csv Read 0
1678 {
1679 .dramType = TYPE_LPDDR4, .freq = 1866, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
1680 .readLat = 36, .writeLat = 16, .DivMode = DIV8_MODE,
1681
1682 .tras = 11, .tras_05T = 1,
1683 .trp = 7, .trp_05T = 0,
1684 .trpab = 8, .trpab_05T = 1,
1685 .trc = 19, .trc_05T = 0,
1686 .trfc = 119, .trfc_05T = 0,
1687 .trfcpb = 53, .trfcpb_05T = 1,
1688 .txp = 0, .txp_05T = 1,
1689 .trtp = 2, .trtp_05T = 0,
1690 .trcd = 8, .trcd_05T = 1,
1691 .twr = 14, .twr_05T = 1,
1692 .twtr = 9, .twtr_05T = 0,
1693 .tpbr2pbr = 35, .tpbr2pbr_05T = 0,
1694 .tpbr2act = 0, .tpbr2act_05T = 0,
1695 .tr2mrw = 16, .tr2mrw_05T = 1,
1696 .tw2mrw = 10, .tw2mrw_05T = 0,
1697 .tmrr2mrw = 13, .tmrr2mrw_05T = 1,
1698 .tmrw = 5, .tmrw_05T = 1,
1699 .tmrd = 7, .tmrd_05T = 1,
1700 .tmrwckel = 8, .tmrwckel_05T = 1,
1701 .tpde = 1, .tpde_05T = 1,
1702 .tpdx = 1, .tpdx_05T = 0,
1703 .tmrri = 12, .tmrri_05T = 0,
1704 .trrd = 4, .trrd_05T = 0,
1705 .trrd_4266 = 2, .trrd_4266_05T = 1,
1706 .tfaw = 11, .tfaw_05T = 0,
1707 .tfaw_4266 = 6, .tfaw_4266_05T = 0,
1708 .trtw_odt_off = 6, .trtw_odt_off_05T = 0,
1709 .trtw_odt_on = 9, .trtw_odt_on_05T = 0,
1710 .txrefcnt = 135,
1711 .tzqcs = 40,
1712 .xrtw2w_new_mode = 5,
1713 .xrtw2w_old_mode = 6,
1714 .xrtw2r_odt_on = 1,
1715 .xrtw2r_odt_off = 1,
1716 .xrtr2w_odt_on = 8,
1717 .xrtr2w_odt_off = 8,
1718 .xrtr2r_new_mode = 3,
1719 .xrtr2r_old_mode = 7,
1720 .tr2mrr = 4,
1721 .vrcgdis_prdcnt = 47,
1722 .hwset_mr2_op = 54,
1723 .hwset_mr13_op = 216,
1724 .hwset_vrcg_op = 208,
1725 .trcd_derate = 9, .trcd_derate_05T = 1,
1726 .trc_derate = 21, .trc_derate_05T = 1,
1727 .tras_derate = 12, .tras_derate_05T = 0,
1728 .trpab_derate = 9, .trpab_derate_05T = 1,
1729 .trp_derate = 8, .trp_derate_05T = 0,
1730 .trrd_derate = 5, .trrd_derate_05T = 0,
1731 .trtpd = 14, .trtpd_05T = 0,
1732 .twtpd = 17, .twtpd_05T = 1,
1733 .tmrr2w_odt_off = 10,
1734 .tmrr2w_odt_on = 12,
1735 .ckeprd = 3,
1736 .ckelckcnt = 3,
1737 .zqlat2 = 14,
1738
1739 //DQSINCTL, DATLAT aren't in ACTiming excel file
1740 .dqsinctl = 6, .datlat = 16
1741 },
1742 #endif
1743 #endif
1744 #if SUPPORT_LP4_DDR3200_ACTIM
1745 //LP4_DDR3200 ACTiming---------------------------------
1746 #if (ENABLE_READ_DBI == 1)
1747 //LPDDR4 4X_3200_Div 8_DBI1.csv Read 1
1748 {
1749 .dramType = TYPE_LPDDR4, .freq = 1600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1,
1750 .readLat = 32, .writeLat = 14, .DivMode = DIV8_MODE,
1751
1752 .tras = 8, .tras_05T = 1,
1753 .trp = 6, .trp_05T = 0,
1754 .trpab = 7, .trpab_05T = 0,
1755 .trc = 15, .trc_05T = 0,
1756 .trfc = 100, .trfc_05T = 0,
1757 .trfcpb = 44, .trfcpb_05T = 0,
1758 .txp = 0, .txp_05T = 0,
1759 .trtp = 1, .trtp_05T = 1,
1760 .trcd = 7, .trcd_05T = 1,
1761 .twr = 12, .twr_05T = 1,
1762 .twtr = 7, .twtr_05T = 0,
1763 .tpbr2pbr = 29, .tpbr2pbr_05T = 0,
1764 .tpbr2act = 0, .tpbr2act_05T = 0,
1765 .tr2mrw = 14, .tr2mrw_05T = 1,
1766 .tw2mrw = 9, .tw2mrw_05T = 0,
1767 .tmrr2mrw = 12, .tmrr2mrw_05T = 1,
1768 .tmrw = 4, .tmrw_05T = 1,
1769 .tmrd = 6, .tmrd_05T = 1,
1770 .tmrwckel = 7, .tmrwckel_05T = 1,
1771 .tpde = 1, .tpde_05T = 1,
1772 .tpdx = 1, .tpdx_05T = 0,
1773 .tmrri = 10, .tmrri_05T = 1,
1774 .trrd = 3, .trrd_05T = 0,
1775 .trrd_4266 = 2, .trrd_4266_05T = 0,
1776 .tfaw = 8, .tfaw_05T = 0,
1777 .tfaw_4266 = 4, .tfaw_4266_05T = 0,
1778 .trtw_odt_off = 5, .trtw_odt_off_05T = 0,
1779 .trtw_odt_on = 7, .trtw_odt_on_05T = 0,
1780 .txrefcnt = 115,
1781 .tzqcs = 34,
1782 .xrtw2w_new_mode = 4,
1783 .xrtw2w_old_mode = 6,
1784 .xrtw2r_odt_on = 1,
1785 .xrtw2r_odt_off = 1,
1786 .xrtr2w_odt_on = 6,
1787 .xrtr2w_odt_off = 6,
1788 .xrtr2r_new_mode = 3,
1789 .xrtr2r_old_mode = 7,
1790 .tr2mrr = 4,
1791 .vrcgdis_prdcnt = 40,
1792 .hwset_mr2_op = 45,
1793 .hwset_mr13_op = 216,
1794 .hwset_vrcg_op = 208,
1795 .trcd_derate = 8, .trcd_derate_05T = 0,
1796 .trc_derate = 17, .trc_derate_05T = 0,
1797 .tras_derate = 9, .tras_derate_05T = 1,
1798 .trpab_derate = 8, .trpab_derate_05T = 0,
1799 .trp_derate = 6, .trp_derate_05T = 1,
1800 .trrd_derate = 4, .trrd_derate_05T = 0,
1801 .trtpd = 13, .trtpd_05T = 0,
1802 .twtpd = 14, .twtpd_05T = 1,
1803 .tmrr2w_odt_off = 9,
1804 .tmrr2w_odt_on = 11,
1805 .ckeprd = 2,
1806 .ckelckcnt = 2,
1807 .zqlat2 = 12,
1808
1809 //DQSINCTL, DATLAT aren't in ACTiming excel file
1810 .dqsinctl = 5, .datlat = 15
1811 },
1812 //LPDDR4 4X_3200_BT_Div 8_DBI1.csv Read 1
1813 {
1814 .dramType = TYPE_LPDDR4, .freq = 1600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1,
1815 .readLat = 36, .writeLat = 14, .DivMode = DIV8_MODE,
1816
1817 .tras = 8, .tras_05T = 1,
1818 .trp = 6, .trp_05T = 0,
1819 .trpab = 7, .trpab_05T = 0,
1820 .trc = 15, .trc_05T = 0,
1821 .trfc = 100, .trfc_05T = 0,
1822 .trfcpb = 44, .trfcpb_05T = 0,
1823 .txp = 0, .txp_05T = 0,
1824 .trtp = 1, .trtp_05T = 1,
1825 .trcd = 7, .trcd_05T = 1,
1826 .twr = 12, .twr_05T = 1,
1827 .twtr = 8, .twtr_05T = 0,
1828 .tpbr2pbr = 29, .tpbr2pbr_05T = 0,
1829 .tpbr2act = 0, .tpbr2act_05T = 0,
1830 .tr2mrw = 15, .tr2mrw_05T = 1,
1831 .tw2mrw = 9, .tw2mrw_05T = 0,
1832 .tmrr2mrw = 13, .tmrr2mrw_05T = 1,
1833 .tmrw = 4, .tmrw_05T = 1,
1834 .tmrd = 6, .tmrd_05T = 1,
1835 .tmrwckel = 7, .tmrwckel_05T = 1,
1836 .tpde = 1, .tpde_05T = 1,
1837 .tpdx = 1, .tpdx_05T = 0,
1838 .tmrri = 10, .tmrri_05T = 1,
1839 .trrd = 3, .trrd_05T = 0,
1840 .trrd_4266 = 2, .trrd_4266_05T = 0,
1841 .tfaw = 8, .tfaw_05T = 0,
1842 .tfaw_4266 = 4, .tfaw_4266_05T = 0,
1843 .trtw_odt_off = 6, .trtw_odt_off_05T = 0,
1844 .trtw_odt_on = 8, .trtw_odt_on_05T = 0,
1845 .txrefcnt = 115,
1846 .tzqcs = 34,
1847 .xrtw2w_new_mode = 4,
1848 .xrtw2w_old_mode = 6,
1849 .xrtw2r_odt_on = 1,
1850 .xrtw2r_odt_off = 1,
1851 .xrtr2w_odt_on = 7,
1852 .xrtr2w_odt_off = 7,
1853 .xrtr2r_new_mode = 3,
1854 .xrtr2r_old_mode = 7,
1855 .tr2mrr = 4,
1856 .vrcgdis_prdcnt = 40,
1857 .hwset_mr2_op = 45,
1858 .hwset_mr13_op = 216,
1859 .hwset_vrcg_op = 208,
1860 .trcd_derate = 8, .trcd_derate_05T = 0,
1861 .trc_derate = 17, .trc_derate_05T = 0,
1862 .tras_derate = 9, .tras_derate_05T = 1,
1863 .trpab_derate = 8, .trpab_derate_05T = 0,
1864 .trp_derate = 6, .trp_derate_05T = 1,
1865 .trrd_derate = 4, .trrd_derate_05T = 0,
1866 .trtpd = 14, .trtpd_05T = 0,
1867 .twtpd = 15, .twtpd_05T = 1,
1868 .tmrr2w_odt_off = 10,
1869 .tmrr2w_odt_on = 12,
1870 .ckeprd = 2,
1871 .ckelckcnt = 2,
1872 .zqlat2 = 12,
1873
1874 //DQSINCTL, DATLAT aren't in ACTiming excel file
1875 .dqsinctl = 5, .datlat = 15
1876 },
1877 #else //ENABLE_READ_DBI == 0)
1878 //LPDDR4 4X_3200_Div 8_DBI0.csv Read 0
1879 {
1880 .dramType = TYPE_LPDDR4, .freq = 1600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
1881 .readLat = 28, .writeLat = 14, .DivMode = DIV8_MODE,
1882
1883 .tras = 8, .tras_05T = 1,
1884 .trp = 6, .trp_05T = 0,
1885 .trpab = 7, .trpab_05T = 0,
1886 .trc = 15, .trc_05T = 0,
1887 .trfc = 100, .trfc_05T = 0,
1888 .trfcpb = 44, .trfcpb_05T = 0,
1889 .txp = 0, .txp_05T = 0,
1890 .trtp = 1, .trtp_05T = 1,
1891 .trcd = 7, .trcd_05T = 1,
1892 .twr = 12, .twr_05T = 1,
1893 .twtr = 7, .twtr_05T = 0,
1894 .tpbr2pbr = 29, .tpbr2pbr_05T = 0,
1895 .tpbr2act = 0, .tpbr2act_05T = 0,
1896 .tr2mrw = 13, .tr2mrw_05T = 1,
1897 .tw2mrw = 9, .tw2mrw_05T = 0,
1898 .tmrr2mrw = 11, .tmrr2mrw_05T = 1,
1899 .tmrw = 4, .tmrw_05T = 1,
1900 .tmrd = 6, .tmrd_05T = 1,
1901 .tmrwckel = 7, .tmrwckel_05T = 1,
1902 .tpde = 1, .tpde_05T = 1,
1903 .tpdx = 1, .tpdx_05T = 0,
1904 .tmrri = 10, .tmrri_05T = 1,
1905 .trrd = 3, .trrd_05T = 0,
1906 .trrd_4266 = 2, .trrd_4266_05T = 0,
1907 .tfaw = 8, .tfaw_05T = 0,
1908 .tfaw_4266 = 4, .tfaw_4266_05T = 0,
1909 .trtw_odt_off = 4, .trtw_odt_off_05T = 0,
1910 .trtw_odt_on = 6, .trtw_odt_on_05T = 0,
1911 .txrefcnt = 115,
1912 .tzqcs = 34,
1913 .xrtw2w_new_mode = 4,
1914 .xrtw2w_old_mode = 6,
1915 .xrtw2r_odt_on = 1,
1916 .xrtw2r_odt_off = 1,
1917 .xrtr2w_odt_on = 5,
1918 .xrtr2w_odt_off = 5,
1919 .xrtr2r_new_mode = 3,
1920 .xrtr2r_old_mode = 7,
1921 .tr2mrr = 4,
1922 .vrcgdis_prdcnt = 40,
1923 .hwset_mr2_op = 45,
1924 .hwset_mr13_op = 216,
1925 .hwset_vrcg_op = 208,
1926 .trcd_derate = 8, .trcd_derate_05T = 0,
1927 .trc_derate = 17, .trc_derate_05T = 0,
1928 .tras_derate = 9, .tras_derate_05T = 1,
1929 .trpab_derate = 8, .trpab_derate_05T = 0,
1930 .trp_derate = 6, .trp_derate_05T = 1,
1931 .trrd_derate = 4, .trrd_derate_05T = 0,
1932 .trtpd = 12, .trtpd_05T = 0,
1933 .twtpd = 14, .twtpd_05T = 1,
1934 .tmrr2w_odt_off = 8,
1935 .tmrr2w_odt_on = 10,
1936 .ckeprd = 2,
1937 .ckelckcnt = 2,
1938 .zqlat2 = 12,
1939
1940 //DQSINCTL, DATLAT aren't in ACTiming excel file
1941 .dqsinctl = 5, .datlat = 15
1942 },
1943 //LPDDR4 4X_3200_BT_Div 8_DBI0.csv Read 0
1944 {
1945 .dramType = TYPE_LPDDR4, .freq = 1600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
1946 .readLat = 32, .writeLat = 14, .DivMode = DIV8_MODE,
1947
1948 .tras = 8, .tras_05T = 1,
1949 .trp = 6, .trp_05T = 0,
1950 .trpab = 7, .trpab_05T = 0,
1951 .trc = 15, .trc_05T = 0,
1952 .trfc = 100, .trfc_05T = 0,
1953 .trfcpb = 44, .trfcpb_05T = 0,
1954 .txp = 0, .txp_05T = 0,
1955 .trtp = 1, .trtp_05T = 1,
1956 .trcd = 7, .trcd_05T = 1,
1957 .twr = 12, .twr_05T = 1,
1958 .twtr = 8, .twtr_05T = 0,
1959 .tpbr2pbr = 29, .tpbr2pbr_05T = 0,
1960 .tpbr2act = 0, .tpbr2act_05T = 0,
1961 .tr2mrw = 14, .tr2mrw_05T = 1,
1962 .tw2mrw = 9, .tw2mrw_05T = 0,
1963 .tmrr2mrw = 12, .tmrr2mrw_05T = 1,
1964 .tmrw = 4, .tmrw_05T = 1,
1965 .tmrd = 6, .tmrd_05T = 1,
1966 .tmrwckel = 7, .tmrwckel_05T = 1,
1967 .tpde = 1, .tpde_05T = 1,
1968 .tpdx = 1, .tpdx_05T = 0,
1969 .tmrri = 10, .tmrri_05T = 1,
1970 .trrd = 3, .trrd_05T = 0,
1971 .trrd_4266 = 2, .trrd_4266_05T = 0,
1972 .tfaw = 8, .tfaw_05T = 0,
1973 .tfaw_4266 = 4, .tfaw_4266_05T = 0,
1974 .trtw_odt_off = 5, .trtw_odt_off_05T = 0,
1975 .trtw_odt_on = 7, .trtw_odt_on_05T = 0,
1976 .txrefcnt = 115,
1977 .tzqcs = 34,
1978 .xrtw2w_new_mode = 4,
1979 .xrtw2w_old_mode = 6,
1980 .xrtw2r_odt_on = 1,
1981 .xrtw2r_odt_off = 1,
1982 .xrtr2w_odt_on = 6,
1983 .xrtr2w_odt_off = 6,
1984 .xrtr2r_new_mode = 3,
1985 .xrtr2r_old_mode = 7,
1986 .tr2mrr = 4,
1987 .vrcgdis_prdcnt = 40,
1988 .hwset_mr2_op = 45,
1989 .hwset_mr13_op = 216,
1990 .hwset_vrcg_op = 208,
1991 .trcd_derate = 8, .trcd_derate_05T = 0,
1992 .trc_derate = 17, .trc_derate_05T = 0,
1993 .tras_derate = 9, .tras_derate_05T = 1,
1994 .trpab_derate = 8, .trpab_derate_05T = 0,
1995 .trp_derate = 6, .trp_derate_05T = 1,
1996 .trrd_derate = 4, .trrd_derate_05T = 0,
1997 .trtpd = 13, .trtpd_05T = 0,
1998 .twtpd = 15, .twtpd_05T = 1,
1999 .tmrr2w_odt_off = 9,
2000 .tmrr2w_odt_on = 11,
2001 .ckeprd = 2,
2002 .ckelckcnt = 2,
2003 .zqlat2 = 12,
2004
2005 //DQSINCTL, DATLAT aren't in ACTiming excel file
2006 .dqsinctl = 5, .datlat = 15
2007 },
2008 #endif
2009 #endif
2010 #if SUPPORT_LP4_DDR2667_ACTIM
2011 //LP4_DDR2667 ACTiming---------------------------------
2012 //LPDDR4 4X_2667_Div 8_DBI0.csv Read 0
2013 {
2014 .dramType = TYPE_LPDDR4, .freq = 1333, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
2015 .readLat = 24, .writeLat = 12, .DivMode = DIV8_MODE,
2016
2017 .tras = 6, .tras_05T = 0,
2018 .trp = 5, .trp_05T = 0,
2019 .trpab = 6, .trpab_05T = 0,
2020 .trc = 11, .trc_05T = 1,
2021 .trfc = 81, .trfc_05T = 1,
2022 .trfcpb = 35, .trfcpb_05T = 0,
2023 .txp = 0, .txp_05T = 0,
2024 .trtp = 1, .trtp_05T = 1,
2025 .trcd = 6, .trcd_05T = 1,
2026 .twr = 10, .twr_05T = 0,
2027 .twtr = 6, .twtr_05T = 0,
2028 .tpbr2pbr = 23, .tpbr2pbr_05T = 1,
2029 .tpbr2act = 0, .tpbr2act_05T = 0,
2030 .tr2mrw = 12, .tr2mrw_05T = 0,
2031 .tw2mrw = 8, .tw2mrw_05T = 0,
2032 .tmrr2mrw = 10, .tmrr2mrw_05T = 0,
2033 .tmrw = 4, .tmrw_05T = 0,
2034 .tmrd = 5, .tmrd_05T = 1,
2035 .tmrwckel = 6, .tmrwckel_05T = 1,
2036 .tpde = 1, .tpde_05T = 1,
2037 .tpdx = 1, .tpdx_05T = 0,
2038 .tmrri = 9, .tmrri_05T = 0,
2039 .trrd = 2, .trrd_05T = 1,
2040 .trrd_4266 = 2, .trrd_4266_05T = 0,
2041 .tfaw = 5, .tfaw_05T = 1,
2042 .tfaw_4266 = 2, .tfaw_4266_05T = 1,
2043 .trtw_odt_off = 3, .trtw_odt_off_05T = 0,
2044 .trtw_odt_on = 6, .trtw_odt_on_05T = 0,
2045 .txrefcnt = 96,
2046 .tzqcs = 29,
2047 .xrtw2w_new_mode = 4,
2048 .xrtw2w_old_mode = 6,
2049 .xrtw2r_odt_on = 1,
2050 .xrtw2r_odt_off = 1,
2051 .xrtr2w_odt_on = 5,
2052 .xrtr2w_odt_off = 5,
2053 .xrtr2r_new_mode = 3,
2054 .xrtr2r_old_mode = 6,
2055 .tr2mrr = 4,
2056 .vrcgdis_prdcnt = 34,
2057 .hwset_mr2_op = 36,
2058 .hwset_mr13_op = 216,
2059 .hwset_vrcg_op = 208,
2060 .trcd_derate = 7, .trcd_derate_05T = 0,
2061 .trc_derate = 13, .trc_derate_05T = 0,
2062 .tras_derate = 6, .tras_derate_05T = 1,
2063 .trpab_derate = 6, .trpab_derate_05T = 1,
2064 .trp_derate = 5, .trp_derate_05T = 1,
2065 .trrd_derate = 3, .trrd_derate_05T = 0,
2066 .trtpd = 10, .trtpd_05T = 1,
2067 .twtpd = 13, .twtpd_05T = 0,
2068 .tmrr2w_odt_off = 6,
2069 .tmrr2w_odt_on = 8,
2070 .ckeprd = 2,
2071 .ckelckcnt = 2,
2072 .zqlat2 = 11,
2073
2074 //DQSINCTL, DATLAT aren't in ACTiming excel file
2075 .dqsinctl = TBD, .datlat = TBD
2076 },
2077 //LPDDR4 4X_2667_BT_Div 8_DBI0.csv Read 0
2078 {
2079 .dramType = TYPE_LPDDR4, .freq = 1333, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
2080 .readLat = 26, .writeLat = 12, .DivMode = DIV8_MODE,
2081
2082 .tras = 6, .tras_05T = 0,
2083 .trp = 5, .trp_05T = 0,
2084 .trpab = 6, .trpab_05T = 0,
2085 .trc = 11, .trc_05T = 1,
2086 .trfc = 81, .trfc_05T = 1,
2087 .trfcpb = 35, .trfcpb_05T = 0,
2088 .txp = 0, .txp_05T = 0,
2089 .trtp = 1, .trtp_05T = 1,
2090 .trcd = 6, .trcd_05T = 1,
2091 .twr = 11, .twr_05T = 1,
2092 .twtr = 7, .twtr_05T = 1,
2093 .tpbr2pbr = 23, .tpbr2pbr_05T = 1,
2094 .tpbr2act = 0, .tpbr2act_05T = 0,
2095 .tr2mrw = 12, .tr2mrw_05T = 1,
2096 .tw2mrw = 8, .tw2mrw_05T = 0,
2097 .tmrr2mrw = 10, .tmrr2mrw_05T = 1,
2098 .tmrw = 4, .tmrw_05T = 0,
2099 .tmrd = 5, .tmrd_05T = 1,
2100 .tmrwckel = 6, .tmrwckel_05T = 1,
2101 .tpde = 1, .tpde_05T = 1,
2102 .tpdx = 1, .tpdx_05T = 0,
2103 .tmrri = 9, .tmrri_05T = 0,
2104 .trrd = 2, .trrd_05T = 1,
2105 .trrd_4266 = 2, .trrd_4266_05T = 0,
2106 .tfaw = 5, .tfaw_05T = 1,
2107 .tfaw_4266 = 2, .tfaw_4266_05T = 1,
2108 .trtw_odt_off = 4, .trtw_odt_off_05T = 0,
2109 .trtw_odt_on = 6, .trtw_odt_on_05T = 0,
2110 .txrefcnt = 96,
2111 .tzqcs = 29,
2112 .xrtw2w_new_mode = 4,
2113 .xrtw2w_old_mode = 6,
2114 .xrtw2r_odt_on = 1,
2115 .xrtw2r_odt_off = 1,
2116 .xrtr2w_odt_on = 5,
2117 .xrtr2w_odt_off = 5,
2118 .xrtr2r_new_mode = 3,
2119 .xrtr2r_old_mode = 6,
2120 .tr2mrr = 4,
2121 .vrcgdis_prdcnt = 34,
2122 .hwset_mr2_op = 36,
2123 .hwset_mr13_op = 216,
2124 .hwset_vrcg_op = 208,
2125 .trcd_derate = 7, .trcd_derate_05T = 0,
2126 .trc_derate = 13, .trc_derate_05T = 0,
2127 .tras_derate = 6, .tras_derate_05T = 1,
2128 .trpab_derate = 6, .trpab_derate_05T = 1,
2129 .trp_derate = 5, .trp_derate_05T = 1,
2130 .trrd_derate = 3, .trrd_derate_05T = 0,
2131 .trtpd = 11, .trtpd_05T = 0,
2132 .twtpd = 13, .twtpd_05T = 1,
2133 .tmrr2w_odt_off = 7,
2134 .tmrr2w_odt_on = 9,
2135 .ckeprd = 2,
2136 .ckelckcnt = 2,
2137 .zqlat2 = 11,
2138
2139 //DQSINCTL, DATLAT aren't in ACTiming excel file
2140 .dqsinctl = TBD, .datlat = TBD
2141 },
2142 #endif
2143 #if SUPPORT_LP4_DDR2400_ACTIM
2144 //LP4_DDR2400 ACTiming---------------------------------
2145 //LPDDR4 4X_2400_Div 8_DBI0.csv Read 0
2146 {
2147 .dramType = TYPE_LPDDR4, .freq = 1200, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
2148 .readLat = 24, .writeLat = 12, .DivMode = DIV8_MODE,
2149
2150 .tras = 4, .tras_05T = 1,
2151 .trp = 4, .trp_05T = 0,
2152 .trpab = 5, .trpab_05T = 0,
2153 .trc = 9, .trc_05T = 1,
2154 .trfc = 72, .trfc_05T = 1,
2155 .trfcpb = 30, .trfcpb_05T = 1,
2156 .txp = 0, .txp_05T = 1,
2157 .trtp = 1, .trtp_05T = 0,
2158 .trcd = 5, .trcd_05T = 1,
2159 .twr = 9, .twr_05T = 1,
2160 .twtr = 6, .twtr_05T = 1,
2161 .tpbr2pbr = 20, .tpbr2pbr_05T = 1,
2162 .tpbr2act = 0, .tpbr2act_05T = 0,
2163 .tr2mrw = 12, .tr2mrw_05T = 0,
2164 .tw2mrw = 8, .tw2mrw_05T = 0,
2165 .tmrr2mrw = 10, .tmrr2mrw_05T = 0,
2166 .tmrw = 4, .tmrw_05T = 0,
2167 .tmrd = 5, .tmrd_05T = 0,
2168 .tmrwckel = 6, .tmrwckel_05T = 0,
2169 .tpde = 1, .tpde_05T = 1,
2170 .tpdx = 1, .tpdx_05T = 0,
2171 .tmrri = 8, .tmrri_05T = 0,
2172 .trrd = 2, .trrd_05T = 1,
2173 .trrd_4266 = 1, .trrd_4266_05T = 1,
2174 .tfaw = 4, .tfaw_05T = 1,
2175 .tfaw_4266 = 1, .tfaw_4266_05T = 1,
2176 .trtw_odt_off = 3, .trtw_odt_off_05T = 0,
2177 .trtw_odt_on = 6, .trtw_odt_on_05T = 0,
2178 .txrefcnt = 87,
2179 .tzqcs = 26,
2180 .xrtw2w_new_mode = 4,
2181 .xrtw2w_old_mode = 6,
2182 .xrtw2r_odt_on = 2,
2183 .xrtw2r_odt_off = 2,
2184 .xrtr2w_odt_on = 5,
2185 .xrtr2w_odt_off = 5,
2186 .xrtr2r_new_mode = 3,
2187 .xrtr2r_old_mode = 6,
2188 .tr2mrr = 4,
2189 .vrcgdis_prdcnt = 31,
2190 .hwset_mr2_op = 36,
2191 .hwset_mr13_op = 24,
2192 .hwset_vrcg_op = 16,
2193 .trcd_derate = 6, .trcd_derate_05T = 0,
2194 .trc_derate = 10, .trc_derate_05T = 1,
2195 .tras_derate = 5, .tras_derate_05T = 0,
2196 .trpab_derate = 5, .trpab_derate_05T = 1,
2197 .trp_derate = 4, .trp_derate_05T = 1,
2198 .trrd_derate = 3, .trrd_derate_05T = 0,
2199 .trtpd = 10, .trtpd_05T = 1,
2200 .twtpd = 12, .twtpd_05T = 0,
2201 .tmrr2w_odt_off = 6,
2202 .tmrr2w_odt_on = 8,
2203 .ckeprd = 2,
2204 .ckelckcnt = 2,
2205 .zqlat2 = 10,
2206
2207 //DQSINCTL, DATLAT aren't in ACTiming excel file
2208 .dqsinctl = 4, .datlat = 13
2209 },
2210 //LPDDR4 4X_2400_BT_Div 8_DBI0.csv Read 0
2211 {
2212 .dramType = TYPE_LPDDR4, .freq = 1200, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
2213 .readLat = 26, .writeLat = 12, .DivMode = DIV8_MODE,
2214
2215 .tras = 4, .tras_05T = 1,
2216 .trp = 4, .trp_05T = 0,
2217 .trpab = 5, .trpab_05T = 0,
2218 .trc = 9, .trc_05T = 1,
2219 .trfc = 72, .trfc_05T = 1,
2220 .trfcpb = 30, .trfcpb_05T = 1,
2221 .txp = 0, .txp_05T = 1,
2222 .trtp = 1, .trtp_05T = 0,
2223 .trcd = 5, .trcd_05T = 1,
2224 .twr = 10, .twr_05T = 0,
2225 .twtr = 6, .twtr_05T = 0,
2226 .tpbr2pbr = 20, .tpbr2pbr_05T = 1,
2227 .tpbr2act = 0, .tpbr2act_05T = 0,
2228 .tr2mrw = 12, .tr2mrw_05T = 1,
2229 .tw2mrw = 8, .tw2mrw_05T = 0,
2230 .tmrr2mrw = 10, .tmrr2mrw_05T = 1,
2231 .tmrw = 4, .tmrw_05T = 0,
2232 .tmrd = 5, .tmrd_05T = 0,
2233 .tmrwckel = 6, .tmrwckel_05T = 0,
2234 .tpde = 1, .tpde_05T = 1,
2235 .tpdx = 1, .tpdx_05T = 0,
2236 .tmrri = 8, .tmrri_05T = 0,
2237 .trrd = 2, .trrd_05T = 1,
2238 .trrd_4266 = 1, .trrd_4266_05T = 1,
2239 .tfaw = 4, .tfaw_05T = 1,
2240 .tfaw_4266 = 1, .tfaw_4266_05T = 1,
2241 .trtw_odt_off = 4, .trtw_odt_off_05T = 0,
2242 .trtw_odt_on = 6, .trtw_odt_on_05T = 0,
2243 .txrefcnt = 87,
2244 .tzqcs = 26,
2245 .xrtw2w_new_mode = 4,
2246 .xrtw2w_old_mode = 6,
2247 .xrtw2r_odt_on = 1,
2248 .xrtw2r_odt_off = 1,
2249 .xrtr2w_odt_on = 5,
2250 .xrtr2w_odt_off = 5,
2251 .xrtr2r_new_mode = 3,
2252 .xrtr2r_old_mode = 6,
2253 .tr2mrr = 4,
2254 .vrcgdis_prdcnt = 31,
2255 .hwset_mr2_op = 36,
2256 .hwset_mr13_op = 24,
2257 .hwset_vrcg_op = 16,
2258 .trcd_derate = 6, .trcd_derate_05T = 0,
2259 .trc_derate = 10, .trc_derate_05T = 1,
2260 .tras_derate = 5, .tras_derate_05T = 0,
2261 .trpab_derate = 5, .trpab_derate_05T = 1,
2262 .trp_derate = 4, .trp_derate_05T = 1,
2263 .trrd_derate = 3, .trrd_derate_05T = 0,
2264 .trtpd = 11, .trtpd_05T = 0,
2265 .twtpd = 13, .twtpd_05T = 0,
2266 .tmrr2w_odt_off = 7,
2267 .tmrr2w_odt_on = 9,
2268 .ckeprd = 2,
2269 .ckelckcnt = 2,
2270 .zqlat2 = 10,
2271
2272 //DQSINCTL, DATLAT aren't in ACTiming excel file
2273 .dqsinctl = 4, .datlat = 13
2274 },
2275 #endif
2276 #if SUPPORT_LP4_DDR1866_ACTIM
2277 //LP4_DDR1866 ACTiming---------------------------------
2278 //LPDDR4 4X_1866_Div 8_DBI0.csv Read 0
2279 {
2280 .dramType = TYPE_LPDDR4, .freq = 933, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
2281 .readLat = 20, .writeLat = 10, .DivMode = DIV8_MODE,
2282
2283 .tras = 1, .tras_05T = 1,
2284 .trp = 3, .trp_05T = 0,
2285 .trpab = 3, .trpab_05T = 1,
2286 .trc = 5, .trc_05T = 0,
2287 .trfc = 53, .trfc_05T = 1,
2288 .trfcpb = 21, .trfcpb_05T = 0,
2289 .txp = 0, .txp_05T = 0,
2290 .trtp = 0, .trtp_05T = 1,
2291 .trcd = 4, .trcd_05T = 1,
2292 .twr = 8, .twr_05T = 1,
2293 .twtr = 5, .twtr_05T = 1,
2294 .tpbr2pbr = 14, .tpbr2pbr_05T = 0,
2295 .tpbr2act = 0, .tpbr2act_05T = 0,
2296 .tr2mrw = 10, .tr2mrw_05T = 0,
2297 .tw2mrw = 7, .tw2mrw_05T = 0,
2298 .tmrr2mrw = 9, .tmrr2mrw_05T = 0,
2299 .tmrw = 3, .tmrw_05T = 0,
2300 .tmrd = 4, .tmrd_05T = 0,
2301 .tmrwckel = 5, .tmrwckel_05T = 0,
2302 .tpde = 1, .tpde_05T = 1,
2303 .tpdx = 1, .tpdx_05T = 0,
2304 .tmrri = 6, .tmrri_05T = 0,
2305 .trrd = 1, .trrd_05T = 1,
2306 .trrd_4266 = 1, .trrd_4266_05T = 0,
2307 .tfaw = 1, .tfaw_05T = 1,
2308 .tfaw_4266 = 0, .tfaw_4266_05T = 0,
2309 .trtw_odt_off = 3, .trtw_odt_off_05T = 0,
2310 .trtw_odt_on = 5, .trtw_odt_on_05T = 0,
2311 .txrefcnt = 68,
2312 .tzqcs = 19,
2313 .xrtw2w_new_mode = 4,
2314 .xrtw2w_old_mode = 6,
2315 .xrtw2r_odt_on = 2,
2316 .xrtw2r_odt_off = 2,
2317 .xrtr2w_odt_on = 3,
2318 .xrtr2w_odt_off = 3,
2319 .xrtr2r_new_mode = 3,
2320 .xrtr2r_old_mode = 6,
2321 .tr2mrr = 4,
2322 .vrcgdis_prdcnt = 24,
2323 .hwset_mr2_op = 27,
2324 .hwset_mr13_op = 24,
2325 .hwset_vrcg_op = 16,
2326 .trcd_derate = 5, .trcd_derate_05T = 0,
2327 .trc_derate = 6, .trc_derate_05T = 1,
2328 .tras_derate = 2, .tras_derate_05T = 0,
2329 .trpab_derate = 4, .trpab_derate_05T = 0,
2330 .trp_derate = 3, .trp_derate_05T = 1,
2331 .trrd_derate = 2, .trrd_derate_05T = 0,
2332 .trtpd = 9, .trtpd_05T = 1,
2333 .twtpd = 10, .twtpd_05T = 1,
2334 .tmrr2w_odt_off = 5,
2335 .tmrr2w_odt_on = 7,
2336 .ckeprd = 1,
2337 .ckelckcnt = 2,
2338 .zqlat2 = 7,
2339
2340 //DQSINCTL, DATLAT aren't in ACTiming excel file
2341 .dqsinctl = 3, .datlat = 13
2342 },
2343 //LPDDR4 4X_1866_BT_Div 8_DBI0.csv Read 0
2344 {
2345 .dramType = TYPE_LPDDR4, .freq = 933, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
2346 .readLat = 22, .writeLat = 10, .DivMode = DIV8_MODE,
2347
2348 .tras = 1, .tras_05T = 1,
2349 .trp = 3, .trp_05T = 0,
2350 .trpab = 3, .trpab_05T = 1,
2351 .trc = 5, .trc_05T = 0,
2352 .trfc = 53, .trfc_05T = 1,
2353 .trfcpb = 21, .trfcpb_05T = 0,
2354 .txp = 0, .txp_05T = 0,
2355 .trtp = 0, .trtp_05T = 1,
2356 .trcd = 4, .trcd_05T = 1,
2357 .twr = 8, .twr_05T = 0,
2358 .twtr = 5, .twtr_05T = 0,
2359 .tpbr2pbr = 14, .tpbr2pbr_05T = 0,
2360 .tpbr2act = 0, .tpbr2act_05T = 0,
2361 .tr2mrw = 10, .tr2mrw_05T = 1,
2362 .tw2mrw = 7, .tw2mrw_05T = 0,
2363 .tmrr2mrw = 9, .tmrr2mrw_05T = 1,
2364 .tmrw = 3, .tmrw_05T = 0,
2365 .tmrd = 4, .tmrd_05T = 0,
2366 .tmrwckel = 5, .tmrwckel_05T = 0,
2367 .tpde = 1, .tpde_05T = 1,
2368 .tpdx = 1, .tpdx_05T = 0,
2369 .tmrri = 6, .tmrri_05T = 0,
2370 .trrd = 1, .trrd_05T = 1,
2371 .trrd_4266 = 1, .trrd_4266_05T = 0,
2372 .tfaw = 1, .tfaw_05T = 1,
2373 .tfaw_4266 = 0, .tfaw_4266_05T = 0,
2374 .trtw_odt_off = 3, .trtw_odt_off_05T = 0,
2375 .trtw_odt_on = 5, .trtw_odt_on_05T = 0,
2376 .txrefcnt = 68,
2377 .tzqcs = 19,
2378 .xrtw2w_new_mode = 4,
2379 .xrtw2w_old_mode = 6,
2380 .xrtw2r_odt_on = 2,
2381 .xrtw2r_odt_off = 1,
2382 .xrtr2w_odt_on = 4,
2383 .xrtr2w_odt_off = 4,
2384 .xrtr2r_new_mode = 3,
2385 .xrtr2r_old_mode = 6,
2386 .tr2mrr = 4,
2387 .vrcgdis_prdcnt = 24,
2388 .hwset_mr2_op = 27,
2389 .hwset_mr13_op = 24,
2390 .hwset_vrcg_op = 16,
2391 .trcd_derate = 5, .trcd_derate_05T = 0,
2392 .trc_derate = 6, .trc_derate_05T = 1,
2393 .tras_derate = 2, .tras_derate_05T = 0,
2394 .trpab_derate = 4, .trpab_derate_05T = 0,
2395 .trp_derate = 3, .trp_derate_05T = 1,
2396 .trrd_derate = 2, .trrd_derate_05T = 0,
2397 .trtpd = 10, .trtpd_05T = 0,
2398 .twtpd = 11, .twtpd_05T = 0,
2399 .tmrr2w_odt_off = 6,
2400 .tmrr2w_odt_on = 8,
2401 .ckeprd = 1,
2402 .ckelckcnt = 2,
2403 .zqlat2 = 7,
2404
2405 //DQSINCTL, DATLAT aren't in ACTiming excel file
2406 .dqsinctl = 3, .datlat = 13
2407 },
2408 #endif
2409 #if SUPPORT_LP4_DDR1600_ACTIM
2410 //LP4_DDR1600 ACTiming---------------------------------
2411 //LPDDR4 4X_1600_Div 4_DBI0.csv Read 0
2412 {
2413 .dramType = TYPE_LPDDR4, .freq = 800, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
2414 .readLat = 14, .writeLat = 8, .DivMode = DIV4_MODE,
2415
2416 .tras = 9, .tras_05T = 0,
2417 .trp = 6, .trp_05T = 0,
2418 .trpab = 7, .trpab_05T = 0,
2419 .trc = 15, .trc_05T = 0,
2420 .trfc = 100, .trfc_05T = 0,
2421 .trfcpb = 44, .trfcpb_05T = 0,
2422 .txp = 0, .txp_05T = 0,
2423 .trtp = 3, .trtp_05T = 0,
2424 .trcd = 8, .trcd_05T = 0,
2425 .twr = 15, .twr_05T = 0,
2426 .twtr = 10, .twtr_05T = 0,
2427 .tpbr2pbr = 29, .tpbr2pbr_05T = 0,
2428 .tpbr2act = 0, .tpbr2act_05T = 0,
2429 .tr2mrw = 17, .tr2mrw_05T = 0,
2430 .tw2mrw = 13, .tw2mrw_05T = 0,
2431 .tmrr2mrw = 14, .tmrr2mrw_05T = 0,
2432 .tmrw = 6, .tmrw_05T = 0,
2433 .tmrd = 7, .tmrd_05T = 0,
2434 .tmrwckel = 9, .tmrwckel_05T = 0,
2435 .tpde = 3, .tpde_05T = 0,
2436 .tpdx = 3, .tpdx_05T = 0,
2437 .tmrri = 11, .tmrri_05T = 0,
2438 .trrd = 3, .trrd_05T = 0,
2439 .trrd_4266 = 2, .trrd_4266_05T = 0,
2440 .tfaw = 8, .tfaw_05T = 0,
2441 .tfaw_4266 = 4, .tfaw_4266_05T = 0,
2442 .trtw_odt_off = 7, .trtw_odt_off_05T = 0,
2443 .trtw_odt_on = 11, .trtw_odt_on_05T = 0,
2444 .txrefcnt = 115,
2445 .tzqcs = 34,
2446 .xrtw2w_new_mode = 9,
2447 .xrtw2w_old_mode = 10,
2448 .xrtw2r_odt_on = 7,
2449 .xrtw2r_odt_off = 6,
2450 .xrtr2w_odt_on = 10,
2451 .xrtr2w_odt_off = 10,
2452 .xrtr2r_new_mode = 7,
2453 .xrtr2r_old_mode = 9,
2454 .tr2mrr = 8,
2455 .vrcgdis_prdcnt = 40,
2456 .hwset_mr2_op = 18,
2457 .hwset_mr13_op = 24,
2458 .hwset_vrcg_op = 16,
2459 .trcd_derate = 8, .trcd_derate_05T = 0,
2460 .trc_derate = 17, .trc_derate_05T = 0,
2461 .tras_derate = 10, .tras_derate_05T = 0,
2462 .trpab_derate = 8, .trpab_derate_05T = 0,
2463 .trp_derate = 6, .trp_derate_05T = 0,
2464 .trrd_derate = 4, .trrd_derate_05T = 0,
2465 .trtpd = 15, .trtpd_05T = 0,
2466 .twtpd = 19, .twtpd_05T = 0,
2467 .tmrr2w_odt_off = 10,
2468 .tmrr2w_odt_on = 12,
2469 .ckeprd = 2,
2470 .ckelckcnt = 3,
2471 .zqlat2 = 12,
2472
2473 //DQSINCTL, DATLAT aren't in ACTiming excel file
2474 .dqsinctl = 2, .datlat = 10
2475 },
2476 //LPDDR4 4X_1600_BT_Div 4_DBI0.csv Read 0
2477 {
2478 .dramType = TYPE_LPDDR4, .freq = 800, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
2479 .readLat = 16, .writeLat = 8, .DivMode = DIV4_MODE,
2480
2481 .tras = 9, .tras_05T = 0,
2482 .trp = 6, .trp_05T = 0,
2483 .trpab = 7, .trpab_05T = 0,
2484 .trc = 15, .trc_05T = 0,
2485 .trfc = 100, .trfc_05T = 0,
2486 .trfcpb = 44, .trfcpb_05T = 0,
2487 .txp = 0, .txp_05T = 0,
2488 .trtp = 3, .trtp_05T = 0,
2489 .trcd = 8, .trcd_05T = 0,
2490 .twr = 16, .twr_05T = 0,
2491 .twtr = 11, .twtr_05T = 0,
2492 .tpbr2pbr = 29, .tpbr2pbr_05T = 0,
2493 .tpbr2act = 0, .tpbr2act_05T = 0,
2494 .tr2mrw = 18, .tr2mrw_05T = 0,
2495 .tw2mrw = 13, .tw2mrw_05T = 0,
2496 .tmrr2mrw = 15, .tmrr2mrw_05T = 0,
2497 .tmrw = 6, .tmrw_05T = 0,
2498 .tmrd = 7, .tmrd_05T = 0,
2499 .tmrwckel = 9, .tmrwckel_05T = 0,
2500 .tpde = 3, .tpde_05T = 0,
2501 .tpdx = 3, .tpdx_05T = 0,
2502 .tmrri = 11, .tmrri_05T = 0,
2503 .trrd = 3, .trrd_05T = 0,
2504 .trrd_4266 = 2, .trrd_4266_05T = 0,
2505 .tfaw = 8, .tfaw_05T = 0,
2506 .tfaw_4266 = 4, .tfaw_4266_05T = 0,
2507 .trtw_odt_off = 8, .trtw_odt_off_05T = 0,
2508 .trtw_odt_on = 12, .trtw_odt_on_05T = 0,
2509 .txrefcnt = 115,
2510 .tzqcs = 34,
2511 .xrtw2w_new_mode = 9,
2512 .xrtw2w_old_mode = 10,
2513 .xrtw2r_odt_on = 6,
2514 .xrtw2r_odt_off = 5,
2515 .xrtr2w_odt_on = 11,
2516 .xrtr2w_odt_off = 11,
2517 .xrtr2r_new_mode = 7,
2518 .xrtr2r_old_mode = 10,
2519 .tr2mrr = 8,
2520 .vrcgdis_prdcnt = 40,
2521 .hwset_mr2_op = 18,
2522 .hwset_mr13_op = 24,
2523 .hwset_vrcg_op = 16,
2524 .trcd_derate = 8, .trcd_derate_05T = 0,
2525 .trc_derate = 17, .trc_derate_05T = 0,
2526 .tras_derate = 10, .tras_derate_05T = 0,
2527 .trpab_derate = 8, .trpab_derate_05T = 0,
2528 .trp_derate = 6, .trp_derate_05T = 0,
2529 .trrd_derate = 4, .trrd_derate_05T = 0,
2530 .trtpd = 16, .trtpd_05T = 0,
2531 .twtpd = 19, .twtpd_05T = 0,
2532 .tmrr2w_odt_off = 11,
2533 .tmrr2w_odt_on = 13,
2534 .ckeprd = 2,
2535 .ckelckcnt = 3,
2536 .zqlat2 = 12,
2537
2538 //DQSINCTL, DATLAT aren't in ACTiming excel file
2539 .dqsinctl = 2, .datlat = 10
2540 },
2541 //LPDDR4 4X_1600_Div 8_DBI0.csv Read 0
2542 {
2543 .dramType = TYPE_LPDDR4, .freq = 800, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
2544 .readLat = 14, .writeLat = 8, .DivMode = DIV8_MODE,
2545
2546 .tras = 0, .tras_05T = 0,
2547 .trp = 2, .trp_05T = 1,
2548 .trpab = 3, .trpab_05T = 0,
2549 .trc = 3, .trc_05T = 0,
2550 .trfc = 44, .trfc_05T = 0,
2551 .trfcpb = 16, .trfcpb_05T = 0,
2552 .txp = 0, .txp_05T = 0,
2553 .trtp = 0, .trtp_05T = 1,
2554 .trcd = 4, .trcd_05T = 0,
2555 .twr = 7, .twr_05T = 1,
2556 .twtr = 4, .twtr_05T = 1,
2557 .tpbr2pbr = 11, .tpbr2pbr_05T = 0,
2558 .tpbr2act = 0, .tpbr2act_05T = 0,
2559 .tr2mrw = 8, .tr2mrw_05T = 1,
2560 .tw2mrw = 6, .tw2mrw_05T = 1,
2561 .tmrr2mrw = 7, .tmrr2mrw_05T = 0,
2562 .tmrw = 3, .tmrw_05T = 0,
2563 .tmrd = 3, .tmrd_05T = 1,
2564 .tmrwckel = 4, .tmrwckel_05T = 1,
2565 .tpde = 1, .tpde_05T = 1,
2566 .tpdx = 1, .tpdx_05T = 0,
2567 .tmrri = 5, .tmrri_05T = 1,
2568 .trrd = 1, .trrd_05T = 0,
2569 .trrd_4266 = 0, .trrd_4266_05T = 1,
2570 .tfaw = 0, .tfaw_05T = 0,
2571 .tfaw_4266 = 0, .tfaw_4266_05T = 0,
2572 .trtw_odt_off = 1, .trtw_odt_off_05T = 0,
2573 .trtw_odt_on = 4, .trtw_odt_on_05T = 0,
2574 .txrefcnt = 58,
2575 .tzqcs = 16,
2576 .xrtw2w_new_mode = 4,
2577 .xrtw2w_old_mode = 6,
2578 .xrtw2r_odt_on = 3,
2579 .xrtw2r_odt_off = 3,
2580 .xrtr2w_odt_on = 3,
2581 .xrtr2w_odt_off = 3,
2582 .xrtr2r_new_mode = 3,
2583 .xrtr2r_old_mode = 6,
2584 .tr2mrr = 4,
2585 .vrcgdis_prdcnt = 20,
2586 .hwset_mr2_op = 18,
2587 .hwset_mr13_op = 24,
2588 .hwset_vrcg_op = 16,
2589 .trcd_derate = 4, .trcd_derate_05T = 0,
2590 .trc_derate = 4, .trc_derate_05T = 0,
2591 .tras_derate = 0, .tras_derate_05T = 1,
2592 .trpab_derate = 3, .trpab_derate_05T = 1,
2593 .trp_derate = 2, .trp_derate_05T = 1,
2594 .trrd_derate = 1, .trrd_derate_05T = 1,
2595 .trtpd = 7, .trtpd_05T = 1,
2596 .twtpd = 9, .twtpd_05T = 1,
2597 .tmrr2w_odt_off = 3,
2598 .tmrr2w_odt_on = 5,
2599 .ckeprd = 1,
2600 .ckelckcnt = 2,
2601 .zqlat2 = 6,
2602
2603 //DQSINCTL, DATLAT aren't in ACTiming excel file
2604 .dqsinctl = 2, .datlat = 10
2605 },
2606 //LPDDR4 4X_1600_BT_Div 8_DBI0.csv Read 0
2607 {
2608 .dramType = TYPE_LPDDR4, .freq = 800, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
2609 .readLat = 16, .writeLat = 8, .DivMode = DIV8_MODE,
2610
2611 .tras = 0, .tras_05T = 0,
2612 .trp = 2, .trp_05T = 1,
2613 .trpab = 3, .trpab_05T = 0,
2614 .trc = 3, .trc_05T = 0,
2615 .trfc = 44, .trfc_05T = 0,
2616 .trfcpb = 16, .trfcpb_05T = 0,
2617 .txp = 0, .txp_05T = 0,
2618 .trtp = 0, .trtp_05T = 1,
2619 .trcd = 4, .trcd_05T = 0,
2620 .twr = 7, .twr_05T = 0,
2621 .twtr = 4, .twtr_05T = 0,
2622 .tpbr2pbr = 11, .tpbr2pbr_05T = 0,
2623 .tpbr2act = 0, .tpbr2act_05T = 0,
2624 .tr2mrw = 9, .tr2mrw_05T = 0,
2625 .tw2mrw = 6, .tw2mrw_05T = 1,
2626 .tmrr2mrw = 7, .tmrr2mrw_05T = 1,
2627 .tmrw = 3, .tmrw_05T = 0,
2628 .tmrd = 3, .tmrd_05T = 1,
2629 .tmrwckel = 4, .tmrwckel_05T = 1,
2630 .tpde = 1, .tpde_05T = 1,
2631 .tpdx = 1, .tpdx_05T = 0,
2632 .tmrri = 5, .tmrri_05T = 1,
2633 .trrd = 1, .trrd_05T = 0,
2634 .trrd_4266 = 0, .trrd_4266_05T = 1,
2635 .tfaw = 0, .tfaw_05T = 0,
2636 .tfaw_4266 = 0, .tfaw_4266_05T = 0,
2637 .trtw_odt_off = 2, .trtw_odt_off_05T = 0,
2638 .trtw_odt_on = 4, .trtw_odt_on_05T = 0,
2639 .txrefcnt = 58,
2640 .tzqcs = 16,
2641 .xrtw2w_new_mode = 4,
2642 .xrtw2w_old_mode = 6,
2643 .xrtw2r_odt_on = 3,
2644 .xrtw2r_odt_off = 2,
2645 .xrtr2w_odt_on = 3,
2646 .xrtr2w_odt_off = 3,
2647 .xrtr2r_new_mode = 3,
2648 .xrtr2r_old_mode = 6,
2649 .tr2mrr = 4,
2650 .vrcgdis_prdcnt = 20,
2651 .hwset_mr2_op = 18,
2652 .hwset_mr13_op = 24,
2653 .hwset_vrcg_op = 16,
2654 .trcd_derate = 4, .trcd_derate_05T = 0,
2655 .trc_derate = 4, .trc_derate_05T = 0,
2656 .tras_derate = 0, .tras_derate_05T = 1,
2657 .trpab_derate = 3, .trpab_derate_05T = 1,
2658 .trp_derate = 2, .trp_derate_05T = 1,
2659 .trrd_derate = 1, .trrd_derate_05T = 1,
2660 .trtpd = 8, .trtpd_05T = 0,
2661 .twtpd = 9, .twtpd_05T = 1,
2662 .tmrr2w_odt_off = 4,
2663 .tmrr2w_odt_on = 6,
2664 .ckeprd = 1,
2665 .ckelckcnt = 2,
2666 .zqlat2 = 6,
2667
2668 //DQSINCTL, DATLAT aren't in ACTiming excel file
2669 .dqsinctl = 2, .datlat = 10
2670 },
2671 #endif
2672 #if SUPPORT_LP4_DDR1333_ACTIM
2673 //LP4_DDR1333 ACTiming---------------------------------
2674 //LPDDR4 4X_1333_Div 4_DBI0.csv Read 0
2675 {
2676 .dramType = TYPE_LPDDR4, .freq = 666, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
2677 .readLat = 14, .writeLat = 8, .DivMode = DIV4_MODE,
2678
2679 .tras = 6, .tras_05T = 0,
2680 .trp = 4, .trp_05T = 0,
2681 .trpab = 5, .trpab_05T = 0,
2682 .trc = 11, .trc_05T = 0,
2683 .trfc = 82, .trfc_05T = 0,
2684 .trfcpb = 35, .trfcpb_05T = 0,
2685 .txp = 0, .txp_05T = 0,
2686 .trtp = 3, .trtp_05T = 0,
2687 .trcd = 6, .trcd_05T = 0,
2688 .twr = 14, .twr_05T = 0,
2689 .twtr = 10, .twtr_05T = 0,
2690 .tpbr2pbr = 23, .tpbr2pbr_05T = 0,
2691 .tpbr2act = 0, .tpbr2act_05T = 0,
2692 .tr2mrw = 17, .tr2mrw_05T = 0,
2693 .tw2mrw = 13, .tw2mrw_05T = 0,
2694 .tmrr2mrw = 14, .tmrr2mrw_05T = 0,
2695 .tmrw = 6, .tmrw_05T = 0,
2696 .tmrd = 6, .tmrd_05T = 0,
2697 .tmrwckel = 8, .tmrwckel_05T = 0,
2698 .tpde = 3, .tpde_05T = 0,
2699 .tpdx = 3, .tpdx_05T = 0,
2700 .tmrri = 9, .tmrri_05T = 0,
2701 .trrd = 3, .trrd_05T = 0,
2702 .trrd_4266 = 2, .trrd_4266_05T = 0,
2703 .tfaw = 6, .tfaw_05T = 0,
2704 .tfaw_4266 = 2, .tfaw_4266_05T = 0,
2705 .trtw_odt_off = 7, .trtw_odt_off_05T = 0,
2706 .trtw_odt_on = 11, .trtw_odt_on_05T = 0,
2707 .txrefcnt = 96,
2708 .tzqcs = 28,
2709 .xrtw2w_new_mode = 9,
2710 .xrtw2w_old_mode = 10,
2711 .xrtw2r_odt_on = 7,
2712 .xrtw2r_odt_off = 6,
2713 .xrtr2w_odt_on = 10,
2714 .xrtr2w_odt_off = 10,
2715 .xrtr2r_new_mode = 7,
2716 .xrtr2r_old_mode = 9,
2717 .tr2mrr = 8,
2718 .vrcgdis_prdcnt = 34,
2719 .hwset_mr2_op = 18,
2720 .hwset_mr13_op = 24,
2721 .hwset_vrcg_op = 16,
2722 .trcd_derate = 7, .trcd_derate_05T = 0,
2723 .trc_derate = 13, .trc_derate_05T = 0,
2724 .tras_derate = 7, .tras_derate_05T = 0,
2725 .trpab_derate = 6, .trpab_derate_05T = 0,
2726 .trp_derate = 5, .trp_derate_05T = 0,
2727 .trrd_derate = 3, .trrd_derate_05T = 0,
2728 .trtpd = 15, .trtpd_05T = 0,
2729 .twtpd = 17, .twtpd_05T = 0,
2730 .tmrr2w_odt_off = 10,
2731 .tmrr2w_odt_on = 12,
2732 .ckeprd = 2,
2733 .ckelckcnt = 3,
2734 .zqlat2 = 10,
2735
2736 //DQSINCTL, DATLAT aren't in ACTiming excel file
2737 .dqsinctl = TBD, .datlat = TBD
2738 },
2739 //LPDDR4 4X_1333_BT_Div 4_DBI0.csv Read 0
2740 {
2741 .dramType = TYPE_LPDDR4, .freq = 666, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
2742 .readLat = 16, .writeLat = 8, .DivMode = DIV4_MODE,
2743
2744 .tras = 6, .tras_05T = 0,
2745 .trp = 4, .trp_05T = 0,
2746 .trpab = 5, .trpab_05T = 0,
2747 .trc = 11, .trc_05T = 0,
2748 .trfc = 82, .trfc_05T = 0,
2749 .trfcpb = 35, .trfcpb_05T = 0,
2750 .txp = 0, .txp_05T = 0,
2751 .trtp = 3, .trtp_05T = 0,
2752 .trcd = 6, .trcd_05T = 0,
2753 .twr = 15, .twr_05T = 0,
2754 .twtr = 10, .twtr_05T = 0,
2755 .tpbr2pbr = 23, .tpbr2pbr_05T = 0,
2756 .tpbr2act = 0, .tpbr2act_05T = 0,
2757 .tr2mrw = 18, .tr2mrw_05T = 0,
2758 .tw2mrw = 13, .tw2mrw_05T = 0,
2759 .tmrr2mrw = 15, .tmrr2mrw_05T = 0,
2760 .tmrw = 6, .tmrw_05T = 0,
2761 .tmrd = 6, .tmrd_05T = 0,
2762 .tmrwckel = 8, .tmrwckel_05T = 0,
2763 .tpde = 3, .tpde_05T = 0,
2764 .tpdx = 3, .tpdx_05T = 0,
2765 .tmrri = 9, .tmrri_05T = 0,
2766 .trrd = 3, .trrd_05T = 0,
2767 .trrd_4266 = 2, .trrd_4266_05T = 0,
2768 .tfaw = 6, .tfaw_05T = 0,
2769 .tfaw_4266 = 2, .tfaw_4266_05T = 0,
2770 .trtw_odt_off = 8, .trtw_odt_off_05T = 0,
2771 .trtw_odt_on = 12, .trtw_odt_on_05T = 0,
2772 .txrefcnt = 96,
2773 .tzqcs = 28,
2774 .xrtw2w_new_mode = 9,
2775 .xrtw2w_old_mode = 10,
2776 .xrtw2r_odt_on = 6,
2777 .xrtw2r_odt_off = 5,
2778 .xrtr2w_odt_on = 11,
2779 .xrtr2w_odt_off = 11,
2780 .xrtr2r_new_mode = 7,
2781 .xrtr2r_old_mode = 10,
2782 .tr2mrr = 8,
2783 .vrcgdis_prdcnt = 34,
2784 .hwset_mr2_op = 18,
2785 .hwset_mr13_op = 24,
2786 .hwset_vrcg_op = 16,
2787 .trcd_derate = 7, .trcd_derate_05T = 0,
2788 .trc_derate = 13, .trc_derate_05T = 0,
2789 .tras_derate = 7, .tras_derate_05T = 0,
2790 .trpab_derate = 6, .trpab_derate_05T = 0,
2791 .trp_derate = 5, .trp_derate_05T = 0,
2792 .trrd_derate = 3, .trrd_derate_05T = 0,
2793 .trtpd = 16, .trtpd_05T = 0,
2794 .twtpd = 18, .twtpd_05T = 0,
2795 .tmrr2w_odt_off = 11,
2796 .tmrr2w_odt_on = 13,
2797 .ckeprd = 2,
2798 .ckelckcnt = 3,
2799 .zqlat2 = 10,
2800
2801 //DQSINCTL, DATLAT aren't in ACTiming excel file
2802 .dqsinctl = TBD, .datlat = TBD
2803 },
2804 //LPDDR4 4X_1333_Div 8_DBI0.csv Read 0
2805 {
2806 .dramType = TYPE_LPDDR4, .freq = 666, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
2807 .readLat = 14, .writeLat = 8, .DivMode = DIV8_MODE,
2808
2809 .tras = 0, .tras_05T = 0,
2810 .trp = 1, .trp_05T = 1,
2811 .trpab = 2, .trpab_05T = 0,
2812 .trc = 1, .trc_05T = 0,
2813 .trfc = 35, .trfc_05T = 0,
2814 .trfcpb = 11, .trfcpb_05T = 1,
2815 .txp = 0, .txp_05T = 0,
2816 .trtp = 0, .trtp_05T = 1,
2817 .trcd = 3, .trcd_05T = 0,
2818 .twr = 6, .twr_05T = 0,
2819 .twtr = 4, .twtr_05T = 1,
2820 .tpbr2pbr = 8, .tpbr2pbr_05T = 0,
2821 .tpbr2act = 0, .tpbr2act_05T = 0,
2822 .tr2mrw = 8, .tr2mrw_05T = 1,
2823 .tw2mrw = 6, .tw2mrw_05T = 1,
2824 .tmrr2mrw = 7, .tmrr2mrw_05T = 0,
2825 .tmrw = 3, .tmrw_05T = 0,
2826 .tmrd = 3, .tmrd_05T = 0,
2827 .tmrwckel = 4, .tmrwckel_05T = 0,
2828 .tpde = 1, .tpde_05T = 1,
2829 .tpdx = 1, .tpdx_05T = 0,
2830 .tmrri = 4, .tmrri_05T = 1,
2831 .trrd = 1, .trrd_05T = 0,
2832 .trrd_4266 = 0, .trrd_4266_05T = 1,
2833 .tfaw = 0, .tfaw_05T = 0,
2834 .tfaw_4266 = 0, .tfaw_4266_05T = 0,
2835 .trtw_odt_off = 1, .trtw_odt_off_05T = 0,
2836 .trtw_odt_on = 4, .trtw_odt_on_05T = 0,
2837 .txrefcnt = 48,
2838 .tzqcs = 13,
2839 .xrtw2w_new_mode = 4,
2840 .xrtw2w_old_mode = 6,
2841 .xrtw2r_odt_on = 3,
2842 .xrtw2r_odt_off = 3,
2843 .xrtr2w_odt_on = 3,
2844 .xrtr2w_odt_off = 3,
2845 .xrtr2r_new_mode = 3,
2846 .xrtr2r_old_mode = 6,
2847 .tr2mrr = 4,
2848 .vrcgdis_prdcnt = 17,
2849 .hwset_mr2_op = 18,
2850 .hwset_mr13_op = 24,
2851 .hwset_vrcg_op = 16,
2852 .trcd_derate = 3, .trcd_derate_05T = 1,
2853 .trc_derate = 2, .trc_derate_05T = 0,
2854 .tras_derate = 0, .tras_derate_05T = 0,
2855 .trpab_derate = 2, .trpab_derate_05T = 1,
2856 .trp_derate = 2, .trp_derate_05T = 0,
2857 .trrd_derate = 1, .trrd_derate_05T = 0,
2858 .trtpd = 7, .trtpd_05T = 1,
2859 .twtpd = 8, .twtpd_05T = 1,
2860 .tmrr2w_odt_off = 3,
2861 .tmrr2w_odt_on = 5,
2862 .ckeprd = 1,
2863 .ckelckcnt = 2,
2864 .zqlat2 = 5,
2865
2866 //DQSINCTL, DATLAT aren't in ACTiming excel file
2867 .dqsinctl = TBD, .datlat = TBD
2868 },
2869 //LPDDR4 4X_1333_BT_Div 8_DBI0.csv Read 0
2870 {
2871 .dramType = TYPE_LPDDR4, .freq = 666, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
2872 .readLat = 16, .writeLat = 8, .DivMode = DIV8_MODE,
2873
2874 .tras = 0, .tras_05T = 0,
2875 .trp = 1, .trp_05T = 1,
2876 .trpab = 2, .trpab_05T = 0,
2877 .trc = 1, .trc_05T = 0,
2878 .trfc = 35, .trfc_05T = 0,
2879 .trfcpb = 11, .trfcpb_05T = 1,
2880 .txp = 0, .txp_05T = 0,
2881 .trtp = 0, .trtp_05T = 1,
2882 .trcd = 3, .trcd_05T = 0,
2883 .twr = 6, .twr_05T = 1,
2884 .twtr = 4, .twtr_05T = 1,
2885 .tpbr2pbr = 8, .tpbr2pbr_05T = 0,
2886 .tpbr2act = 0, .tpbr2act_05T = 0,
2887 .tr2mrw = 9, .tr2mrw_05T = 0,
2888 .tw2mrw = 6, .tw2mrw_05T = 1,
2889 .tmrr2mrw = 7, .tmrr2mrw_05T = 1,
2890 .tmrw = 3, .tmrw_05T = 0,
2891 .tmrd = 3, .tmrd_05T = 0,
2892 .tmrwckel = 4, .tmrwckel_05T = 0,
2893 .tpde = 1, .tpde_05T = 1,
2894 .tpdx = 1, .tpdx_05T = 0,
2895 .tmrri = 4, .tmrri_05T = 1,
2896 .trrd = 1, .trrd_05T = 0,
2897 .trrd_4266 = 0, .trrd_4266_05T = 1,
2898 .tfaw = 0, .tfaw_05T = 0,
2899 .tfaw_4266 = 0, .tfaw_4266_05T = 0,
2900 .trtw_odt_off = 2, .trtw_odt_off_05T = 0,
2901 .trtw_odt_on = 5, .trtw_odt_on_05T = 0,
2902 .txrefcnt = 48,
2903 .tzqcs = 13,
2904 .xrtw2w_new_mode = 4,
2905 .xrtw2w_old_mode = 6,
2906 .xrtw2r_odt_on = 3,
2907 .xrtw2r_odt_off = 2,
2908 .xrtr2w_odt_on = 3,
2909 .xrtr2w_odt_off = 3,
2910 .xrtr2r_new_mode = 3,
2911 .xrtr2r_old_mode = 6,
2912 .tr2mrr = 4,
2913 .vrcgdis_prdcnt = 17,
2914 .hwset_mr2_op = 18,
2915 .hwset_mr13_op = 24,
2916 .hwset_vrcg_op = 16,
2917 .trcd_derate = 3, .trcd_derate_05T = 1,
2918 .trc_derate = 2, .trc_derate_05T = 0,
2919 .tras_derate = 0, .tras_derate_05T = 0,
2920 .trpab_derate = 2, .trpab_derate_05T = 1,
2921 .trp_derate = 2, .trp_derate_05T = 0,
2922 .trrd_derate = 1, .trrd_derate_05T = 0,
2923 .trtpd = 8, .trtpd_05T = 0,
2924 .twtpd = 9, .twtpd_05T = 0,
2925 .tmrr2w_odt_off = 4,
2926 .tmrr2w_odt_on = 6,
2927 .ckeprd = 1,
2928 .ckelckcnt = 2,
2929 .zqlat2 = 5,
2930
2931 //DQSINCTL, DATLAT aren't in ACTiming excel file
2932 .dqsinctl = TBD, .datlat = TBD
2933 },
2934 #endif
2935 #if SUPPORT_LP4_DDR1200_ACTIM
2936 //LP4_DDR1200 ACTiming---------------------------------
2937 //LPDDR4 4X_1200_Div 4_DBI0.csv Read 0
2938 {
2939 .dramType = TYPE_LPDDR4, .freq = 600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
2940 .readLat = 14, .writeLat = 8, .DivMode = DIV4_MODE,
2941
2942 .tras = 5, .tras_05T = 0,
2943 .trp = 4, .trp_05T = 0,
2944 .trpab = 5, .trpab_05T = 0,
2945 .trc = 10, .trc_05T = 0,
2946 .trfc = 73, .trfc_05T = 0,
2947 .trfcpb = 31, .trfcpb_05T = 0,
2948 .txp = 0, .txp_05T = 0,
2949 .trtp = 3, .trtp_05T = 0,
2950 .trcd = 6, .trcd_05T = 0,
2951 .twr = 13, .twr_05T = 0,
2952 .twtr = 10, .twtr_05T = 0,
2953 .tpbr2pbr = 21, .tpbr2pbr_05T = 0,
2954 .tpbr2act = 0, .tpbr2act_05T = 0,
2955 .tr2mrw = 17, .tr2mrw_05T = 0,
2956 .tw2mrw = 13, .tw2mrw_05T = 0,
2957 .tmrr2mrw = 14, .tmrr2mrw_05T = 0,
2958 .tmrw = 6, .tmrw_05T = 0,
2959 .tmrd = 6, .tmrd_05T = 0,
2960 .tmrwckel = 8, .tmrwckel_05T = 0,
2961 .tpde = 3, .tpde_05T = 0,
2962 .tpdx = 3, .tpdx_05T = 0,
2963 .tmrri = 8, .tmrri_05T = 0,
2964 .trrd = 3, .trrd_05T = 0,
2965 .trrd_4266 = 2, .trrd_4266_05T = 0,
2966 .tfaw = 5, .tfaw_05T = 0,
2967 .tfaw_4266 = 2, .tfaw_4266_05T = 0,
2968 .trtw_odt_off = 7, .trtw_odt_off_05T = 0,
2969 .trtw_odt_on = 11, .trtw_odt_on_05T = 0,
2970 .txrefcnt = 87,
2971 .tzqcs = 26,
2972 .xrtw2w_new_mode = 9,
2973 .xrtw2w_old_mode = 10,
2974 .xrtw2r_odt_on = 7,
2975 .xrtw2r_odt_off = 6,
2976 .xrtr2w_odt_on = 10,
2977 .xrtr2w_odt_off = 10,
2978 .xrtr2r_new_mode = 7,
2979 .xrtr2r_old_mode = 9,
2980 .tr2mrr = 8,
2981 .vrcgdis_prdcnt = 31,
2982 .hwset_mr2_op = 18,
2983 .hwset_mr13_op = 24,
2984 .hwset_vrcg_op = 16,
2985 .trcd_derate = 6, .trcd_derate_05T = 0,
2986 .trc_derate = 11, .trc_derate_05T = 0,
2987 .tras_derate = 6, .tras_derate_05T = 0,
2988 .trpab_derate = 5, .trpab_derate_05T = 0,
2989 .trp_derate = 4, .trp_derate_05T = 0,
2990 .trrd_derate = 3, .trrd_derate_05T = 0,
2991 .trtpd = 15, .trtpd_05T = 0,
2992 .twtpd = 17, .twtpd_05T = 0,
2993 .tmrr2w_odt_off = 10,
2994 .tmrr2w_odt_on = 12,
2995 .ckeprd = 2,
2996 .ckelckcnt = 3,
2997 .zqlat2 = 10,
2998
2999 //DQSINCTL, DATLAT aren't in ACTiming excel file
3000 .dqsinctl = 2, .datlat = 9
3001 },
3002 //LPDDR4 4X_1200_BT_Div 4_DBI0.csv Read 0
3003 {
3004 .dramType = TYPE_LPDDR4, .freq = 600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
3005 .readLat = 16, .writeLat = 8, .DivMode = DIV4_MODE,
3006
3007 .tras = 5, .tras_05T = 0,
3008 .trp = 4, .trp_05T = 0,
3009 .trpab = 5, .trpab_05T = 0,
3010 .trc = 10, .trc_05T = 0,
3011 .trfc = 73, .trfc_05T = 0,
3012 .trfcpb = 31, .trfcpb_05T = 0,
3013 .txp = 0, .txp_05T = 0,
3014 .trtp = 3, .trtp_05T = 0,
3015 .trcd = 6, .trcd_05T = 0,
3016 .twr = 14, .twr_05T = 0,
3017 .twtr = 10, .twtr_05T = 0,
3018 .tpbr2pbr = 21, .tpbr2pbr_05T = 0,
3019 .tpbr2act = 0, .tpbr2act_05T = 0,
3020 .tr2mrw = 18, .tr2mrw_05T = 0,
3021 .tw2mrw = 13, .tw2mrw_05T = 0,
3022 .tmrr2mrw = 15, .tmrr2mrw_05T = 0,
3023 .tmrw = 6, .tmrw_05T = 0,
3024 .tmrd = 6, .tmrd_05T = 0,
3025 .tmrwckel = 8, .tmrwckel_05T = 0,
3026 .tpde = 3, .tpde_05T = 0,
3027 .tpdx = 3, .tpdx_05T = 0,
3028 .tmrri = 8, .tmrri_05T = 0,
3029 .trrd = 3, .trrd_05T = 0,
3030 .trrd_4266 = 2, .trrd_4266_05T = 0,
3031 .tfaw = 5, .tfaw_05T = 0,
3032 .tfaw_4266 = 2, .tfaw_4266_05T = 0,
3033 .trtw_odt_off = 8, .trtw_odt_off_05T = 0,
3034 .trtw_odt_on = 12, .trtw_odt_on_05T = 0,
3035 .txrefcnt = 87,
3036 .tzqcs = 26,
3037 .xrtw2w_new_mode = 9,
3038 .xrtw2w_old_mode = 10,
3039 .xrtw2r_odt_on = 6,
3040 .xrtw2r_odt_off = 5,
3041 .xrtr2w_odt_on = 11,
3042 .xrtr2w_odt_off = 11,
3043 .xrtr2r_new_mode = 7,
3044 .xrtr2r_old_mode = 10,
3045 .tr2mrr = 8,
3046 .vrcgdis_prdcnt = 31,
3047 .hwset_mr2_op = 18,
3048 .hwset_mr13_op = 24,
3049 .hwset_vrcg_op = 16,
3050 .trcd_derate = 6, .trcd_derate_05T = 0,
3051 .trc_derate = 11, .trc_derate_05T = 0,
3052 .tras_derate = 6, .tras_derate_05T = 0,
3053 .trpab_derate = 5, .trpab_derate_05T = 0,
3054 .trp_derate = 4, .trp_derate_05T = 0,
3055 .trrd_derate = 3, .trrd_derate_05T = 0,
3056 .trtpd = 16, .trtpd_05T = 0,
3057 .twtpd = 18, .twtpd_05T = 0,
3058 .tmrr2w_odt_off = 11,
3059 .tmrr2w_odt_on = 13,
3060 .ckeprd = 2,
3061 .ckelckcnt = 3,
3062 .zqlat2 = 10,
3063
3064 //DQSINCTL, DATLAT aren't in ACTiming excel file
3065 .dqsinctl = 2, .datlat = 9
3066 },
3067 //LPDDR4 4X_1200_Div 8_DBI0.csv Read 0
3068 {
3069 .dramType = TYPE_LPDDR4, .freq = 600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
3070 .readLat = 14, .writeLat = 8, .DivMode = DIV8_MODE,
3071
3072 .tras = 0, .tras_05T = 0,
3073 .trp = 1, .trp_05T = 1,
3074 .trpab = 2, .trpab_05T = 0,
3075 .trc = 0, .trc_05T = 1,
3076 .trfc = 30, .trfc_05T = 1,
3077 .trfcpb = 9, .trfcpb_05T = 1,
3078 .txp = 0, .txp_05T = 0,
3079 .trtp = 0, .trtp_05T = 1,
3080 .trcd = 3, .trcd_05T = 0,
3081 .twr = 6, .twr_05T = 1,
3082 .twtr = 4, .twtr_05T = 1,
3083 .tpbr2pbr = 7, .tpbr2pbr_05T = 0,
3084 .tpbr2act = 0, .tpbr2act_05T = 0,
3085 .tr2mrw = 8, .tr2mrw_05T = 1,
3086 .tw2mrw = 6, .tw2mrw_05T = 1,
3087 .tmrr2mrw = 7, .tmrr2mrw_05T = 0,
3088 .tmrw = 3, .tmrw_05T = 0,
3089 .tmrd = 3, .tmrd_05T = 0,
3090 .tmrwckel = 4, .tmrwckel_05T = 0,
3091 .tpde = 1, .tpde_05T = 1,
3092 .tpdx = 1, .tpdx_05T = 0,
3093 .tmrri = 4, .tmrri_05T = 0,
3094 .trrd = 1, .trrd_05T = 0,
3095 .trrd_4266 = 0, .trrd_4266_05T = 1,
3096 .tfaw = 0, .tfaw_05T = 0,
3097 .tfaw_4266 = 0, .tfaw_4266_05T = 0,
3098 .trtw_odt_off = 1, .trtw_odt_off_05T = 0,
3099 .trtw_odt_on = 4, .trtw_odt_on_05T = 0,
3100 .txrefcnt = 44,
3101 .tzqcs = 12,
3102 .xrtw2w_new_mode = 4,
3103 .xrtw2w_old_mode = 6,
3104 .xrtw2r_odt_on = 3,
3105 .xrtw2r_odt_off = 3,
3106 .xrtr2w_odt_on = 3,
3107 .xrtr2w_odt_off = 3,
3108 .xrtr2r_new_mode = 3,
3109 .xrtr2r_old_mode = 6,
3110 .tr2mrr = 4,
3111 .vrcgdis_prdcnt = 16,
3112 .hwset_mr2_op = 18,
3113 .hwset_mr13_op = 24,
3114 .hwset_vrcg_op = 16,
3115 .trcd_derate = 3, .trcd_derate_05T = 0,
3116 .trc_derate = 1, .trc_derate_05T = 0,
3117 .tras_derate = 0, .tras_derate_05T = 0,
3118 .trpab_derate = 2, .trpab_derate_05T = 0,
3119 .trp_derate = 1, .trp_derate_05T = 1,
3120 .trrd_derate = 1, .trrd_derate_05T = 0,
3121 .trtpd = 7, .trtpd_05T = 1,
3122 .twtpd = 8, .twtpd_05T = 1,
3123 .tmrr2w_odt_off = 3,
3124 .tmrr2w_odt_on = 5,
3125 .ckeprd = 1,
3126 .ckelckcnt = 2,
3127 .zqlat2 = 5,
3128
3129 //DQSINCTL, DATLAT aren't in ACTiming excel file
3130 .dqsinctl = 2, .datlat = 9
3131 },
3132 //LPDDR4 4X_1200_BT_Div 8_DBI0.csv Read 0
3133 {
3134 .dramType = TYPE_LPDDR4, .freq = 600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
3135 .readLat = 16, .writeLat = 8, .DivMode = DIV8_MODE,
3136
3137 .tras = 0, .tras_05T = 0,
3138 .trp = 1, .trp_05T = 1,
3139 .trpab = 2, .trpab_05T = 0,
3140 .trc = 0, .trc_05T = 1,
3141 .trfc = 30, .trfc_05T = 1,
3142 .trfcpb = 9, .trfcpb_05T = 1,
3143 .txp = 0, .txp_05T = 0,
3144 .trtp = 0, .trtp_05T = 1,
3145 .trcd = 3, .trcd_05T = 0,
3146 .twr = 6, .twr_05T = 0,
3147 .twtr = 4, .twtr_05T = 1,
3148 .tpbr2pbr = 7, .tpbr2pbr_05T = 0,
3149 .tpbr2act = 0, .tpbr2act_05T = 0,
3150 .tr2mrw = 9, .tr2mrw_05T = 0,
3151 .tw2mrw = 6, .tw2mrw_05T = 1,
3152 .tmrr2mrw = 7, .tmrr2mrw_05T = 1,
3153 .tmrw = 3, .tmrw_05T = 0,
3154 .tmrd = 3, .tmrd_05T = 0,
3155 .tmrwckel = 4, .tmrwckel_05T = 0,
3156 .tpde = 1, .tpde_05T = 1,
3157 .tpdx = 1, .tpdx_05T = 0,
3158 .tmrri = 4, .tmrri_05T = 0,
3159 .trrd = 1, .trrd_05T = 0,
3160 .trrd_4266 = 0, .trrd_4266_05T = 1,
3161 .tfaw = 0, .tfaw_05T = 0,
3162 .tfaw_4266 = 0, .tfaw_4266_05T = 0,
3163 .trtw_odt_off = 2, .trtw_odt_off_05T = 0,
3164 .trtw_odt_on = 5, .trtw_odt_on_05T = 0,
3165 .txrefcnt = 44,
3166 .tzqcs = 12,
3167 .xrtw2w_new_mode = 4,
3168 .xrtw2w_old_mode = 6,
3169 .xrtw2r_odt_on = 3,
3170 .xrtw2r_odt_off = 2,
3171 .xrtr2w_odt_on = 3,
3172 .xrtr2w_odt_off = 3,
3173 .xrtr2r_new_mode = 3,
3174 .xrtr2r_old_mode = 6,
3175 .tr2mrr = 4,
3176 .vrcgdis_prdcnt = 16,
3177 .hwset_mr2_op = 18,
3178 .hwset_mr13_op = 24,
3179 .hwset_vrcg_op = 16,
3180 .trcd_derate = 3, .trcd_derate_05T = 0,
3181 .trc_derate = 1, .trc_derate_05T = 0,
3182 .tras_derate = 0, .tras_derate_05T = 0,
3183 .trpab_derate = 2, .trpab_derate_05T = 0,
3184 .trp_derate = 1, .trp_derate_05T = 1,
3185 .trrd_derate = 1, .trrd_derate_05T = 0,
3186 .trtpd = 8, .trtpd_05T = 0,
3187 .twtpd = 9, .twtpd_05T = 0,
3188 .tmrr2w_odt_off = 4,
3189 .tmrr2w_odt_on = 6,
3190 .ckeprd = 1,
3191 .ckelckcnt = 2,
3192 .zqlat2 = 5,
3193
3194 //DQSINCTL, DATLAT aren't in ACTiming excel file
3195 .dqsinctl = 2, .datlat = 9
3196 },
3197 #endif
3198 #if SUPPORT_LP4_DDR800_ACTIM
3199 //LP4_DDR800 ACTiming---------------------------------
3200 //LPDDR4 4X_800_Div 4_DBI0.csv Read 0
3201 {
3202 .dramType = TYPE_LPDDR4, .freq = 400, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
3203 .readLat = 14, .writeLat = 8, .DivMode = DIV4_MODE,
3204
3205 .tras = 1, .tras_05T = 0,
3206 .trp = 2, .trp_05T = 0,
3207 .trpab = 3, .trpab_05T = 0,
3208 .trc = 3, .trc_05T = 0,
3209 .trfc = 44, .trfc_05T = 0,
3210 .trfcpb = 16, .trfcpb_05T = 0,
3211 .txp = 0, .txp_05T = 0,
3212 .trtp = 3, .trtp_05T = 0,
3213 .trcd = 4, .trcd_05T = 0,
3214 .twr = 12, .twr_05T = 0,
3215 .twtr = 10, .twtr_05T = 0,
3216 .tpbr2pbr = 11, .tpbr2pbr_05T = 0,
3217 .tpbr2act = 0, .tpbr2act_05T = 0,
3218 .tr2mrw = 16, .tr2mrw_05T = 0,
3219 .tw2mrw = 13, .tw2mrw_05T = 0,
3220 .tmrr2mrw = 14, .tmrr2mrw_05T = 0,
3221 .tmrw = 6, .tmrw_05T = 0,
3222 .tmrd = 6, .tmrd_05T = 0,
3223 .tmrwckel = 8, .tmrwckel_05T = 0,
3224 .tpde = 3, .tpde_05T = 0,
3225 .tpdx = 3, .tpdx_05T = 0,
3226 .tmrri = 7, .tmrri_05T = 0,
3227 .trrd = 1, .trrd_05T = 0,
3228 .trrd_4266 = 1, .trrd_4266_05T = 0,
3229 .tfaw = 0, .tfaw_05T = 0,
3230 .tfaw_4266 = 0, .tfaw_4266_05T = 0,
3231 .trtw_odt_off = 6, .trtw_odt_off_05T = 0,
3232 .trtw_odt_on = 11, .trtw_odt_on_05T = 0,
3233 .txrefcnt = 58,
3234 .tzqcs = 16,
3235 .xrtw2w_new_mode = 9,
3236 .xrtw2w_old_mode = 10,
3237 .xrtw2r_odt_on = 7,
3238 .xrtw2r_odt_off = 5,
3239 .xrtr2w_odt_on = 9,
3240 .xrtr2w_odt_off = 9,
3241 .xrtr2r_new_mode = 6,
3242 .xrtr2r_old_mode = 8,
3243 .tr2mrr = 8,
3244 .vrcgdis_prdcnt = 20,
3245 .hwset_mr2_op = 18,
3246 .hwset_mr13_op = 24,
3247 .hwset_vrcg_op = 16,
3248 .trcd_derate = 4, .trcd_derate_05T = 0,
3249 .trc_derate = 4, .trc_derate_05T = 0,
3250 .tras_derate = 1, .tras_derate_05T = 0,
3251 .trpab_derate = 3, .trpab_derate_05T = 0,
3252 .trp_derate = 2, .trp_derate_05T = 0,
3253 .trrd_derate = 2, .trrd_derate_05T = 0,
3254 .trtpd = 15, .trtpd_05T = 0,
3255 .twtpd = 15, .twtpd_05T = 0,
3256 .tmrr2w_odt_off = 10,
3257 .tmrr2w_odt_on = 12,
3258 .ckeprd = 2,
3259 .ckelckcnt = 3,
3260 .zqlat2 = 6,
3261
3262 //DQSINCTL, DATLAT aren't in ACTiming excel file
3263 .dqsinctl = 5, .datlat = 15
3264 },
3265 //LPDDR4 4X_800_BT_Div 4_DBI0.csv Read 0
3266 {
3267 .dramType = TYPE_LPDDR4, .freq = 400, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
3268 .readLat = 16, .writeLat = 8, .DivMode = DIV4_MODE,
3269
3270 .tras = 1, .tras_05T = 0,
3271 .trp = 2, .trp_05T = 0,
3272 .trpab = 3, .trpab_05T = 0,
3273 .trc = 3, .trc_05T = 0,
3274 .trfc = 44, .trfc_05T = 0,
3275 .trfcpb = 16, .trfcpb_05T = 0,
3276 .txp = 0, .txp_05T = 0,
3277 .trtp = 3, .trtp_05T = 0,
3278 .trcd = 4, .trcd_05T = 0,
3279 .twr = 12, .twr_05T = 0,
3280 .twtr = 10, .twtr_05T = 0,
3281 .tpbr2pbr = 11, .tpbr2pbr_05T = 0,
3282 .tpbr2act = 0, .tpbr2act_05T = 0,
3283 .tr2mrw = 17, .tr2mrw_05T = 0,
3284 .tw2mrw = 13, .tw2mrw_05T = 0,
3285 .tmrr2mrw = 15, .tmrr2mrw_05T = 0,
3286 .tmrw = 6, .tmrw_05T = 0,
3287 .tmrd = 6, .tmrd_05T = 0,
3288 .tmrwckel = 8, .tmrwckel_05T = 0,
3289 .tpde = 3, .tpde_05T = 0,
3290 .tpdx = 3, .tpdx_05T = 0,
3291 .tmrri = 7, .tmrri_05T = 0,
3292 .trrd = 1, .trrd_05T = 0,
3293 .trrd_4266 = 1, .trrd_4266_05T = 0,
3294 .tfaw = 0, .tfaw_05T = 0,
3295 .tfaw_4266 = 0, .tfaw_4266_05T = 0,
3296 .trtw_odt_off = 7, .trtw_odt_off_05T = 0,
3297 .trtw_odt_on = 12, .trtw_odt_on_05T = 0,
3298 .txrefcnt = 58,
3299 .tzqcs = 16,
3300 .xrtw2w_new_mode = 9,
3301 .xrtw2w_old_mode = 10,
3302 .xrtw2r_odt_on = 6,
3303 .xrtw2r_odt_off = 4,
3304 .xrtr2w_odt_on = 10,
3305 .xrtr2w_odt_off = 10,
3306 .xrtr2r_new_mode = 6,
3307 .xrtr2r_old_mode = 9,
3308 .tr2mrr = 8,
3309 .vrcgdis_prdcnt = 20,
3310 .hwset_mr2_op = 18,
3311 .hwset_mr13_op = 24,
3312 .hwset_vrcg_op = 16,
3313 .trcd_derate = 4, .trcd_derate_05T = 0,
3314 .trc_derate = 4, .trc_derate_05T = 0,
3315 .tras_derate = 1, .tras_derate_05T = 0,
3316 .trpab_derate = 3, .trpab_derate_05T = 0,
3317 .trp_derate = 2, .trp_derate_05T = 0,
3318 .trrd_derate = 2, .trrd_derate_05T = 0,
3319 .trtpd = 16, .trtpd_05T = 0,
3320 .twtpd = 15, .twtpd_05T = 0,
3321 .tmrr2w_odt_off = 11,
3322 .tmrr2w_odt_on = 13,
3323 .ckeprd = 2,
3324 .ckelckcnt = 3,
3325 .zqlat2 = 6,
3326
3327 //DQSINCTL, DATLAT aren't in ACTiming excel file
3328 .dqsinctl = 5, .datlat = 15
3329 },
3330 //LPDDR4 4X_800_Div 8_DBI0.csv Read 0
3331 {
3332 .dramType = TYPE_LPDDR4, .freq = 400, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
3333 .readLat = 14, .writeLat = 8, .DivMode = DIV8_MODE,
3334
3335 .tras = 0, .tras_05T = 0,
3336 .trp = 0, .trp_05T = 1,
3337 .trpab = 1, .trpab_05T = 0,
3338 .trc = 0, .trc_05T = 0,
3339 .trfc = 16, .trfc_05T = 0,
3340 .trfcpb = 2, .trfcpb_05T = 0,
3341 .txp = 0, .txp_05T = 0,
3342 .trtp = 0, .trtp_05T = 1,
3343 .trcd = 2, .trcd_05T = 0,
3344 .twr = 5, .twr_05T = 0,
3345 .twtr = 4, .twtr_05T = 1,
3346 .tpbr2pbr = 2, .tpbr2pbr_05T = 0,
3347 .tpbr2act = 0, .tpbr2act_05T = 0,
3348 .tr2mrw = 8, .tr2mrw_05T = 0,
3349 .tw2mrw = 6, .tw2mrw_05T = 1,
3350 .tmrr2mrw = 7, .tmrr2mrw_05T = 0,
3351 .tmrw = 3, .tmrw_05T = 0,
3352 .tmrd = 3, .tmrd_05T = 0,
3353 .tmrwckel = 4, .tmrwckel_05T = 0,
3354 .tpde = 1, .tpde_05T = 1,
3355 .tpdx = 1, .tpdx_05T = 0,
3356 .tmrri = 3, .tmrri_05T = 1,
3357 .trrd = 0, .trrd_05T = 0,
3358 .trrd_4266 = 0, .trrd_4266_05T = 0,
3359 .tfaw = 0, .tfaw_05T = 0,
3360 .tfaw_4266 = 0, .tfaw_4266_05T = 0,
3361 .trtw_odt_off = 1, .trtw_odt_off_05T = 0,
3362 .trtw_odt_on = 4, .trtw_odt_on_05T = 0,
3363 .txrefcnt = 29,
3364 .tzqcs = 7,
3365 .xrtw2w_new_mode = 4,
3366 .xrtw2w_old_mode = 6,
3367 .xrtw2r_odt_on = 3,
3368 .xrtw2r_odt_off = 2,
3369 .xrtr2w_odt_on = 2,
3370 .xrtr2w_odt_off = 2,
3371 .xrtr2r_new_mode = 3,
3372 .xrtr2r_old_mode = 6,
3373 .tr2mrr = 4,
3374 .vrcgdis_prdcnt = 10,
3375 .hwset_mr2_op = 18,
3376 .hwset_mr13_op = 24,
3377 .hwset_vrcg_op = 16,
3378 .trcd_derate = 2, .trcd_derate_05T = 0,
3379 .trc_derate = 0, .trc_derate_05T = 0,
3380 .tras_derate = 0, .tras_derate_05T = 0,
3381 .trpab_derate = 1, .trpab_derate_05T = 0,
3382 .trp_derate = 0, .trp_derate_05T = 1,
3383 .trrd_derate = 0, .trrd_derate_05T = 1,
3384 .trtpd = 7, .trtpd_05T = 1,
3385 .twtpd = 7, .twtpd_05T = 1,
3386 .tmrr2w_odt_off = 3,
3387 .tmrr2w_odt_on = 5,
3388 .ckeprd = 1,
3389 .ckelckcnt = 2,
3390 .zqlat2 = 3,
3391
3392 //DQSINCTL, DATLAT aren't in ACTiming excel file
3393 .dqsinctl = 5, .datlat = 15
3394 },
3395 //LPDDR4 4X_800_BT_Div 8_DBI0.csv Read 0
3396 {
3397 .dramType = TYPE_LPDDR4, .freq = 400, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
3398 .readLat = 16, .writeLat = 8, .DivMode = DIV8_MODE,
3399
3400 .tras = 0, .tras_05T = 0,
3401 .trp = 0, .trp_05T = 1,
3402 .trpab = 1, .trpab_05T = 0,
3403 .trc = 0, .trc_05T = 0,
3404 .trfc = 16, .trfc_05T = 0,
3405 .trfcpb = 2, .trfcpb_05T = 0,
3406 .txp = 0, .txp_05T = 0,
3407 .trtp = 0, .trtp_05T = 1,
3408 .trcd = 2, .trcd_05T = 0,
3409 .twr = 5, .twr_05T = 0,
3410 .twtr = 4, .twtr_05T = 1,
3411 .tpbr2pbr = 2, .tpbr2pbr_05T = 0,
3412 .tpbr2act = 0, .tpbr2act_05T = 0,
3413 .tr2mrw = 8, .tr2mrw_05T = 1,
3414 .tw2mrw = 6, .tw2mrw_05T = 1,
3415 .tmrr2mrw = 7, .tmrr2mrw_05T = 1,
3416 .tmrw = 3, .tmrw_05T = 0,
3417 .tmrd = 3, .tmrd_05T = 0,
3418 .tmrwckel = 4, .tmrwckel_05T = 0,
3419 .tpde = 1, .tpde_05T = 1,
3420 .tpdx = 1, .tpdx_05T = 0,
3421 .tmrri = 3, .tmrri_05T = 1,
3422 .trrd = 0, .trrd_05T = 0,
3423 .trrd_4266 = 0, .trrd_4266_05T = 0,
3424 .tfaw = 0, .tfaw_05T = 0,
3425 .tfaw_4266 = 0, .tfaw_4266_05T = 0,
3426 .trtw_odt_off = 2, .trtw_odt_off_05T = 0,
3427 .trtw_odt_on = 4, .trtw_odt_on_05T = 0,
3428 .txrefcnt = 29,
3429 .tzqcs = 7,
3430 .xrtw2w_new_mode = 4,
3431 .xrtw2w_old_mode = 6,
3432 .xrtw2r_odt_on = 3,
3433 .xrtw2r_odt_off = 2,
3434 .xrtr2w_odt_on = 3,
3435 .xrtr2w_odt_off = 3,
3436 .xrtr2r_new_mode = 3,
3437 .xrtr2r_old_mode = 6,
3438 .tr2mrr = 4,
3439 .vrcgdis_prdcnt = 10,
3440 .hwset_mr2_op = 18,
3441 .hwset_mr13_op = 24,
3442 .hwset_vrcg_op = 16,
3443 .trcd_derate = 2, .trcd_derate_05T = 0,
3444 .trc_derate = 0, .trc_derate_05T = 0,
3445 .tras_derate = 0, .tras_derate_05T = 0,
3446 .trpab_derate = 1, .trpab_derate_05T = 0,
3447 .trp_derate = 0, .trp_derate_05T = 1,
3448 .trrd_derate = 0, .trrd_derate_05T = 1,
3449 .trtpd = 8, .trtpd_05T = 0,
3450 .twtpd = 7, .twtpd_05T = 1,
3451 .tmrr2w_odt_off = 4,
3452 .tmrr2w_odt_on = 6,
3453 .ckeprd = 1,
3454 .ckelckcnt = 2,
3455 .zqlat2 = 3,
3456
3457 //DQSINCTL, DATLAT aren't in ACTiming excel file
3458 .dqsinctl = 5, .datlat = 15
3459 },
3460 #endif
3461 #if SUPPORT_LP4_DDR400_ACTIM
3462 //LP4_DDR400 ACTiming---------------------------------
3463 //LPDDR4 4X_400_Div 4_DBI0.csv Read 0
3464 {
3465 .dramType = TYPE_LPDDR4, .freq = 200, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
3466 .readLat = 14, .writeLat = 8, .DivMode = DIV4_MODE,
3467
3468 .tras = 0, .tras_05T = 0,
3469 .trp = 0, .trp_05T = 0,
3470 .trpab = 1, .trpab_05T = 0,
3471 .trc = 0, .trc_05T = 0,
3472 .trfc = 16, .trfc_05T = 0,
3473 .trfcpb = 2, .trfcpb_05T = 0,
3474 .txp = 0, .txp_05T = 0,
3475 .trtp = 3, .trtp_05T = 0,
3476 .trcd = 2, .trcd_05T = 0,
3477 .twr = 11, .twr_05T = 0,
3478 .twtr = 10, .twtr_05T = 0,
3479 .tpbr2pbr = 2, .tpbr2pbr_05T = 0,
3480 .tpbr2act = 0, .tpbr2act_05T = 0,
3481 .tr2mrw = 16, .tr2mrw_05T = 0,
3482 .tw2mrw = 13, .tw2mrw_05T = 0,
3483 .tmrr2mrw = 13, .tmrr2mrw_05T = 0,
3484 .tmrw = 6, .tmrw_05T = 0,
3485 .tmrd = 6, .tmrd_05T = 0,
3486 .tmrwckel = 8, .tmrwckel_05T = 0,
3487 .tpde = 3, .tpde_05T = 0,
3488 .tpdx = 3, .tpdx_05T = 0,
3489 .tmrri = 5, .tmrri_05T = 0,
3490 .trrd = 1, .trrd_05T = 0,
3491 .trrd_4266 = 1, .trrd_4266_05T = 0,
3492 .tfaw = 0, .tfaw_05T = 0,
3493 .tfaw_4266 = 0, .tfaw_4266_05T = 0,
3494 .trtw_odt_off = 6, .trtw_odt_off_05T = 0,
3495 .trtw_odt_on = 10, .trtw_odt_on_05T = 0,
3496 .txrefcnt = 29,
3497 .tzqcs = 7,
3498 .xrtw2w_new_mode = 10,
3499 .xrtw2w_old_mode = 10,
3500 .xrtw2r_odt_on = 8,
3501 .xrtw2r_odt_off = 8,
3502 .xrtr2w_odt_on = 9,
3503 .xrtr2w_odt_off = 9,
3504 .xrtr2r_new_mode = 6,
3505 .xrtr2r_old_mode = 8,
3506 .tr2mrr = 8,
3507 .vrcgdis_prdcnt = 10,
3508 .hwset_mr2_op = 18,
3509 .hwset_mr13_op = 24,
3510 .hwset_vrcg_op = 16,
3511 .trcd_derate = 2, .trcd_derate_05T = 0,
3512 .trc_derate = 0, .trc_derate_05T = 0,
3513 .tras_derate = 0, .tras_derate_05T = 0,
3514 .trpab_derate = 1, .trpab_derate_05T = 0,
3515 .trp_derate = 0, .trp_derate_05T = 0,
3516 .trrd_derate = 1, .trrd_derate_05T = 0,
3517 .trtpd = 14, .trtpd_05T = 0,
3518 .twtpd = 14, .twtpd_05T = 0,
3519 .tmrr2w_odt_off = 9,
3520 .tmrr2w_odt_on = 11,
3521 .ckeprd = 2,
3522 .ckelckcnt = 3,
3523 .zqlat2 = 4,
3524
3525 //DQSINCTL, DATLAT aren't in ACTiming excel file
3526 .dqsinctl = 2, .datlat = 15
3527 },
3528 //LPDDR4 4X_400_BT_Div 4_DBI0.csv Read 0
3529 {
3530 .dramType = TYPE_LPDDR4, .freq = 200, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
3531 .readLat = 16, .writeLat = 8, .DivMode = DIV4_MODE,
3532
3533 .tras = 0, .tras_05T = 0,
3534 .trp = 0, .trp_05T = 0,
3535 .trpab = 1, .trpab_05T = 0,
3536 .trc = 0, .trc_05T = 0,
3537 .trfc = 16, .trfc_05T = 0,
3538 .trfcpb = 2, .trfcpb_05T = 0,
3539 .txp = 0, .txp_05T = 0,
3540 .trtp = 3, .trtp_05T = 0,
3541 .trcd = 2, .trcd_05T = 0,
3542 .twr = 11, .twr_05T = 0,
3543 .twtr = 10, .twtr_05T = 0,
3544 .tpbr2pbr = 2, .tpbr2pbr_05T = 0,
3545 .tpbr2act = 0, .tpbr2act_05T = 0,
3546 .tr2mrw = 17, .tr2mrw_05T = 0,
3547 .tw2mrw = 13, .tw2mrw_05T = 0,
3548 .tmrr2mrw = 14, .tmrr2mrw_05T = 0,
3549 .tmrw = 6, .tmrw_05T = 0,
3550 .tmrd = 6, .tmrd_05T = 0,
3551 .tmrwckel = 8, .tmrwckel_05T = 0,
3552 .tpde = 3, .tpde_05T = 0,
3553 .tpdx = 3, .tpdx_05T = 0,
3554 .tmrri = 5, .tmrri_05T = 0,
3555 .trrd = 1, .trrd_05T = 0,
3556 .trrd_4266 = 1, .trrd_4266_05T = 0,
3557 .tfaw = 0, .tfaw_05T = 0,
3558 .tfaw_4266 = 0, .tfaw_4266_05T = 0,
3559 .trtw_odt_off = 7, .trtw_odt_off_05T = 0,
3560 .trtw_odt_on = 11, .trtw_odt_on_05T = 0,
3561 .txrefcnt = 29,
3562 .tzqcs = 7,
3563 .xrtw2w_new_mode = 10,
3564 .xrtw2w_old_mode = 10,
3565 .xrtw2r_odt_on = 7,
3566 .xrtw2r_odt_off = 7,
3567 .xrtr2w_odt_on = 10,
3568 .xrtr2w_odt_off = 10,
3569 .xrtr2r_new_mode = 6,
3570 .xrtr2r_old_mode = 9,
3571 .tr2mrr = 8,
3572 .vrcgdis_prdcnt = 10,
3573 .hwset_mr2_op = 18,
3574 .hwset_mr13_op = 24,
3575 .hwset_vrcg_op = 16,
3576 .trcd_derate = 2, .trcd_derate_05T = 0,
3577 .trc_derate = 0, .trc_derate_05T = 0,
3578 .tras_derate = 0, .tras_derate_05T = 0,
3579 .trpab_derate = 1, .trpab_derate_05T = 0,
3580 .trp_derate = 0, .trp_derate_05T = 0,
3581 .trrd_derate = 1, .trrd_derate_05T = 0,
3582 .trtpd = 15, .trtpd_05T = 0,
3583 .twtpd = 14, .twtpd_05T = 0,
3584 .tmrr2w_odt_off = 10,
3585 .tmrr2w_odt_on = 12,
3586 .ckeprd = 2,
3587 .ckelckcnt = 3,
3588 .zqlat2 = 4,
3589
3590 //DQSINCTL, DATLAT aren't in ACTiming excel file
3591 .dqsinctl = 2, .datlat = 15
3592 },
3593 #endif
3594 };
3595
3596 #if (__LP5_COMBO__)
3597 const ACTime_T_LP5 ACTimingTbl_LP5[AC_TIMING_NUMBER_LP5] = {
3598 //----------LPDDR5---------------------------
3599 #if SUPPORT_LP5_DDR6400_ACTIM
3600 //LP5_DDR6400 ACTiming---------------------------------
3601 #if (ENABLE_READ_DBI == 1)
3602 //LPDDR5_6400_Div 16_DBI1.csv Read 1
3603 {
3604 .dramType = TYPE_LPDDR5, .freq = 3200, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1,
3605
3606 //BL (burst length) = 16, DRMC_Clock_Rate = 400.0
3607 .readLat = 20, .writeLat = 9, .DivMode = DIV16_MODE,
3608
3609 .tras = 8, .tras_05T = 0,
3610 .trp = 7, .trp_05T = 1,
3611 .trpab = 8, .trpab_05T = 1,
3612 .trc = 16, .trc_05T = 1,
3613 .trfc = 100, .trfc_05T = 0,
3614 .trfcpb = 44, .trfcpb_05T = 0,
3615 .txp = 2, .txp_05T = 1,
3616 .trtp = 1, .trtp_05T = 1,
3617 .trcd = 7, .trcd_05T = 1,
3618 .twr = 19, .twr_05T = 0,
3619 .twtr = 6, .twtr_05T = 0,
3620 .twtr_l = 10, .twtr_l_05T = 0,
3621 .tpbr2pbr = 28, .tpbr2pbr_05T = 0,
3622 .tpbr2act = 2, .tpbr2act_05T = 0,
3623 .tr2mrw = 15, .tr2mrw_05T = 0,
3624 .tw2mrw = 8, .tw2mrw_05T = 1,
3625 .tmrr2mrw = 13, .tmrr2mrw_05T = 0,
3626 .tmrw = 4, .tmrw_05T = 0,
3627 .tmrd = 6, .tmrd_05T = 1,
3628 .tmrwckel = 8, .tmrwckel_05T = 1,
3629 .tpde = 2, .tpde_05T = 1,
3630 .tpdx = 1, .tpdx_05T = 1,
3631 .tmrri = 12, .tmrri_05T = 0,
3632 .trrd = 2, .trrd_05T = 0,
3633 .tfaw = 0, .tfaw_05T = 0,
3634 .tr2w_odt_off = 5, .tr2w_odt_off_05T = 1,
3635 .tr2w_odt_on = 7, .tr2w_odt_on_05T = 0,
3636 .txrefcnt = 115,
3637 .wckrdoff = 13, .wckrdoff_05T = 0,
3638 .wckwroff = 7, .wckwroff_05T = 1,
3639 .tzqcs = 34,
3640 .xrtw2w_odt_off = 2,
3641 .xrtw2w_odt_on = 3,
3642 .xrtw2r_odt_off_otf_off = 0,
3643 .xrtw2r_odt_on_otf_off = 0,
3644 .xrtw2r_odt_off_otf_on = 3,
3645 .xrtw2r_odt_on_otf_on = 3,
3646 .xrtr2w_odt_off = 8,
3647 .xrtr2w_odt_on = 9,
3648 .xrtr2r_odt_off = 6,
3649 .xrtr2r_odt_on = 6,
3650 .xrtw2w_odt_off_wck = 6,
3651 .xrtw2w_odt_on_wck = 8,
3652 .xrtw2r_odt_off_wck = 3,
3653 .xrtw2r_odt_on_wck = 4,
3654 .xrtr2w_odt_off_wck = 11,
3655 .xrtr2w_odt_on_wck = 11,
3656 .xrtr2r_wck = 8,
3657 .tr2mrr = 4,
3658 .hwset_mr2_op = 187,
3659 .hwset_mr13_op = 74,
3660 .hwset_vrcg_op = 176,
3661 .vrcgdis_prdcnt = 40,
3662 .lp5_cmd1to2en = 0,
3663 .trtpd = 13, .trtpd_05T = 1,
3664 .twtpd = 21, .twtpd_05T = 1,
3665 .tmrr2w = 16,
3666 .ckeprd = 2,
3667 .ckelckcnt = 3,
3668 .tcsh_cscal = 3,
3669 .tcacsh = 2,
3670 .tcsh = 5,
3671 .trcd_derate = 8, .trcd_derate_05T = 0,
3672 .trc_derate = 17, .trc_derate_05T = 0,
3673 .tras_derate = 10, .tras_derate_05T = 0,
3674 .trpab_derate = 7, .trpab_derate_05T = 1,
3675 .trp_derate = 6, .trp_derate_05T = 0,
3676 .trrd_derate = 2, .trrd_derate_05T = 0,
3677 .zqlat2 = 12,
3678
3679 //DQSINCTL, DATLAT aren't in ACTiming excel file
3680 .dqsinctl = 7, .datlat = 10
3681 },
3682 //LPDDR5_6400_BT_Div 16_DBI1.csv Read 1
3683 {
3684 .dramType = TYPE_LPDDR5, .freq = 3200, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1,
3685 //BL (burst length) = 16, DRMC_Clock_Rate = 400.0
3686 .readLat = 18, .writeLat = 9, .DivMode = DIV16_MODE,
3687
3688 .tras = 8, .tras_05T = 0,
3689 .trp = 7, .trp_05T = 1,
3690 .trpab = 8, .trpab_05T = 1,
3691 .trc = 16, .trc_05T = 1,
3692 .trfc = 100, .trfc_05T = 0,
3693 .trfcpb = 44, .trfcpb_05T = 0,
3694 .txp = 2, .txp_05T = 1,
3695 .trtp = 1, .trtp_05T = 1,
3696 .trcd = 7, .trcd_05T = 1,
3697 .twr = 18, .twr_05T = 1,
3698 .twtr = 5, .twtr_05T = 0,
3699 .twtr_l = 9, .twtr_l_05T = 0,
3700 .tpbr2pbr = 28, .tpbr2pbr_05T = 0,
3701 .tpbr2act = 2, .tpbr2act_05T = 0,
3702 .tr2mrw = 14, .tr2mrw_05T = 0,
3703 .tw2mrw = 8, .tw2mrw_05T = 1,
3704 .tmrr2mrw = 12, .tmrr2mrw_05T = 0,
3705 .tmrw = 4, .tmrw_05T = 0,
3706 .tmrd = 6, .tmrd_05T = 1,
3707 .tmrwckel = 8, .tmrwckel_05T = 1,
3708 .tpde = 2, .tpde_05T = 1,
3709 .tpdx = 1, .tpdx_05T = 1,
3710 .tmrri = 12, .tmrri_05T = 0,
3711 .trrd = 2, .trrd_05T = 0,
3712 .tfaw = 0, .tfaw_05T = 0,
3713 .tr2w_odt_off = 4, .tr2w_odt_off_05T = 1,
3714 .tr2w_odt_on = 6, .tr2w_odt_on_05T = 0,
3715 .txrefcnt = 115,
3716 .wckrdoff = 12, .wckrdoff_05T = 0,
3717 .wckwroff = 7, .wckwroff_05T = 1,
3718 .tzqcs = 34,
3719 .xrtw2w_odt_off = 2,
3720 .xrtw2w_odt_on = 3,
3721 .xrtw2r_odt_off_otf_off = 0,
3722 .xrtw2r_odt_on_otf_off = 0,
3723 .xrtw2r_odt_off_otf_on = 3,
3724 .xrtw2r_odt_on_otf_on = 3,
3725 .xrtr2w_odt_off = 7,
3726 .xrtr2w_odt_on = 8,
3727 .xrtr2r_odt_off = 6,
3728 .xrtr2r_odt_on = 6,
3729 .xrtw2w_odt_off_wck = 6,
3730 .xrtw2w_odt_on_wck = 8,
3731 .xrtw2r_odt_off_wck = 4,
3732 .xrtw2r_odt_on_wck = 5,
3733 .xrtr2w_odt_off_wck = 10,
3734 .xrtr2w_odt_on_wck = 10,
3735 .xrtr2r_wck = 8,
3736 .tr2mrr = 3,
3737 .hwset_mr2_op = 187,
3738 .hwset_mr13_op = 74,
3739 .hwset_vrcg_op = 176,
3740 .vrcgdis_prdcnt = 40,
3741 .lp5_cmd1to2en = 0,
3742 .trtpd = 12, .trtpd_05T = 1,
3743 .twtpd = 21, .twtpd_05T = 0,
3744 .tmrr2w = 15,
3745 .ckeprd = 2,
3746 .ckelckcnt = 3,
3747 .tcsh_cscal = 3,
3748 .tcacsh = 2,
3749 .tcsh = 5,
3750 .trcd_derate = 8, .trcd_derate_05T = 0,
3751 .trc_derate = 17, .trc_derate_05T = 0,
3752 .tras_derate = 10, .tras_derate_05T = 0,
3753 .trpab_derate = 7, .trpab_derate_05T = 1,
3754 .trp_derate = 6, .trp_derate_05T = 0,
3755 .trrd_derate = 2, .trrd_derate_05T = 0,
3756 .zqlat2 = 12,
3757
3758 //DQSINCTL, DATLAT aren't in ACTiming excel file
3759 .dqsinctl = 7, .datlat = 10
3760 },
3761 #else //ENABLE_READ_DBI == 0)
3762 //LPDDR5_6400_Div 16_DBI0.csv Read 0
3763 {
3764 .dramType = TYPE_LPDDR5, .freq = 3200, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
3765 //BL (burst length) = 16, DRMC_Clock_Rate = 400.0
3766 .readLat = 18, .writeLat = 9, .DivMode = DIV16_MODE,
3767
3768 .tras = 8, .tras_05T = 0,
3769 .trp = 7, .trp_05T = 1,
3770 .trpab = 8, .trpab_05T = 1,
3771 .trc = 16, .trc_05T = 1,
3772 .trfc = 100, .trfc_05T = 0,
3773 .trfcpb = 44, .trfcpb_05T = 0,
3774 .txp = 2, .txp_05T = 1,
3775 .trtp = 1, .trtp_05T = 1,
3776 .trcd = 7, .trcd_05T = 1,
3777 .twr = 19, .twr_05T = 0,
3778 .twtr = 6, .twtr_05T = 0,
3779 .twtr_l = 10, .twtr_l_05T = 0,
3780 .tpbr2pbr = 28, .tpbr2pbr_05T = 0,
3781 .tpbr2act = 2, .tpbr2act_05T = 0,
3782 .tr2mrw = 14, .tr2mrw_05T = 0,
3783 .tw2mrw = 8, .tw2mrw_05T = 1,
3784 .tmrr2mrw = 12, .tmrr2mrw_05T = 0,
3785 .tmrw = 4, .tmrw_05T = 0,
3786 .tmrd = 6, .tmrd_05T = 1,
3787 .tmrwckel = 8, .tmrwckel_05T = 1,
3788 .tpde = 2, .tpde_05T = 1,
3789 .tpdx = 1, .tpdx_05T = 1,
3790 .tmrri = 12, .tmrri_05T = 0,
3791 .trrd = 2, .trrd_05T = 0,
3792 .tfaw = 0, .tfaw_05T = 0,
3793 .tr2w_odt_off = 4, .tr2w_odt_off_05T = 1,
3794 .tr2w_odt_on = 6, .tr2w_odt_on_05T = 0,
3795 .txrefcnt = 115,
3796 .wckrdoff = 12, .wckrdoff_05T = 0,
3797 .wckwroff = 7, .wckwroff_05T = 1,
3798 .tzqcs = 34,
3799 .xrtw2w_odt_off = 2,
3800 .xrtw2w_odt_on = 3,
3801 .xrtw2r_odt_off_otf_off = 0,
3802 .xrtw2r_odt_on_otf_off = 0,
3803 .xrtw2r_odt_off_otf_on = 3,
3804 .xrtw2r_odt_on_otf_on = 3,
3805 .xrtr2w_odt_off = 7,
3806 .xrtr2w_odt_on = 8,
3807 .xrtr2r_odt_off = 6,
3808 .xrtr2r_odt_on = 6,
3809 .xrtw2w_odt_off_wck = 6,
3810 .xrtw2w_odt_on_wck = 8,
3811 .xrtw2r_odt_off_wck = 4,
3812 .xrtw2r_odt_on_wck = 5,
3813 .xrtr2w_odt_off_wck = 10,
3814 .xrtr2w_odt_on_wck = 10,
3815 .xrtr2r_wck = 8,
3816 .tr2mrr = 3,
3817 .hwset_mr2_op = 187,
3818 .hwset_mr13_op = 74,
3819 .hwset_vrcg_op = 176,
3820 .vrcgdis_prdcnt = 40,
3821 .lp5_cmd1to2en = 0,
3822 .trtpd = 12, .trtpd_05T = 1,
3823 .twtpd = 21, .twtpd_05T = 1,
3824 .tmrr2w = 15,
3825 .ckeprd = 2,
3826 .ckelckcnt = 3,
3827 .tcsh_cscal = 3,
3828 .tcacsh = 2,
3829 .tcsh = 5,
3830 .trcd_derate = 8, .trcd_derate_05T = 0,
3831 .trc_derate = 17, .trc_derate_05T = 0,
3832 .tras_derate = 10, .tras_derate_05T = 0,
3833 .trpab_derate = 7, .trpab_derate_05T = 1,
3834 .trp_derate = 6, .trp_derate_05T = 0,
3835 .trrd_derate = 2, .trrd_derate_05T = 0,
3836 .zqlat2 = 12,
3837
3838 //DQSINCTL, DATLAT aren't in ACTiming excel file
3839 .dqsinctl = 7, .datlat = 10
3840 },
3841 //LPDDR5_6400_BT_Div 16_DBI0.csv Read 0
3842 {
3843 .dramType = TYPE_LPDDR5, .freq = 3200, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
3844 //BL (burst length) = 16, DRMC_Clock_Rate = 400.0
3845 .readLat = 17, .writeLat = 9, .DivMode = DIV16_MODE,
3846
3847 .tras = 8, .tras_05T = 0,
3848 .trp = 7, .trp_05T = 1,
3849 .trpab = 8, .trpab_05T = 1,
3850 .trc = 16, .trc_05T = 1,
3851 .trfc = 100, .trfc_05T = 0,
3852 .trfcpb = 44, .trfcpb_05T = 0,
3853 .txp = 2, .txp_05T = 1,
3854 .trtp = 1, .trtp_05T = 1,
3855 .trcd = 7, .trcd_05T = 1,
3856 .twr = 18, .twr_05T = 1,
3857 .twtr = 5, .twtr_05T = 0,
3858 .twtr_l = 9, .twtr_l_05T = 0,
3859 .tpbr2pbr = 28, .tpbr2pbr_05T = 0,
3860 .tpbr2act = 2, .tpbr2act_05T = 0,
3861 .tr2mrw = 13, .tr2mrw_05T = 1,
3862 .tw2mrw = 8, .tw2mrw_05T = 1,
3863 .tmrr2mrw = 11, .tmrr2mrw_05T = 1,
3864 .tmrw = 4, .tmrw_05T = 0,
3865 .tmrd = 6, .tmrd_05T = 1,
3866 .tmrwckel = 8, .tmrwckel_05T = 1,
3867 .tpde = 2, .tpde_05T = 1,
3868 .tpdx = 1, .tpdx_05T = 1,
3869 .tmrri = 12, .tmrri_05T = 0,
3870 .trrd = 2, .trrd_05T = 0,
3871 .tfaw = 0, .tfaw_05T = 0,
3872 .tr2w_odt_off = 4, .tr2w_odt_off_05T = 0,
3873 .tr2w_odt_on = 5, .tr2w_odt_on_05T = 1,
3874 .txrefcnt = 115,
3875 .wckrdoff = 11, .wckrdoff_05T = 1,
3876 .wckwroff = 7, .wckwroff_05T = 1,
3877 .tzqcs = 34,
3878 .xrtw2w_odt_off = 2,
3879 .xrtw2w_odt_on = 3,
3880 .xrtw2r_odt_off_otf_off = 0,
3881 .xrtw2r_odt_on_otf_off = 0,
3882 .xrtw2r_odt_off_otf_on = 3,
3883 .xrtw2r_odt_on_otf_on = 3,
3884 .xrtr2w_odt_off = 7,
3885 .xrtr2w_odt_on = 7,
3886 .xrtr2r_odt_off = 6,
3887 .xrtr2r_odt_on = 6,
3888 .xrtw2w_odt_off_wck = 6,
3889 .xrtw2w_odt_on_wck = 8,
3890 .xrtw2r_odt_off_wck = 4,
3891 .xrtw2r_odt_on_wck = 5,
3892 .xrtr2w_odt_off_wck = 10,
3893 .xrtr2w_odt_on_wck = 10,
3894 .xrtr2r_wck = 8,
3895 .tr2mrr = 2,
3896 .hwset_mr2_op = 187,
3897 .hwset_mr13_op = 74,
3898 .hwset_vrcg_op = 176,
3899 .vrcgdis_prdcnt = 40,
3900 .lp5_cmd1to2en = 0,
3901 .trtpd = 12, .trtpd_05T = 0,
3902 .twtpd = 21, .twtpd_05T = 0,
3903 .tmrr2w = 15,
3904 .ckeprd = 2,
3905 .ckelckcnt = 3,
3906 .tcsh_cscal = 3,
3907 .tcacsh = 2,
3908 .tcsh = 5,
3909 .trcd_derate = 8, .trcd_derate_05T = 0,
3910 .trc_derate = 17, .trc_derate_05T = 0,
3911 .tras_derate = 10, .tras_derate_05T = 0,
3912 .trpab_derate = 7, .trpab_derate_05T = 1,
3913 .trp_derate = 6, .trp_derate_05T = 0,
3914 .trrd_derate = 2, .trrd_derate_05T = 0,
3915 .zqlat2 = 12,
3916
3917 //DQSINCTL, DATLAT aren't in ACTiming excel file
3918 .dqsinctl = 7, .datlat = 10
3919 },
3920 #endif
3921 #endif
3922 #if SUPPORT_LP5_DDR5500_ACTIM
3923 //LP5_DDR5500 ACTiming---------------------------------
3924 #if ((ENABLE_READ_DBI == 1) || (LP5_DDR4266_RDBI_WORKAROUND == 1))
3925 //F5500_Div16_DB1_NT0_RG0_EC0.csv Read 1
3926 {
3927 .dramType = TYPE_LPDDR5, .freq = 2750, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1,
3928
3929 //BL (burst length) = 16, DRMC_Clock_Rate = 343.75
3930 .readLat = 17, .writeLat = 8, .DivMode = DIV16_MODE,
3931
3932 .tras = 5, .tras_05T = 1,
3933 .trp = 6, .trp_05T = 1,
3934 .trpab = 7, .trpab_05T = 1,
3935 .trc = 13, .trc_05T = 0,
3936 .trfc = 84, .trfc_05T = 1,
3937 .trfcpb = 36, .trfcpb_05T = 1,
3938 .txp = 2, .txp_05T = 0,
3939 .trtp = 1, .trtp_05T = 1,
3940 .trcd = 6, .trcd_05T = 1,
3941 .twr = 16, .twr_05T = 1,
3942 .twtr = 5, .twtr_05T = 0,
3943 .twtr_l = 8, .twtr_l_05T = 1,
3944 .tpbr2pbr = 23, .tpbr2pbr_05T = 0,
3945 .tpbr2act = 2, .tpbr2act_05T = 0,
3946 .tr2mrw = 13, .tr2mrw_05T = 1,
3947 .tw2mrw = 8, .tw2mrw_05T = 0,
3948 .tmrr2mrw = 11, .tmrr2mrw_05T = 1,
3949 .tmrw = 3, .tmrw_05T = 1,
3950 .tmrd = 5, .tmrd_05T = 1,
3951 .tmrwckel = 7, .tmrwckel_05T = 1,
3952 .tpde = 2, .tpde_05T = 1,
3953 .tpdx = 1, .tpdx_05T = 1,
3954 .tmrri = 10, .tmrri_05T = 1,
3955 .trrd = 2, .trrd_05T = 0,
3956 .tfaw = 0, .tfaw_05T = 0,
3957 .tr2w_odt_off = 4, .tr2w_odt_off_05T = 1,
3958 .tr2w_odt_on = 6, .tr2w_odt_on_05T = 0,
3959 .txrefcnt = 99,
3960 .wckrdoff = 11, .wckrdoff_05T = 1,
3961 .wckwroff = 7, .wckwroff_05T = 0,
3962 .tzqcs = 29,
3963 .xrtw2w_odt_off = 2,
3964 .xrtw2w_odt_on = 3,
3965 .xrtw2r_odt_off_otf_off = 0,
3966 .xrtw2r_odt_on_otf_off = 0,
3967 .xrtw2r_odt_off_otf_on = 3,
3968 .xrtw2r_odt_on_otf_on = 3,
3969 .xrtr2w_odt_off = 7,
3970 .xrtr2w_odt_on = 8,
3971 .xrtr2r_odt_off = 6,
3972 .xrtr2r_odt_on = 6,
3973 .xrtw2w_odt_off_wck = 6,
3974 .xrtw2w_odt_on_wck = 8,
3975 .xrtw2r_odt_off_wck = 3,
3976 .xrtw2r_odt_on_wck = 4,
3977 .xrtr2w_odt_off_wck = 10,
3978 .xrtr2w_odt_on_wck = 10,
3979 .xrtr2r_wck = 8,
3980 .tr2mrr = 2,
3981 .hwset_mr2_op = 153,
3982 .hwset_mr13_op = 74,
3983 .hwset_vrcg_op = 144,
3984 .vrcgdis_prdcnt = 35,
3985 .lp5_cmd1to2en = 0,
3986 .trtpd = 12, .trtpd_05T = 0,
3987 .twtpd = 19, .twtpd_05T = 0,
3988 .tmrr2w = 15,
3989 .ckeprd = 2,
3990 .ckelckcnt = 3,
3991 .tcsh_cscal = 3,
3992 .tcacsh = 2,
3993 .tcsh = 5,
3994 .trcd_derate = 7, .trcd_derate_05T = 0,
3995 .trc_derate = 13, .trc_derate_05T = 1,
3996 .tras_derate = 7, .tras_derate_05T = 0,
3997 .trpab_derate = 6, .trpab_derate_05T = 0,
3998 .trp_derate = 5, .trp_derate_05T = 0,
3999 .trrd_derate = 1, .trrd_derate_05T = 1,
4000 .zqlat2 = 11,
4001
4002 //DQSINCTL, DATLAT aren't in ACTiming excel file
4003 .dqsinctl = 6, .datlat = 19
4004 },
4005 //LPDDR5_DDR5500_Div 16_RDBI_ON_CBT_NORMAL_MODE
4006 {
4007 .dramType = TYPE_LPDDR5, .freq = 2750, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1,
4008 //BL (burst length) = 16, DRMC_Clock_Rate = 343.75
4009 .readLat = 16, .writeLat = 8, .DivMode = DIV16_MODE,
4010
4011 .tras = 5, .tras_05T = 1,
4012 .trp = 6, .trp_05T = 1,
4013 .trpab = 7, .trpab_05T = 1,
4014 .trc = 13, .trc_05T = 0,
4015 .trfc = 84, .trfc_05T = 1,
4016 .trfcpb = 36, .trfcpb_05T = 1,
4017 .txp = 2, .txp_05T = 0,
4018 .trtp = 1, .trtp_05T = 1,
4019 .trcd = 6, .trcd_05T = 1,
4020 .twr = 16, .twr_05T = 0,
4021 .twtr = 4, .twtr_05T = 1,
4022 .twtr_l = 8, .twtr_l_05T = 0,
4023 .tpbr2pbr = 23, .tpbr2pbr_05T = 0,
4024 .tpbr2act = 2, .tpbr2act_05T = 0,
4025 .tr2mrw = 13, .tr2mrw_05T = 0,
4026 .tw2mrw = 8, .tw2mrw_05T = 0,
4027 .tmrr2mrw = 11, .tmrr2mrw_05T = 0,
4028 .tmrw = 3, .tmrw_05T = 1,
4029 .tmrd = 5, .tmrd_05T = 1,
4030 .tmrwckel = 7, .tmrwckel_05T = 1,
4031 .tpde = 2, .tpde_05T = 1,
4032 .tpdx = 1, .tpdx_05T = 1,
4033 .tmrri = 10, .tmrri_05T = 1,
4034 .trrd = 2, .trrd_05T = 0,
4035 .tfaw = 0, .tfaw_05T = 0,
4036 .tr2w_odt_off = 4, .tr2w_odt_off_05T = 0,
4037 .tr2w_odt_on = 5, .tr2w_odt_on_05T = 1,
4038 .txrefcnt = 99,
4039 .wckrdoff = 11, .wckrdoff_05T = 0,
4040 .wckwroff = 7, .wckwroff_05T = 0,
4041 .tzqcs = 29,
4042 .xrtw2w_odt_off = 2,
4043 .xrtw2w_odt_on = 3,
4044 .xrtw2r_odt_off_otf_off = 0,
4045 .xrtw2r_odt_on_otf_off = 0,
4046 .xrtw2r_odt_off_otf_on = 3,
4047 .xrtw2r_odt_on_otf_on = 3,
4048 .xrtr2w_odt_off = 7,
4049 .xrtr2w_odt_on = 7,
4050 .xrtr2r_odt_off = 6,
4051 .xrtr2r_odt_on = 6,
4052 .xrtw2w_odt_off_wck = 6,
4053 .xrtw2w_odt_on_wck = 8,
4054 .xrtw2r_odt_off_wck = 4,
4055 .xrtw2r_odt_on_wck = 5,
4056 .xrtr2w_odt_off_wck = 10,
4057 .xrtr2w_odt_on_wck = 10,
4058 .xrtr2r_wck = 8,
4059 .tr2mrr = 2,
4060 .hwset_mr2_op = 153,
4061 .hwset_mr13_op = 74,
4062 .hwset_vrcg_op = 144,
4063 .vrcgdis_prdcnt = 35,
4064 .lp5_cmd1to2en = 0,
4065 .trtpd = 11, .trtpd_05T = 1,
4066 .twtpd = 18, .twtpd_05T = 1,
4067 .tmrr2w = 14,
4068 .ckeprd = 2,
4069 .ckelckcnt = 3,
4070 .tcsh_cscal = 3,
4071 .tcacsh = 2,
4072 .tcsh = 5,
4073 .trcd_derate = 7, .trcd_derate_05T = 0,
4074 .trc_derate = 13, .trc_derate_05T = 1,
4075 .tras_derate = 7, .tras_derate_05T = 0,
4076 .trpab_derate = 6, .trpab_derate_05T = 0,
4077 .trp_derate = 5, .trp_derate_05T = 0,
4078 .trrd_derate = 1, .trrd_derate_05T = 1,
4079 .zqlat2 = 11,
4080
4081 //DQSINCTL, DATLAT aren't in ACTiming excel file
4082 .dqsinctl = 6, .datlat = 19
4083 },
4084 #else //ENABLE_READ_DBI == 0
4085 //LPDDR5_DDR5500_Div 16_RDBI_OFF_CBT_BYTE_MODE1
4086 {
4087 .dramType = TYPE_LPDDR5, .freq = 2750, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
4088 //BL (burst length) = 16, DRMC_Clock_Rate = 343.75
4089 .readLat = 16, .writeLat = 8, .DivMode = DIV16_MODE,
4090
4091 .tras = 5, .tras_05T = 1,
4092 .trp = 6, .trp_05T = 1,
4093 .trpab = 7, .trpab_05T = 1,
4094 .trc = 13, .trc_05T = 0,
4095 .trfc = 84, .trfc_05T = 1,
4096 .trfcpb = 36, .trfcpb_05T = 1,
4097 .txp = 2, .txp_05T = 0,
4098 .trtp = 1, .trtp_05T = 1,
4099 .trcd = 6, .trcd_05T = 1,
4100 .twr = 16, .twr_05T = 1,
4101 .twtr = 5, .twtr_05T = 0,
4102 .twtr_l = 8, .twtr_l_05T = 1,
4103 .tpbr2pbr = 23, .tpbr2pbr_05T = 0,
4104 .tpbr2act = 2, .tpbr2act_05T = 0,
4105 .tr2mrw = 13, .tr2mrw_05T = 0,
4106 .tw2mrw = 8, .tw2mrw_05T = 0,
4107 .tmrr2mrw = 11, .tmrr2mrw_05T = 0,
4108 .tmrw = 3, .tmrw_05T = 1,
4109 .tmrd = 5, .tmrd_05T = 1,
4110 .tmrwckel = 7, .tmrwckel_05T = 1,
4111 .tpde = 2, .tpde_05T = 1,
4112 .tpdx = 1, .tpdx_05T = 1,
4113 .tmrri = 10, .tmrri_05T = 1,
4114 .trrd = 2, .trrd_05T = 0,
4115 .tfaw = 0, .tfaw_05T = 0,
4116 .tr2w_odt_off = 4, .tr2w_odt_off_05T = 0,
4117 .tr2w_odt_on = 5, .tr2w_odt_on_05T = 1,
4118 .txrefcnt = 99,
4119 .wckrdoff = 11, .wckrdoff_05T = 0,
4120 .wckwroff = 7, .wckwroff_05T = 0,
4121 .tzqcs = 29,
4122 .xrtw2w_odt_off = 2,
4123 .xrtw2w_odt_on = 3,
4124 .xrtw2r_odt_off_otf_off = 0,
4125 .xrtw2r_odt_on_otf_off = 0,
4126 .xrtw2r_odt_off_otf_on = 3,
4127 .xrtw2r_odt_on_otf_on = 3,
4128 .xrtr2w_odt_off = 7,
4129 .xrtr2w_odt_on = 7,
4130 .xrtr2r_odt_off = 6,
4131 .xrtr2r_odt_on = 6,
4132 .xrtw2w_odt_off_wck = 6,
4133 .xrtw2w_odt_on_wck = 8,
4134 .xrtw2r_odt_off_wck = 4,
4135 .xrtw2r_odt_on_wck = 5,
4136 .xrtr2w_odt_off_wck = 10,
4137 .xrtr2w_odt_on_wck = 10,
4138 .xrtr2r_wck = 8,
4139 .tr2mrr = 2,
4140 .hwset_mr2_op = 153,
4141 .hwset_mr13_op = 74,
4142 .hwset_vrcg_op = 144,
4143 .vrcgdis_prdcnt = 35,
4144 .lp5_cmd1to2en = 0,
4145 .trtpd = 11, .trtpd_05T = 1,
4146 .twtpd = 19, .twtpd_05T = 0,
4147 .tmrr2w = 14,
4148 .ckeprd = 2,
4149 .ckelckcnt = 3,
4150 .tcsh_cscal = 3,
4151 .tcacsh = 2,
4152 .tcsh = 5,
4153 .trcd_derate = 7, .trcd_derate_05T = 0,
4154 .trc_derate = 13, .trc_derate_05T = 1,
4155 .tras_derate = 7, .tras_derate_05T = 0,
4156 .trpab_derate = 6, .trpab_derate_05T = 0,
4157 .trp_derate = 5, .trp_derate_05T = 0,
4158 .trrd_derate = 1, .trrd_derate_05T = 1,
4159 .zqlat2 = 11,
4160
4161 //DQSINCTL, DATLAT aren't in ACTiming excel file
4162 .dqsinctl = 6, .datlat = 19
4163 },
4164 {
4165 .dramType = TYPE_LPDDR5, .freq = 2750, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
4166 //BL (burst length) = 16, DRMC_Clock_Rate = 343.75
4167 .readLat = 15, .writeLat = 8, .DivMode = DIV16_MODE,
4168
4169 .tras = 5, .tras_05T = 1,
4170 .trp = 6, .trp_05T = 1,
4171 .trpab = 7, .trpab_05T = 1,
4172 .trc = 13, .trc_05T = 0,
4173 .trfc = 84, .trfc_05T = 1,
4174 .trfcpb = 36, .trfcpb_05T = 1,
4175 .txp = 2, .txp_05T = 0,
4176 .trtp = 1, .trtp_05T = 1,
4177 .trcd = 6, .trcd_05T = 1,
4178 .twr = 16, .twr_05T = 0,
4179 .twtr = 4, .twtr_05T = 1,
4180 .twtr_l = 8, .twtr_l_05T = 0,
4181 .tpbr2pbr = 23, .tpbr2pbr_05T = 0,
4182 .tpbr2act = 2, .tpbr2act_05T = 0,
4183 .tr2mrw = 12, .tr2mrw_05T = 1,
4184 .tw2mrw = 8, .tw2mrw_05T = 0,
4185 .tmrr2mrw = 10, .tmrr2mrw_05T = 1,
4186 .tmrw = 3, .tmrw_05T = 1,
4187 .tmrd = 5, .tmrd_05T = 1,
4188 .tmrwckel = 7, .tmrwckel_05T = 1,
4189 .tpde = 2, .tpde_05T = 1,
4190 .tpdx = 1, .tpdx_05T = 1,
4191 .tmrri = 10, .tmrri_05T = 1,
4192 .trrd = 2, .trrd_05T = 0,
4193 .tfaw = 0, .tfaw_05T = 0,
4194 .tr2w_odt_off = 3, .tr2w_odt_off_05T = 1,
4195 .tr2w_odt_on = 5, .tr2w_odt_on_05T = 0,
4196 .txrefcnt = 99,
4197 .wckrdoff = 10, .wckrdoff_05T = 1,
4198 .wckwroff = 7, .wckwroff_05T = 0,
4199 .tzqcs = 29,
4200 .xrtw2w_odt_off = 2,
4201 .xrtw2w_odt_on = 3,
4202 .xrtw2r_odt_off_otf_off = 0,
4203 .xrtw2r_odt_on_otf_off = 1,
4204 .xrtw2r_odt_off_otf_on = 3,
4205 .xrtw2r_odt_on_otf_on = 3,
4206 .xrtr2w_odt_off = 6,
4207 .xrtr2w_odt_on = 7,
4208 .xrtr2r_odt_off = 6,
4209 .xrtr2r_odt_on = 6,
4210 .xrtw2w_odt_off_wck = 6,
4211 .xrtw2w_odt_on_wck = 8,
4212 .xrtw2r_odt_off_wck = 4,
4213 .xrtw2r_odt_on_wck = 5,
4214 .xrtr2w_odt_off_wck = 9,
4215 .xrtr2w_odt_on_wck = 9,
4216 .xrtr2r_wck = 8,
4217 .tr2mrr = 1,
4218 .hwset_mr2_op = 153,
4219 .hwset_mr13_op = 74,
4220 .hwset_vrcg_op = 144,
4221 .vrcgdis_prdcnt = 35,
4222 .lp5_cmd1to2en = 0,
4223 .trtpd = 11, .trtpd_05T = 0,
4224 .twtpd = 18, .twtpd_05T = 1,
4225 .tmrr2w = 14,
4226 .ckeprd = 2,
4227 .ckelckcnt = 3,
4228 .tcsh_cscal = 3,
4229 .tcacsh = 2,
4230 .tcsh = 5,
4231 .trcd_derate = 7, .trcd_derate_05T = 0,
4232 .trc_derate = 13, .trc_derate_05T = 1,
4233 .tras_derate = 7, .tras_derate_05T = 0,
4234 .trpab_derate = 6, .trpab_derate_05T = 0,
4235 .trp_derate = 5, .trp_derate_05T = 0,
4236 .trrd_derate = 1, .trrd_derate_05T = 1,
4237 .zqlat2 = 11,
4238
4239 //DQSINCTL, DATLAT aren't in ACTiming excel file
4240 .dqsinctl = 6, .datlat = 19
4241 },
4242 #endif
4243 #endif
4244 #if SUPPORT_LP5_DDR4266_ACTIM
4245 //LP5_DDR4266 ACTiming---------------------------------
4246 #if ((ENABLE_READ_DBI == 1) || (LP5_DDR4266_RDBI_WORKAROUND == 1))
4247 //LPDDR5_4266_Div 8_CKR4_DBI1.csv Read 1
4248 {
4249 .dramType = TYPE_LPDDR5, .freq = 2133, .cbtMode = CBT_BYTE_MODE1, .readDBI = 1,
4250
4251 //BL (burst length) = 16, DRMC_Clock_Rate = 533.25
4252 .readLat = 14, .writeLat = 6, .DivMode = DIV8_MODE,
4253
4254 .tras = 14, .tras_05T = 0,
4255 .trp = 10, .trp_05T = 0,
4256 .trpab = 12, .trpab_05T = 0,
4257 .trc = 25, .trc_05T = 0,
4258 .trfc = 138, .trfc_05T = 0,
4259 .trfcpb = 63, .trfcpb_05T = 0,
4260 .txp = 5, .txp_05T = 0,
4261 .trtp = 4, .trtp_05T = 0,
4262 .trcd = 10, .trcd_05T = 0,
4263 .twr = 27, .twr_05T = 0,
4264 .twtr = 10, .twtr_05T = 0,
4265 .twtr_l = 16, .twtr_l_05T = 0,
4266 .tpbr2pbr = 40, .tpbr2pbr_05T = 0,
4267 .tpbr2act = 3, .tpbr2act_05T = 0,
4268 .tr2mrw = 23, .tr2mrw_05T = 0,
4269 .tw2mrw = 14, .tw2mrw_05T = 0,
4270 .tmrr2mrw = 21, .tmrr2mrw_05T = 0,
4271 .tmrw = 6, .tmrw_05T = 0,
4272 .tmrd = 9, .tmrd_05T = 0,
4273 .tmrwckel = 13, .tmrwckel_05T = 0,
4274 .tpde = 5, .tpde_05T = 0,
4275 .tpdx = 3, .tpdx_05T = 0,
4276 .tmrri = 17, .tmrri_05T = 0,
4277 .trrd = 3, .trrd_05T = 0,
4278 .tfaw = 3, .tfaw_05T = 0,
4279 .tr2w_odt_off = 11, .tr2w_odt_off_05T = 0,
4280 .tr2w_odt_on = 15, .tr2w_odt_on_05T = 0,
4281 .txrefcnt = 154,
4282 .wckrdoff = 20, .wckrdoff_05T = 0,
4283 .wckwroff = 12, .wckwroff_05T = 0,
4284 .tzqcs = 46,
4285 .xrtw2w_odt_off = 5,
4286 .xrtw2w_odt_on = 7,
4287 .xrtw2r_odt_off_otf_off = 0,
4288 .xrtw2r_odt_on_otf_off = 0,
4289 .xrtw2r_odt_off_otf_on = 3,
4290 .xrtw2r_odt_on_otf_on = 3,
4291 .xrtr2w_odt_off = 12,
4292 .xrtr2w_odt_on = 14,
4293 .xrtr2r_odt_off = 9,
4294 .xrtr2r_odt_on = 9,
4295 .xrtw2w_odt_off_wck = 10,
4296 .xrtw2w_odt_on_wck = 12,
4297 .xrtw2r_odt_off_wck = 6,
4298 .xrtw2r_odt_on_wck = 7,
4299 .xrtr2w_odt_off_wck = 18,
4300 .xrtr2w_odt_on_wck = 18,
4301 .xrtr2r_wck = 14,
4302 .tr2mrr = 13,
4303 .hwset_mr2_op = 119,
4304 .hwset_mr13_op = 74,
4305 .hwset_vrcg_op = 112,
4306 .vrcgdis_prdcnt = 54,
4307 .lp5_cmd1to2en = 1,
4308 .trtpd = 19, .trtpd_05T = 0,
4309 .twtpd = 31, .twtpd_05T = 0,
4310 .tmrr2w = 23,
4311 .ckeprd = 3,
4312 .ckelckcnt = 5,
4313 .tcsh_cscal = 5,
4314 .tcacsh = 3,
4315 .tcsh = 4,
4316 .trcd_derate = 11, .trcd_derate_05T = 0,
4317 .trc_derate = 26, .trc_derate_05T = 0,
4318 .tras_derate = 17, .tras_derate_05T = 0,
4319 .trpab_derate = 10, .trpab_derate_05T = 0,
4320 .trp_derate = 8, .trp_derate_05T = 0,
4321 .trrd_derate = 3, .trrd_derate_05T = 0,
4322 .zqlat2 = 16,
4323
4324 //DQSINCTL, DATLAT aren't in ACTiming excel file
4325 .dqsinctl = 10, .datlat = 19
4326 },
4327 //LPDDR5_4266_BT_Div 8_CKR4_DBI1.csv Read 1
4328 {
4329 .dramType = TYPE_LPDDR5, .freq = 2133, .cbtMode = CBT_NORMAL_MODE, .readDBI = 1,
4330 //BL (burst length) = 16, DRMC_Clock_Rate = 533.25
4331 .readLat = 13, .writeLat = 6, .DivMode = DIV8_MODE,
4332
4333 .tras = 14, .tras_05T = 0,
4334 .trp = 10, .trp_05T = 0,
4335 .trpab = 12, .trpab_05T = 0,
4336 .trc = 25, .trc_05T = 0,
4337 .trfc = 138, .trfc_05T = 0,
4338 .trfcpb = 63, .trfcpb_05T = 0,
4339 .txp = 5, .txp_05T = 0,
4340 .trtp = 4, .trtp_05T = 0,
4341 .trcd = 10, .trcd_05T = 0,
4342 .twr = 26, .twr_05T = 0,
4343 .twtr = 9, .twtr_05T = 0,
4344 .twtr_l = 15, .twtr_l_05T = 0,
4345 .tpbr2pbr = 40, .tpbr2pbr_05T = 0,
4346 .tpbr2act = 3, .tpbr2act_05T = 0,
4347 .tr2mrw = 22, .tr2mrw_05T = 0,
4348 .tw2mrw = 14, .tw2mrw_05T = 0,
4349 .tmrr2mrw = 20, .tmrr2mrw_05T = 0,
4350 .tmrw = 6, .tmrw_05T = 0,
4351 .tmrd = 9, .tmrd_05T = 0,
4352 .tmrwckel = 13, .tmrwckel_05T = 0,
4353 .tpde = 5, .tpde_05T = 0,
4354 .tpdx = 3, .tpdx_05T = 0,
4355 .tmrri = 17, .tmrri_05T = 0,
4356 .trrd = 3, .trrd_05T = 0,
4357 .tfaw = 3, .tfaw_05T = 0,
4358 .tr2w_odt_off = 10, .tr2w_odt_off_05T = 0,
4359 .tr2w_odt_on = 14, .tr2w_odt_on_05T = 0,
4360 .txrefcnt = 154,
4361 .wckrdoff = 19, .wckrdoff_05T = 0,
4362 .wckwroff = 12, .wckwroff_05T = 0,
4363 .tzqcs = 46,
4364 .xrtw2w_odt_off = 5,
4365 .xrtw2w_odt_on = 7,
4366 .xrtw2r_odt_off_otf_off = 0,
4367 .xrtw2r_odt_on_otf_off = 0,
4368 .xrtw2r_odt_off_otf_on = 3,
4369 .xrtw2r_odt_on_otf_on = 3,
4370 .xrtr2w_odt_off = 11,
4371 .xrtr2w_odt_on = 13,
4372 .xrtr2r_odt_off = 9,
4373 .xrtr2r_odt_on = 9,
4374 .xrtw2w_odt_off_wck = 10,
4375 .xrtw2w_odt_on_wck = 12,
4376 .xrtw2r_odt_off_wck = 7,
4377 .xrtw2r_odt_on_wck = 8,
4378 .xrtr2w_odt_off_wck = 17,
4379 .xrtr2w_odt_on_wck = 17,
4380 .xrtr2r_wck = 14,
4381 .tr2mrr = 12,
4382 .hwset_mr2_op = 119,
4383 .hwset_mr13_op = 74,
4384 .hwset_vrcg_op = 112,
4385 .vrcgdis_prdcnt = 54,
4386 .lp5_cmd1to2en = 1,
4387 .trtpd = 18, .trtpd_05T = 0,
4388 .twtpd = 30, .twtpd_05T = 0,
4389 .tmrr2w = 22,
4390 .ckeprd = 3,
4391 .ckelckcnt = 5,
4392 .tcsh_cscal = 5,
4393 .tcacsh = 3,
4394 .tcsh = 4,
4395 .trcd_derate = 11, .trcd_derate_05T = 0,
4396 .trc_derate = 26, .trc_derate_05T = 0,
4397 .tras_derate = 17, .tras_derate_05T = 0,
4398 .trpab_derate = 10, .trpab_derate_05T = 0,
4399 .trp_derate = 8, .trp_derate_05T = 0,
4400 .trrd_derate = 3, .trrd_derate_05T = 0,
4401 .zqlat2 = 16,
4402
4403 //DQSINCTL, DATLAT aren't in ACTiming excel file
4404 .dqsinctl = 10, .datlat = 19
4405 },
4406 #else //ENABLE_READ_DBI == 0)
4407 //LPDDR5_4266_Div 8_CKR4_DBI0.csv Read 0
4408 {
4409 .dramType = TYPE_LPDDR5, .freq = 2133, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
4410 //BL (burst length) = 16, DRMC_Clock_Rate = 533.25
4411 .readLat = 13, .writeLat = 6, .DivMode = DIV8_MODE,
4412
4413 .tras = 14, .tras_05T = 0,
4414 .trp = 10, .trp_05T = 0,
4415 .trpab = 12, .trpab_05T = 0,
4416 .trc = 25, .trc_05T = 0,
4417 .trfc = 138, .trfc_05T = 0,
4418 .trfcpb = 63, .trfcpb_05T = 0,
4419 .txp = 5, .txp_05T = 0,
4420 .trtp = 4, .trtp_05T = 0,
4421 .trcd = 10, .trcd_05T = 0,
4422 .twr = 27, .twr_05T = 0,
4423 .twtr = 10, .twtr_05T = 0,
4424 .twtr_l = 16, .twtr_l_05T = 0,
4425 .tpbr2pbr = 40, .tpbr2pbr_05T = 0,
4426 .tpbr2act = 3, .tpbr2act_05T = 0,
4427 .tr2mrw = 22, .tr2mrw_05T = 0,
4428 .tw2mrw = 14, .tw2mrw_05T = 0,
4429 .tmrr2mrw = 20, .tmrr2mrw_05T = 0,
4430 .tmrw = 6, .tmrw_05T = 0,
4431 .tmrd = 9, .tmrd_05T = 0,
4432 .tmrwckel = 13, .tmrwckel_05T = 0,
4433 .tpde = 5, .tpde_05T = 0,
4434 .tpdx = 3, .tpdx_05T = 0,
4435 .tmrri = 17, .tmrri_05T = 0,
4436 .trrd = 3, .trrd_05T = 0,
4437 .tfaw = 3, .tfaw_05T = 0,
4438 .tr2w_odt_off = 10, .tr2w_odt_off_05T = 0,
4439 .tr2w_odt_on = 14, .tr2w_odt_on_05T = 0,
4440 .txrefcnt = 154,
4441 .wckrdoff = 19, .wckrdoff_05T = 0,
4442 .wckwroff = 12, .wckwroff_05T = 0,
4443 .tzqcs = 46,
4444 .xrtw2w_odt_off = 5,
4445 .xrtw2w_odt_on = 7,
4446 .xrtw2r_odt_off_otf_off = 0,
4447 .xrtw2r_odt_on_otf_off = 0,
4448 .xrtw2r_odt_off_otf_on = 3,
4449 .xrtw2r_odt_on_otf_on = 3,
4450 .xrtr2w_odt_off = 11,
4451 .xrtr2w_odt_on = 13,
4452 .xrtr2r_odt_off = 9,
4453 .xrtr2r_odt_on = 9,
4454 .xrtw2w_odt_off_wck = 10,
4455 .xrtw2w_odt_on_wck = 12,
4456 .xrtw2r_odt_off_wck = 7,
4457 .xrtw2r_odt_on_wck = 8,
4458 .xrtr2w_odt_off_wck = 17,
4459 .xrtr2w_odt_on_wck = 17,
4460 .xrtr2r_wck = 14,
4461 .tr2mrr = 12,
4462 .hwset_mr2_op = 119,
4463 .hwset_mr13_op = 74,
4464 .hwset_vrcg_op = 112,
4465 .vrcgdis_prdcnt = 54,
4466 .lp5_cmd1to2en = 1,
4467 .trtpd = 18, .trtpd_05T = 0,
4468 .twtpd = 31, .twtpd_05T = 0,
4469 .tmrr2w = 22,
4470 .ckeprd = 3,
4471 .ckelckcnt = 5,
4472 .tcsh_cscal = 5,
4473 .tcacsh = 3,
4474 .tcsh = 4,
4475 .trcd_derate = 11, .trcd_derate_05T = 0,
4476 .trc_derate = 26, .trc_derate_05T = 0,
4477 .tras_derate = 17, .tras_derate_05T = 0,
4478 .trpab_derate = 10, .trpab_derate_05T = 0,
4479 .trp_derate = 8, .trp_derate_05T = 0,
4480 .trrd_derate = 3, .trrd_derate_05T = 0,
4481 .zqlat2 = 16,
4482
4483 //DQSINCTL, DATLAT aren't in ACTiming excel file
4484 .dqsinctl = 10, .datlat = 19
4485 },
4486 //LPDDR5_4266_BT_Div 8_CKR4_DBI0.csv Read 0
4487 {
4488 .dramType = TYPE_LPDDR5, .freq = 2133, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
4489 //BL (burst length) = 16, DRMC_Clock_Rate = 533.25
4490 .readLat = 12, .writeLat = 6, .DivMode = DIV8_MODE,
4491
4492 .tras = 14, .tras_05T = 0,
4493 .trp = 10, .trp_05T = 0,
4494 .trpab = 12, .trpab_05T = 0,
4495 .trc = 25, .trc_05T = 0,
4496 .trfc = 138, .trfc_05T = 0,
4497 .trfcpb = 63, .trfcpb_05T = 0,
4498 .txp = 5, .txp_05T = 0,
4499 .trtp = 4, .trtp_05T = 0,
4500 .trcd = 10, .trcd_05T = 0,
4501 .twr = 26, .twr_05T = 0,
4502 .twtr = 9, .twtr_05T = 0,
4503 .twtr_l = 15, .twtr_l_05T = 0,
4504 .tpbr2pbr = 40, .tpbr2pbr_05T = 0,
4505 .tpbr2act = 3, .tpbr2act_05T = 0,
4506 .tr2mrw = 21, .tr2mrw_05T = 0,
4507 .tw2mrw = 14, .tw2mrw_05T = 0,
4508 .tmrr2mrw = 19, .tmrr2mrw_05T = 0,
4509 .tmrw = 6, .tmrw_05T = 0,
4510 .tmrd = 9, .tmrd_05T = 0,
4511 .tmrwckel = 13, .tmrwckel_05T = 0,
4512 .tpde = 5, .tpde_05T = 0,
4513 .tpdx = 3, .tpdx_05T = 0,
4514 .tmrri = 17, .tmrri_05T = 0,
4515 .trrd = 3, .trrd_05T = 0,
4516 .tfaw = 3, .tfaw_05T = 0,
4517 .tr2w_odt_off = 9, .tr2w_odt_off_05T = 0,
4518 .tr2w_odt_on = 13, .tr2w_odt_on_05T = 0,
4519 .txrefcnt = 154,
4520 .wckrdoff = 18, .wckrdoff_05T = 0,
4521 .wckwroff = 12, .wckwroff_05T = 0,
4522 .tzqcs = 46,
4523 .xrtw2w_odt_off = 5,
4524 .xrtw2w_odt_on = 7,
4525 .xrtw2r_odt_off_otf_off = 0,
4526 .xrtw2r_odt_on_otf_off = 1,
4527 .xrtw2r_odt_off_otf_on = 3,
4528 .xrtw2r_odt_on_otf_on = 3,
4529 .xrtr2w_odt_off = 10,
4530 .xrtr2w_odt_on = 12,
4531 .xrtr2r_odt_off = 9,
4532 .xrtr2r_odt_on = 9,
4533 .xrtw2w_odt_off_wck = 10,
4534 .xrtw2w_odt_on_wck = 12,
4535 .xrtw2r_odt_off_wck = 8,
4536 .xrtw2r_odt_on_wck = 9,
4537 .xrtr2w_odt_off_wck = 16,
4538 .xrtr2w_odt_on_wck = 16,
4539 .xrtr2r_wck = 14,
4540 .tr2mrr = 11,
4541 .hwset_mr2_op = 119,
4542 .hwset_mr13_op = 74,
4543 .hwset_vrcg_op = 112,
4544 .vrcgdis_prdcnt = 54,
4545 .lp5_cmd1to2en = 1,
4546 .trtpd = 17, .trtpd_05T = 0,
4547 .twtpd = 30, .twtpd_05T = 0,
4548 .tmrr2w = 21,
4549 .ckeprd = 3,
4550 .ckelckcnt = 5,
4551 .tcsh_cscal = 5,
4552 .tcacsh = 3,
4553 .tcsh = 4,
4554 .trcd_derate = 11, .trcd_derate_05T = 0,
4555 .trc_derate = 26, .trc_derate_05T = 0,
4556 .tras_derate = 17, .tras_derate_05T = 0,
4557 .trpab_derate = 10, .trpab_derate_05T = 0,
4558 .trp_derate = 8, .trp_derate_05T = 0,
4559 .trrd_derate = 3, .trrd_derate_05T = 0,
4560 .zqlat2 = 16,
4561
4562 //DQSINCTL, DATLAT aren't in ACTiming excel file
4563 .dqsinctl = 10, .datlat = 19
4564 },
4565 #endif
4566 #endif
4567 #if SUPPORT_LP5_DDR3200_ACTIM
4568 //LP5_DDR3200 ACTiming---------------------------------
4569 //LPDDR5_3200_Div 8_CKR2_DBI1.csv Read 0
4570 {
4571 .dramType = TYPE_LPDDR5, .freq = 1600, .cbtMode = CBT_BYTE_MODE1, .readDBI = 0,
4572
4573 //BL (burst length) = 16, DRMC_Clock_Rate = 400.0
4574 .readLat = 20, .writeLat = 10, .DivMode = DIV8_MODE,
4575
4576 .tras = 8, .tras_05T = 0,
4577 .trp = 7, .trp_05T = 1,
4578 .trpab = 8, .trpab_05T = 1,
4579 .trc = 16, .trc_05T = 1,
4580 .trfc = 140, .trfc_05T = 0,
4581 .trfcpb = 64, .trfcpb_05T = 0,
4582 .txp = 2, .txp_05T = 1,
4583 .trtp = 2, .trtp_05T = 0,
4584 .trcd = 7, .trcd_05T = 1,
4585 .twr = 19, .twr_05T = 0,
4586 .twtr = 10, .twtr_05T = 0,
4587 .twtr_l = 10, .twtr_l_05T = 0,
4588 .tpbr2pbr = 36, .tpbr2pbr_05T = 0,
4589 .tpbr2act = 3, .tpbr2act_05T = 0,
4590 .tr2mrw = 15, .tr2mrw_05T = 0,
4591 .tw2mrw = 10, .tw2mrw_05T = 0,
4592 .tmrr2mrw = 14, .tmrr2mrw_05T = 0,
4593 .tmrw = 4, .tmrw_05T = 0,
4594 .tmrd = 6, .tmrd_05T = 1,
4595 .tmrwckel = 8, .tmrwckel_05T = 1,
4596 .tpde = 2, .tpde_05T = 1,
4597 .tpdx = 1, .tpdx_05T = 1,
4598 .tmrri = 12, .tmrri_05T = 0,
4599 .trrd = 2, .trrd_05T = 0,
4600 .tfaw = 0, .tfaw_05T = 0,
4601 .tr2w_odt_off = 4, .tr2w_odt_off_05T = 0,
4602 .tr2w_odt_on = 6, .tr2w_odt_on_05T = 0,
4603 .txrefcnt = 115,
4604 .wckrdoff = 13, .wckrdoff_05T = 0,
4605 .wckwroff = 8, .wckwroff_05T = 0,
4606 .tzqcs = 34,
4607 .xrtw2w_odt_off = 6,
4608 .xrtw2w_odt_on = 9,
4609 .xrtw2r_odt_off_otf_off = 3,
4610 .xrtw2r_odt_on_otf_off = 3,
4611 .xrtw2r_odt_off_otf_on = 3,
4612 .xrtw2r_odt_on_otf_on = 3,
4613 .xrtr2w_odt_off = 9,
4614 .xrtr2w_odt_on = 10,
4615 .xrtr2r_odt_off = 8,
4616 .xrtr2r_odt_on = 8,
4617 .xrtw2w_odt_off_wck = 7,
4618 .xrtw2w_odt_on_wck = 9,
4619 .xrtw2r_odt_off_wck = 5,
4620 .xrtw2r_odt_on_wck = 6,
4621 .xrtr2w_odt_off_wck = 12,
4622 .xrtr2w_odt_on_wck = 12,
4623 .xrtr2r_wck = 10,
4624 .tr2mrr = 3,
4625 .hwset_mr2_op = 45,
4626 .hwset_mr13_op = 216,
4627 .hwset_vrcg_op = 208,
4628 .vrcgdis_prdcnt = 40,
4629 .lp5_cmd1to2en = 0,
4630 .trtpd = 13, .trtpd_05T = 1,
4631 .twtpd = 13, .twtpd_05T = 0,
4632 .tmrr2w = 16,
4633 .ckeprd = 4,
4634 .ckelckcnt = 3,
4635 .tcsh_cscal = 3,
4636 .tcacsh = 2,
4637 .tcsh = 5,
4638 .trcd_derate = 8, .trcd_derate_05T = 0,
4639 .trc_derate = 17, .trc_derate_05T = 0,
4640 .tras_derate = 10, .tras_derate_05T = 0,
4641 .trpab_derate = 7, .trpab_derate_05T = 1,
4642 .trp_derate = 6, .trp_derate_05T = 0,
4643 .trrd_derate = 2, .trrd_derate_05T = 0,
4644 .zqlat2 = 12,
4645
4646 //DQSINCTL, DATLAT aren't in ACTiming excel file
4647 .dqsinctl = 7, .datlat = 15
4648 },
4649 //LPDDR5_3200_BT_Div 8_CKR2_DBI1.csv Read 0
4650 {
4651 .dramType = TYPE_LPDDR5, .freq = 1600, .cbtMode = CBT_NORMAL_MODE, .readDBI = 0,
4652 //BL (burst length) = 16, DRMC_Clock_Rate = 400.0
4653 .readLat = 18, .writeLat = 10, .DivMode = DIV8_MODE,
4654
4655 .tras = 8, .tras_05T = 0,
4656 .trp = 7, .trp_05T = 1,
4657 .trpab = 8, .trpab_05T = 1,
4658 .trc = 16, .trc_05T = 1,
4659 .trfc = 140, .trfc_05T = 0,
4660 .trfcpb = 64, .trfcpb_05T = 0,
4661 .txp = 2, .txp_05T = 1,
4662 .trtp = 2, .trtp_05T = 0,
4663 .trcd = 7, .trcd_05T = 1,
4664 .twr = 19, .twr_05T = -2,
4665 .twtr = 9, .twtr_05T = 0,
4666 .twtr_l = 9, .twtr_l_05T = 0,
4667 .tpbr2pbr = 36, .tpbr2pbr_05T = 0,
4668 .tpbr2act = 3, .tpbr2act_05T = 0,
4669 .tr2mrw = 14, .tr2mrw_05T = 0,
4670 .tw2mrw = 10, .tw2mrw_05T = 0,
4671 .tmrr2mrw = 13, .tmrr2mrw_05T = 0,
4672 .tmrw = 4, .tmrw_05T = 0,
4673 .tmrd = 6, .tmrd_05T = 1,
4674 .tmrwckel = 8, .tmrwckel_05T = 1,
4675 .tpde = 2, .tpde_05T = 1,
4676 .tpdx = 1, .tpdx_05T = 1,
4677 .tmrri = 12, .tmrri_05T = 0,
4678 .trrd = 2, .trrd_05T = 0,
4679 .tfaw = 0, .tfaw_05T = 0,
4680 .tr2w_odt_off = 3, .tr2w_odt_off_05T = 0,
4681 .tr2w_odt_on = 5, .tr2w_odt_on_05T = 0,
4682 .txrefcnt = 115,
4683 .wckrdoff = 12, .wckrdoff_05T = 0,
4684 .wckwroff = 8, .wckwroff_05T = 0,
4685 .tzqcs = 34,
4686 .xrtw2w_odt_off = 6,
4687 .xrtw2w_odt_on = 9,
4688 .xrtw2r_odt_off_otf_off = 3,
4689 .xrtw2r_odt_on_otf_off = 3,
4690 .xrtw2r_odt_off_otf_on = 3,
4691 .xrtw2r_odt_on_otf_on = 3,
4692 .xrtr2w_odt_off = 8,
4693 .xrtr2w_odt_on = 9,
4694 .xrtr2r_odt_off = 8,
4695 .xrtr2r_odt_on = 8,
4696 .xrtw2w_odt_off_wck = 7,
4697 .xrtw2w_odt_on_wck = 9,
4698 .xrtw2r_odt_off_wck = 6,
4699 .xrtw2r_odt_on_wck = 7,
4700 .xrtr2w_odt_off_wck = 11,
4701 .xrtr2w_odt_on_wck = 11,
4702 .xrtr2r_wck = 10,
4703 .tr2mrr = 2,
4704 .hwset_mr2_op = 45,
4705 .hwset_mr13_op = 216,
4706 .hwset_vrcg_op = 208,
4707 .vrcgdis_prdcnt = 40,
4708 .lp5_cmd1to2en = 0,
4709 .trtpd = 12, .trtpd_05T = 1,
4710 .twtpd = 12, .twtpd_05T = 0,
4711 .tmrr2w = 15,
4712 .ckeprd = 4,
4713 .ckelckcnt = 3,
4714 .tcsh_cscal = 3,
4715 .tcacsh = 2,
4716 .tcsh = 5,
4717 .trcd_derate = 8, .trcd_derate_05T = 0,
4718 .trc_derate = 17, .trc_derate_05T = 0,
4719 .tras_derate = 10, .tras_derate_05T = 0,
4720 .trpab_derate = 7, .trpab_derate_05T = 1,
4721 .trp_derate = 6, .trp_derate_05T = 0,
4722 .trrd_derate = 2, .trrd_derate_05T = 0,
4723 .zqlat2 = 12,
4724
4725 //DQSINCTL, DATLAT aren't in ACTiming excel file
4726 .dqsinctl = 7, .datlat = 15
4727 },
4728 #endif
4729 };
4730 #endif
4731