1 /* Copyright 2024 Advanced Micro Devices, Inc.
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19 * OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * Authors: AMD
22 *
23 */
24
25 #include "common.h"
26 #include "vpe_priv.h"
27 #include "vpe10_cdc_be.h"
28 #include "reg_helper.h"
29
30 #define CTX_BASE cdc_be
31 #define CTX vpe10_cdc_be
32
33 enum mux_sel {
34 MUX_SEL_ALPHA = 0,
35 MUX_SEL_Y_G = 1,
36 MUX_SEL_CB_B = 2,
37 MUX_SEL_CR_R = 3
38 };
39
40 static struct cdc_be_funcs cdc_be_func = {
41 .check_output_format = vpe10_cdc_check_output_format,
42 .program_global_sync = vpe10_cdc_program_global_sync,
43 .program_p2b_config = vpe10_cdc_program_p2b_config,
44 };
45
vpe10_construct_cdc_be(struct vpe_priv * vpe_priv,struct cdc_be * cdc_be)46 void vpe10_construct_cdc_be(struct vpe_priv *vpe_priv, struct cdc_be *cdc_be)
47 {
48 cdc_be->vpe_priv = vpe_priv;
49 cdc_be->funcs = &cdc_be_func;
50 }
51
vpe10_cdc_check_output_format(struct cdc_be * cdc_be,enum vpe_surface_pixel_format format)52 bool vpe10_cdc_check_output_format(struct cdc_be *cdc_be, enum vpe_surface_pixel_format format)
53 {
54 if (vpe_is_32bit_packed_rgb(format))
55 return true;
56 if (vpe_is_fp16(format))
57 return true;
58
59 return false;
60 }
61
vpe10_cdc_program_global_sync(struct cdc_be * cdc_be,uint32_t vupdate_offset,uint32_t vupdate_width,uint32_t vready_offset)62 void vpe10_cdc_program_global_sync(
63 struct cdc_be *cdc_be, uint32_t vupdate_offset, uint32_t vupdate_width, uint32_t vready_offset)
64 {
65 PROGRAM_ENTRY();
66
67 REG_SET_3(VPCDC_BE0_GLOBAL_SYNC_CONFIG, 0, BE0_VUPDATE_OFFSET, vupdate_offset,
68 BE0_VUPDATE_WIDTH, vupdate_width, BE0_VREADY_OFFSET, vready_offset);
69 }
70
vpe10_cdc_program_p2b_config(struct cdc_be * cdc_be,enum vpe_surface_pixel_format format,enum vpe_swizzle_mode_values swizzle,const struct vpe_rect * viewport,const struct vpe_rect * viewport_c)71 void vpe10_cdc_program_p2b_config(struct cdc_be *cdc_be, enum vpe_surface_pixel_format format,
72 enum vpe_swizzle_mode_values swizzle, const struct vpe_rect *viewport,
73 const struct vpe_rect *viewport_c)
74 {
75 uint32_t bar_sel0 = (uint32_t)MUX_SEL_CB_B;
76 uint32_t bar_sel1 = (uint32_t)MUX_SEL_Y_G;
77 uint32_t bar_sel2 = (uint32_t)MUX_SEL_CR_R;
78 uint32_t bar_sel3 = (uint32_t)MUX_SEL_ALPHA;
79 uint32_t p2b_format_sel = 0;
80
81 PROGRAM_ENTRY();
82
83 switch (format) {
84 case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
85 case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888:
86 case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
87 case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
88 case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888:
89 case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888:
90 case VPE_SURFACE_PIXEL_FORMAT_GRPH_XRGB8888:
91 case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888:
92 p2b_format_sel = 0;
93 break;
94 case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
95 case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102:
96 case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
97 case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102:
98 p2b_format_sel = 1;
99 break;
100 case VPE_SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
101 case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F:
102 case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
103 case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F:
104 p2b_format_sel = 2;
105 break;
106 default:
107 VPE_ASSERT(0);
108 break;
109 }
110
111 switch (format) {
112 case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA8888:
113 case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBX8888:
114 case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA1010102:
115 case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBA16161616F:
116 bar_sel3 = (uint32_t)MUX_SEL_CR_R;
117 bar_sel2 = (uint32_t)MUX_SEL_Y_G;
118 bar_sel1 = (uint32_t)MUX_SEL_CB_B;
119 bar_sel0 = (uint32_t)MUX_SEL_ALPHA;
120 break;
121 case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
122 case VPE_SURFACE_PIXEL_FORMAT_GRPH_XBGR8888:
123 case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
124 case VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
125 bar_sel3 = (uint32_t)MUX_SEL_ALPHA;
126 bar_sel2 = (uint32_t)MUX_SEL_CB_B;
127 bar_sel1 = (uint32_t)MUX_SEL_Y_G;
128 bar_sel0 = (uint32_t)MUX_SEL_CR_R;
129 break;
130 case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
131 case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRX8888:
132 case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA1010102:
133 case VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616F:
134 bar_sel3 = (uint32_t)MUX_SEL_CB_B;
135 bar_sel2 = (uint32_t)MUX_SEL_Y_G;
136 bar_sel1 = (uint32_t)MUX_SEL_CR_R;
137 bar_sel0 = (uint32_t)MUX_SEL_ALPHA;
138 break;
139 default:
140 break;
141 }
142
143 REG_SET_5(VPCDC_BE0_P2B_CONFIG, 0, VPCDC_BE0_P2B_XBAR_SEL0, bar_sel0, VPCDC_BE0_P2B_XBAR_SEL1,
144 bar_sel1, VPCDC_BE0_P2B_XBAR_SEL2, bar_sel2, VPCDC_BE0_P2B_XBAR_SEL3, bar_sel3,
145 VPCDC_BE0_P2B_FORMAT_SEL, p2b_format_sel);
146 }
147